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Commit Graph

162757 Commits

Author SHA1 Message Date
Simon Pilgrim
0b528e55e0 Add additional tests from D45336
llvm-svn: 329427
2018-04-06 17:18:44 +00:00
Simon Pilgrim
fde4f43ae8 Add additional tests from D45366
llvm-svn: 329425
2018-04-06 17:15:56 +00:00
Craig Topper
532cd045ec [X686] Add appropriate ReadAfterLd for the register input to memory forms of ADC/SBB.
llvm-svn: 329424
2018-04-06 17:12:18 +00:00
Simon Pilgrim
425c9cca39 Strip trailing whitespace. NFCI.
llvm-svn: 329421
2018-04-06 17:01:54 +00:00
Dmitry Preobrazhensky
6ca6fe9e88 [AMDGPU][MC][GFX9] Added instructions *saveexec*, *wrexec* and *bitreplicate*
See bug 36840: https://bugs.llvm.org/show_bug.cgi?id=36840

Differential Revision: https://reviews.llvm.org/D45250

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 329419
2018-04-06 16:35:11 +00:00
Sanjay Patel
9037a0d41e [InstCombine] add test for fsub+fneg with extra use; NFC
llvm-svn: 329418
2018-04-06 16:30:52 +00:00
Craig Topper
c62685daea [X86] Remove InstRWs for basic arithmetic instructions from Sandy Bridge scheduler model.
We can get this right through WriteALU and friends now.

llvm-svn: 329417
2018-04-06 16:29:31 +00:00
Craig Topper
75554e0d19 [X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs
Summary:
This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency.

Apparently we were inconsistent about whether the store has latency or not thus the test changes.

I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5.

Reviewers: RKSimon, andreadb

Reviewed By: andreadb

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45351

llvm-svn: 329416
2018-04-06 16:16:48 +00:00
Craig Topper
7eb4e0e958 [X86] Add an extra store address cycle to WriteRMW in the Sandy Bridge/Broadwell/Haswell/Skylake scheduler model.
Even those the address was calculated for the load, its calculated again for the store.

llvm-svn: 329415
2018-04-06 16:16:46 +00:00
Craig Topper
f9c44a5cf4 [X86] Merge itineraries for CLC, CMC, and STC.
These are very simple flag setting instructions that appear to only be a single uop. They're unlikely to need this separation.

llvm-svn: 329414
2018-04-06 16:16:43 +00:00
Simon Pilgrim
2f45abf7e1 [CostModel][X86] Regenerate bit count cost tests with update_analyze_test_checks.py
llvm-svn: 329413
2018-04-06 16:14:27 +00:00
Sanjay Patel
576349eaa9 [InstCombine] add potential calloc tests and regenerate checks; NFC
D45344 is proposing to remove the use restriction that made the calloc
transform safe, but it doesn't currently address the problematic example 
given inD16337. Add a test to make sure that doesn't break.

llvm-svn: 329412
2018-04-06 16:06:08 +00:00
Simon Pilgrim
a2f6066293 [CostModel][X86] Regenerate vector shuffle cost tests with update_analyze_test_checks.py
llvm-svn: 329410
2018-04-06 16:00:28 +00:00
Mircea Trofin
3e34df885a [GlobalOpt] Fix support for casts in ctors.
Summary:
Fixing an issue where initializations of globals where constructors use
casts were silently translated to 0-initialization.

Reviewers: davidxl, evgeny777

Reviewed By: evgeny777

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45198

llvm-svn: 329409
2018-04-06 15:54:47 +00:00
Dmitry Preobrazhensky
559fcce292 [AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructions
See bug 36839: https://bugs.llvm.org/show_bug.cgi?id=36839

Differential Revision: https://reviews.llvm.org/D45249

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 329408
2018-04-06 15:48:39 +00:00
Simon Pilgrim
b4db0687f3 [CostModel][X86] Regenerate bswap/bitreverse cost tests with update_analyze_test_checks.py
llvm-svn: 329407
2018-04-06 15:46:26 +00:00
Pete Couperus
9795ca418f [ARC] Add <.f> suffix for F32_GEN4_{DOP|SOP}.
Add disassembler support for instructions which writeback STATUS32.
https://reviews.llvm.org/D45148

Patch by Yan Luo! (Yan.Luo2@synopsys.com)

llvm-svn: 329404
2018-04-06 15:43:11 +00:00
Andrea Di Biagio
917f5d5fcd [llvm-mca] Do not separate iterations with a newline in the timeline view.
Also, update a few tests to minimize the diff in D45369.
No functional change intended.

llvm-svn: 329403
2018-04-06 15:30:02 +00:00
Simon Pilgrim
36a030d2d0 [CostModel][X86] Regenerate integer extension/truncation cost tests with update_analyze_test_checks.py
llvm-svn: 329402
2018-04-06 15:28:26 +00:00
Simon Pilgrim
d6029433e1 [CostModel][X86] Regenerate integer division/remainder tests with update_analyze_test_checks.py
llvm-svn: 329401
2018-04-06 15:23:26 +00:00
Simon Pilgrim
ddd3b968c4 [CostModel][X86] Regenerate vector shift cost tests with update_analyze_test_checks.py
llvm-svn: 329400
2018-04-06 15:14:34 +00:00
Simon Pilgrim
7d204eacbd [CostModel][X86] Regenerate int<->fp cost tests with update_analyze_test_checks.py
llvm-svn: 329398
2018-04-06 15:12:36 +00:00
Dmitry Preobrazhensky
4ab10f3f40 [AMDGPU][MC][GFX9] Added s_dcache_discard* instructions
See bug 36838: https://bugs.llvm.org/show_bug.cgi?id=36838

Differential Revision: https://reviews.llvm.org/D45247

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 329397
2018-04-06 15:08:42 +00:00
Chad Rosier
50b613bff2 [LoopUnroll] Make LoopPeeling respect the AllowPeeling preference.
The SimpleLoopUnrollPass isn't suppose to perform loop peeling.

Differential Revision: https://reviews.llvm.org/D45334

llvm-svn: 329395
2018-04-06 13:57:21 +00:00
Philip Pfaffe
11b24c502b Followup for r329293: Temporarily disable the breaking test on windows.
This test is failing on windows bots. Disable it temporarily to unbreak
the windows bots.

llvm-svn: 329393
2018-04-06 13:39:16 +00:00
Pavel Labath
d1a1d06f8f DWARFVerifier: validate information in name index entries
Summary:
This patch add checks to verify that the information in the name index
entries is consistent with the debug_info section. Specifically, we
check that entries point to valid DIEs, and their names, tags, and
compile units match the information in the debug_info sections.

These checks are only run if the previous checks did not find any errors
in the name index headers. Attempting to proceed with the checks anyway
would likely produce a lot of spurious errors and the verification code
would need to be very careful to avoid crashing.

I also add a couple of more checks to the abbreviation-validation code
to verify that some attributes are always present (an index without a
DW_IDX_die_offset attribute is fairly useless).

The entry verification works only on indexes without any type units - I
haven't attempted to extend it to type units, as we don't even have a
DWARF v5-compatible type unit generator at the moment.

Reviewers: JDevlieghere, aprantl, dblaikie

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45323

llvm-svn: 329392
2018-04-06 13:34:12 +00:00
Simon Pilgrim
9b724910b4 [UpdateTestChecks] Add update_analyze_test_checks.py for cost model analysis generation
The script allows the auto-generation of checks for cost model tests to speed up their creation and help improve coverage, which will help a lot with PR36550.

If the need arises we can add support for other analyze passes as well, but the cost models was the one I needed to get done - at the moment it just warns that any other analysis mode is unsupported.

I've regenerated a couple of x86 test files to show the effect.

Differential Revision: https://reviews.llvm.org/D45272

llvm-svn: 329390
2018-04-06 12:36:27 +00:00
Simon Pilgrim
0bed948de8 [X86][SandyBridge] Add (V)DPPS memory fold latencies
Noticed this during D44654

llvm-svn: 329389
2018-04-06 11:25:21 +00:00
Simon Pilgrim
5eff8414e5 [X86][SandyBridge] SBWriteResPair +5cy Memory Folds
As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions.

I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent.

As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests...

Differential Revision: https://reviews.llvm.org/D44654

llvm-svn: 329388
2018-04-06 11:00:51 +00:00
Hans Wennborg
7a9000ce11 Tweak an assert message in the verifier
llvm-svn: 329387
2018-04-06 10:20:19 +00:00
Simon Pilgrim
74915132b6 [X86][SkylakeServer] Merge 2 InstRW entries to the same sched group. NFCI.
llvm-svn: 329386
2018-04-06 10:16:36 +00:00
Hans Wennborg
22ceb3e983 EntryExitInstrumenter: Handle musttail calls
Inserting instrumentation between a musttail call and ret instruction
would create invalid IR. Instead, treat musttail calls as function
exits.

llvm-svn: 329385
2018-04-06 10:14:09 +00:00
Max Kazantsev
cc46df92b4 [NFC] Add missing end of line symbols
llvm-svn: 329383
2018-04-06 09:47:06 +00:00
Francis Visoiu Mistrih
0ba2468ada [MIR] Add support for MachineFrameInfo::LocalFrameSize
MFI.LocalFrameSize was not serialized.

It is usually set from LocalStackSlotAllocation, so if that pass doesn't
run it is impossible do deduce it from the stack objects. Until now, this
information was lost.

llvm-svn: 329382
2018-04-06 08:56:25 +00:00
Pavel Labath
ad86d0ceb5 [debug_loc] Fix typo in DWARFExpression constructor
Summary:
The positions of the DwarfVersion and AddressSize arguments were
reversed, which caused parsing for dwarf opcodes which contained
address-size-dependent operands (such as DW_OP_addr). Amusingly enough,
none of the address-size asserts fired, as dwarf version was always 4,
which is a valid address size.

I ran into this when constructing weird inputs for the DWARF verifier. I
I add a test case as hand-written dwarf -- I am not sure how to trigger
this differently, as having a DW_OP_addr inside a location list is a
fairly non-standard thing to do.

Fixing this error exposed a bug in the debug_loc.dwo parser, which was
always being constructed with an address size of 0. I fix that as well
by following the pattern in the non-dwo parser of picking up the address
size from the first compile unit (which is technically not correct, but
probably good enough in practice).

Reviewers: JDevlieghere, aprantl, dblaikie

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45324

llvm-svn: 329381
2018-04-06 08:49:57 +00:00
Max Kazantsev
c73178a4ac [NFC] Loosen restriction on preheader to fix buildbot
llvm-svn: 329379
2018-04-06 07:23:45 +00:00
Hiroshi Inoue
f85880f8af [PowerPC] allow D-form VSX load/store when accessing FrameIndex without offset
VSX D-form load/store instructions of POWER9 require the offset be a multiple of 16 and a helper`isOffsetMultipleOf` is used to check this.
So far, the helper handles FrameIndex + offset case, but not handling FrameIndex without offset case. Due to this, we are missing opportunities to exploit D-form instructions when accessing an object or array allocated on stack.
For example, x-form store (stxvx) is used for int a[4] = {0}; instead of d-form store (stxv). For larger arrays, D-form instruction is not used when accessing the first 16-byte. Using D-form instructions reduces register pressure as well as instructions.

Differential Revision: https://reviews.llvm.org/D45079

llvm-svn: 329377
2018-04-06 05:41:16 +00:00
Robert Widmann
7c14afae06 [LLVM-C] Fill Out LLVMCallConv
Summary: Bring LLVMCallConv up to date with latest [[ http://llvm.org/doxygen/CallingConv_8h_source.html | CallConv ]]

Reviewers: whitequark, deadalnix

Reviewed By: whitequark

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45347

llvm-svn: 329373
2018-04-06 04:02:39 +00:00
Robert Widmann
3ea76d99f7 [LLVM-C] Audit Inline Assembly APIs for Consistency
Summary:
- Add a missing getter for module-level inline assembly
- Add a missing append function for module-level inline assembly
- Deprecate LLVMSetModuleInlineAsm and replace it with LLVMSetModuleInlineAsm2 which takes an explicit length parameter
- Deprecate LLVMConstInlineAsm and replace it with LLVMGetInlineAsm, a function that allows passing a dialect and is not mis-classified as a constant operation

Reviewers: whitequark, deadalnix

Reviewed By: whitequark

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45346

llvm-svn: 329369
2018-04-06 02:31:29 +00:00
Rafael Espindola
669e2019b6 Update method names in documentation.
They were renamed in r328848.

llvm-svn: 329368
2018-04-06 01:21:48 +00:00
Manoj Gupta
d5f82e9974 Fix lld-x86_64-darwin13 build fails.
Use double braces in std::array initialization
to keep Darwin builders happy.

llvm-svn: 329363
2018-04-05 23:23:29 +00:00
Sanjay Patel
5d3b82944d [InstCombine] FP: Z - (X - Y) --> Z + (Y - X)
This restores what was lost with rL73243 but without
re-introducing the bug that was present in the old code.

Note that we already have these transforms if the ops are 
marked 'fast' (and I assume that's happening somewhere in
the code added with rL170471), but we clearly don't need 
all of 'fast' for these transforms.

llvm-svn: 329362
2018-04-05 23:21:15 +00:00
Sanjay Patel
fb0967ea63 [InstCombine] add FP tests for Z - (X - Y); NFC
A fold for this pattern was removed at rL73243 to fix PR4374:
https://bugs.llvm.org/show_bug.cgi?id=4374
...and apparently there were no tests that went with that fold.

llvm-svn: 329360
2018-04-05 22:56:54 +00:00
Manoj Gupta
2ed12ef489 Attempt to fix Mips breakages.
Summary:
Replace ArrayRefs by actual std::array objects so that there are
no dangling references.

Reviewers: rsmith, gkistanova

Subscribers: sdardis, arichardson, llvm-commits

Differential Revision: https://reviews.llvm.org/D45338

llvm-svn: 329359
2018-04-05 22:47:25 +00:00
Zvi Rackover
a292d6561e X86 Tests: Add a case for combining sdiv by a splatted pow2 negative. NFC.
Noticed test was missing while working on D42479.

llvm-svn: 329356
2018-04-05 21:57:20 +00:00
Lang Hames
d867d186f3 [RuntimeDyld][PowerPC] Add a test case for r329335.
Checks that calls to different sections go to the function's global entry point,
rather than the local one.

llvm-svn: 329355
2018-04-05 21:56:55 +00:00
Craig Topper
731a02af04 [X86] Separate CDQ and CDQE in the scheduler model.
According to Agner's data, CDQE is closer to CWDE.

llvm-svn: 329354
2018-04-05 21:56:19 +00:00
Mandeep Singh Grang
c7309ec209 [IR] Change std::sort to llvm::sort in response to r327219
r327219 added wrappers to std::sort which randomly shuffle the container before
sorting.  This will help in uncovering non-determinism caused due to undefined
sorting order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of
std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to
llvm::sort.  Refer D44363 for a list of all the required patches.

llvm-svn: 329353
2018-04-05 21:52:24 +00:00
Craig Topper
af54c985ed [X86] Add MOVZPQILo2PQIrr to the Sandy Bridge scheduler model
llvm-svn: 329351
2018-04-05 21:40:32 +00:00
Sanjay Patel
3965f2af89 [InstCombine] nsz: -(X - Y) --> Y - X
This restores part of the fold that was removed with rL73243 (PR4374).

llvm-svn: 329350
2018-04-05 21:37:17 +00:00