Evan Cheng
91e719a6a1
Cast MO.getImm() to unsigned before comparing with an unsigned limit.
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llvm-svn: 81318
2009-09-09 06:05:16 +00:00
Duncan Sands
598fe699d0
Remove some not-really-used variables, as warned
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about by icc (#593 , partial). Patch by Erick Tryzelaar.
llvm-svn: 81115
2009-09-06 12:41:19 +00:00
Chris Lattner
db2965c71f
remove various std::ostream version of printing methods from
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MachineInstr and MachineOperand. This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)
llvm-svn: 79813
2009-08-23 03:41:05 +00:00
Benjamin Kramer
a8760e3e5a
Fix use after free in Thumb2SizeReduction (PR4707). A MachineInstr was used after erasure.
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llvm-svn: 79189
2009-08-16 11:56:42 +00:00
Evan Cheng
9d351a7246
Turn on if-conversion for thumb2.
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llvm-svn: 79084
2009-08-15 07:59:10 +00:00
Evan Cheng
45d6a21e21
Shrink ADR and LDR from constantpool late during constantpool island pass.
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llvm-svn: 78970
2009-08-14 00:32:16 +00:00
Evan Cheng
9199f62b3d
PredCC is meant to be 2 bits wide, like PredCC1.
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llvm-svn: 78829
2009-08-12 18:35:50 +00:00
Evan Cheng
c369ccbe83
Shrink Thumb2 movcc instructions.
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llvm-svn: 78790
2009-08-12 05:17:19 +00:00
Evan Cheng
65f3e466df
Shrink ADDS, ADC, RSB, and SUBS.
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llvm-svn: 78776
2009-08-12 01:49:45 +00:00
Evan Cheng
a29ee9f509
Shrinkify Thumb2 r = add sp, imm.
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llvm-svn: 78745
2009-08-11 23:00:31 +00:00
Evan Cheng
783028063e
Shrinkify Thumb2 load / store multiple instructions.
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llvm-svn: 78717
2009-08-11 21:11:32 +00:00
Evan Cheng
249f07cf57
Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions.
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llvm-svn: 78659
2009-08-11 09:37:40 +00:00
Evan Cheng
434a66fa9b
Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to
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match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.
llvm-svn: 78658
2009-08-11 08:52:18 +00:00
Evan Cheng
0a08d1bb9c
Watch out for empty BB.
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llvm-svn: 78562
2009-08-10 08:10:13 +00:00
Evan Cheng
1ecffadc8d
rev, rev16, and revsh do not set CPSR.
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llvm-svn: 78561
2009-08-10 07:58:45 +00:00
Evan Cheng
87030de948
Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.
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llvm-svn: 78560
2009-08-10 07:20:37 +00:00
Evan Cheng
e76bc4a520
CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.
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llvm-svn: 78559
2009-08-10 06:57:42 +00:00
Evan Cheng
ad380aa97a
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
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llvm-svn: 78550
2009-08-10 02:37:24 +00:00
Evan Cheng
390e1927bf
Add support to convert 32-bit instructions to 16-bit non-two-address ones.
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llvm-svn: 78540
2009-08-09 19:17:19 +00:00
Evan Cheng
d19807e327
Add a skeleton Thumb2 instruction size reduction pass.
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llvm-svn: 78456
2009-08-08 03:21:23 +00:00
