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Commit Graph

7518 Commits

Author SHA1 Message Date
Bill Wendling
03e6a05f0f Fixed now.
llvm-svn: 78042
2009-08-04 03:46:54 +00:00
Rafael Espindola
bca6e956fb Add test for PR4678
llvm-svn: 78040
2009-08-04 03:44:37 +00:00
Bill Wendling
c144416738 XFAIL for the moment.
llvm-svn: 78038
2009-08-04 03:40:47 +00:00
Devang Patel
5312364dd4 Constants and Metadata share ValueList. This means they must be emitted interleaved (using appropriate BLOCK_IDs) otherwise ValuePtrs index gets out of sync.
llvm-svn: 78033
2009-08-04 02:26:56 +00:00
Evan Cheng
817618d570 Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
llvm-svn: 78030
2009-08-04 01:41:15 +00:00
Dan Gohman
aba682a290 Add -disable-output. Thanks Bill!
llvm-svn: 78009
2009-08-03 22:24:22 +00:00
Dan Gohman
39f93f6443 Add a new Constant::getIntegerValue helper function, and convert a
few places in InstCombine to use it, to fix problems handling pointer
types. This fixes the recent llvm-gcc bootstrap error.

llvm-svn: 78005
2009-08-03 22:07:33 +00:00
Bob Wilson
eb3b616a7e Lower CONCAT_VECTOR during legalization instead of matching it during isel.
Add a testcase.

llvm-svn: 77992
2009-08-03 20:36:38 +00:00
Jakob Stoklund Olesen
1b274fd5f0 Fix Bug 4657: register scavenger asserts with subreg lowering
When LowerSubregsInstructionPass::LowerInsert eliminates an INSERT_SUBREG
instriction because it is an identity copy, make sure that the same registers
are alive before and after the elimination.

When the super-register is marked <undef> this requires inserting an
IMPLICIT_DEF instruction to make sure the super register is live.

Fix a related bug where a kill flag on the inserted sub-register was not transferred properly.

Finally, clear the undef flag in MachineInstr::addRegisterKilled. Undef implies dead and kill implies live, so they cant both be valid.

llvm-svn: 77989
2009-08-03 20:08:18 +00:00
Evan Cheng
ff81990e49 Fix a coaelescer bug. If a copy val# is extended to eliminate a non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy.
llvm-svn: 77967
2009-08-03 08:41:59 +00:00
Anton Korobeynikov
0bac80c138 Unbreak Win64 CC. Step one: honour register save area, fix some alignment and provide a different set of call-clobberred registers.
llvm-svn: 77962
2009-08-03 08:12:53 +00:00
Rafael Espindola
14781bacfe Use movd instead of movq
llvm-svn: 77956
2009-08-03 05:21:05 +00:00
Daniel Dunbar
775da1948b Pass target triple string in to TargetMachine constructor.
This is not just a matter of passing in the target triple from the module;
currently backends are making decisions based on the build and host
architecture. The goal is to migrate to making these decisions based off of the
triple (in conjunction with the feature string). Thus most clients pass in the
target triple, or the host triple if that is empty.

This has one important change in the way behavior of the JIT and llc.

For the JIT, it was previously selecting the Target based on the host
(naturally), but it was setting the target machine features based on the triple
from the module. Now it is setting the target machine features based on the
triple of the host.

For LLC, -march was previously only used to select the target, the target
machine features were initialized from the module's triple (which may have been
empty). Now the target triple is taken from the module, or the host's triple is
used if that is empty. Then the triple is adjusted to match -march.

The take away is that -march for llc is now used in conjunction with the host
triple to initialize the subtarget. If users want more deterministic behavior
from llc, they should use -mtriple, or set the triple in the input module.

llvm-svn: 77946
2009-08-03 04:03:51 +00:00
Rafael Espindola
daefe7aa54 Use movq to move 64 bits in and out of mmx registers.
Fixes PR4669

llvm-svn: 77940
2009-08-03 02:45:34 +00:00
Evan Cheng
27ee95d344 Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well.
llvm-svn: 77939
2009-08-03 02:38:06 +00:00
Andreas Bolka
d713824363 Expand LDA testcases.
llvm-svn: 77926
2009-08-02 23:28:14 +00:00
Richard Osborne
179bf3bdc2 Add extra SEXT pattern.
llvm-svn: 77920
2009-08-02 22:45:24 +00:00
Jakob Stoklund Olesen
0f9cf8a32b Remove unneeded intrinsics from Blackfin backend.
__builtin_bfin_ones does the same as ctpop, so it can be implemented in the front-end.

__builtin_bfin_loadbytes loads from an unaligned pointer with the disalignexcpt instruction. It does the same as loading from a pointer with the low bits masked. It is better if the front-end creates a masked load. We can always instruction select the masked to disalignexcpt+load.

We keep csync/ssync/idle. These intrinsics represent instructions that need workarounds for some silicon revisions. We may even want to convert inline assembler to intrinsics to enable the workarounds.

llvm-svn: 77917
2009-08-02 21:49:05 +00:00
Jakob Stoklund Olesen
9e71890531 Fix issue in regscavenger when scavenging a callee-saved register that has not been spilled.
llvm-svn: 77912
2009-08-02 20:29:41 +00:00
Jakob Stoklund Olesen
fe8f36d66b Never add a kill flag to a constrained physical register in a two-addr instruction.
llvm-svn: 77906
2009-08-02 19:13:03 +00:00
Jakob Stoklund Olesen
a726715be6 Scavenger asserts.
Allow imp-def and imp-use of anything in the scavenger asserts, just like the machine code verifier.
Allow redefinition of a sub-register of a live register.

llvm-svn: 77904
2009-08-02 18:28:41 +00:00
Jakob Stoklund Olesen
23ad8d1848 Add some basic blackfin intrinsics.
llvm-svn: 77903
2009-08-02 18:28:11 +00:00
Jakob Stoklund Olesen
5c6e03f669 Inline assembly support for Blackfin.
We use the same constraints as GCC, including those that are slightly insane for inline assembler.

llvm-svn: 77899
2009-08-02 17:39:17 +00:00
Jakob Stoklund Olesen
e7eb74ef39 Analog Devices Blackfin back-end.
Generate code for the Blackfin family of DSPs from Analog Devices:

  http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html
  
We aim to be compatible with the exsisting GNU toolchain found at:

  http://blackfin.uclinux.org/gf/project/toolchain
  
The back-end is experimental.

llvm-svn: 77897
2009-08-02 17:32:10 +00:00
Evan Cheng
3c2d9a0698 Test both darwin and linux.
llvm-svn: 77852
2009-08-02 02:54:34 +00:00
Chris Lattner
1e3d2247ba switch to filecheck format
llvm-svn: 77841
2009-08-02 00:32:26 +00:00
Chris Lattner
e1cc2c27b3 fix a problem Eli noticed where we would compile the attached ptrtoint
to:

.quad X

even on a 32-bit system, where X is not 64-bits.  There isn't much that
we can do here, so we just print:

.quad	((X) & 4294967295)

instead.

llvm-svn: 77818
2009-08-01 22:25:12 +00:00
Dan Gohman
512a0d9f42 Add nounwind to this test.
llvm-svn: 77792
2009-08-01 19:11:04 +00:00
Eli Friedman
cd4d9ff7fa Hack to make this test work on platforms which aren't Macs. Fixing this
myself because I'm getting tired of seeing the red buildbots, which have 
been red since 5:30PM PDT last night.

Proposed supplement to developer policy: committers should make sure to 
be around to watch for buildbot failures after committing.

llvm-svn: 77785
2009-08-01 16:37:18 +00:00
Evan Cheng
b9b4b9aa15 Workaround a couple of Darwin assembler bugs.
llvm-svn: 77781
2009-08-01 06:13:52 +00:00
Daniel Dunbar
c4efea5c56 Avoid a problem with ulimit on Solaris & friends, patch by Edward O'Callaghan!
llvm-svn: 77767
2009-08-01 03:37:54 +00:00
Evan Cheng
c165700a7f Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
llvm-svn: 77764
2009-08-01 01:43:45 +00:00
Daniel Dunbar
7fd7e31119 llvm-mc: More quoted identifier support.
llvm-svn: 77761
2009-08-01 00:48:30 +00:00
Evan Cheng
5ef6928dff Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.

llvm-svn: 77756
2009-08-01 00:16:10 +00:00
Daniel Dunbar
39929d9343 llvm-mc: Add -triple, and fix some typos
llvm-svn: 77750
2009-07-31 23:13:12 +00:00
Daniel Dunbar
a848745eb4 llvm-mc: Fix .s output to quote section & symbol names when necessary.
llvm-svn: 77749
2009-07-31 23:04:32 +00:00
Daniel Dunbar
99d279978e llvm-mc: A few more parsing / match tweaks.
- Operands which are just a label should be parsed as immediates, not memory
   operands (from the assembler perspective).

 - Match a few more flavors of immediates.

 - Distinguish match functions for memory operands which don't take a segment
   register.

 - We match the .s for "hello world" now!

llvm-svn: 77745
2009-07-31 22:22:54 +00:00
David Greene
543296ed84 Simplify operand padding by keying off tabs in the asm stream. If
padding is disabled, tabs get replaced by spaces except in the case of
the first operand, where the tab is output to line up the operands after
the mnemonics.

Add some better comments and eliminate redundant code.

Fix some testcases to not assume tabs.

llvm-svn: 77740
2009-07-31 21:57:10 +00:00
Daniel Dunbar
e150b07b71 llvm-mc: Support quoted identifiers.
- Uses MCAsmToken::getIdentifier which returns the (sub)string representing the
   meaningfull contents a string or identifier token.

 - Directives aren't done yet.

llvm-svn: 77739
2009-07-31 21:55:09 +00:00
Daniel Dunbar
3c72ed6449 llvm-mc/X86: Sketch match functions for immediates and memory operands.
Also, change scale value to always be 1 when unspecified to machine MachineInst
encoding.

llvm-svn: 77728
2009-07-31 20:53:16 +00:00
Eli Friedman
7bb0485237 PR4662: Fix a crash introduced by the recent LLVMContext changes.
llvm-svn: 77716
2009-07-31 19:36:47 +00:00
Chris Lattner
75b7692e66 switch off of 'Section' onto MCSection. We're not properly using
MCSection subclasses yet, but this is a step in the right direction.

llvm-svn: 77708
2009-07-31 18:48:30 +00:00
Evan Cheng
0c9705feed Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.

llvm-svn: 77705
2009-07-31 18:35:56 +00:00
Chris Lattner
85a3632c7a fix PR4650: we only track sizes for certain objects, so only put something
into the mergable section if it is one of our special cases.  This could
obviously be improved, but this is the minimal fix and restores us to the
previous behavior.

llvm-svn: 77679
2009-07-31 16:17:13 +00:00
Daniel Dunbar
813b35a4b7 Add this test back, the check pattern was too strict.
llvm-svn: 77662
2009-07-31 03:11:49 +00:00
Daniel Dunbar
ed28c20ca7 Remove this test while I figure out why it is failing.
llvm-svn: 77659
2009-07-31 02:46:36 +00:00
Daniel Dunbar
41639473ed llvm-mc: Match a few X86 instructions.
- This is "experimental" code, I am feeling my way around and working out the
   best way to do things (and learning tblgen in the process). Comments welcome,
   but keep in mind this stuff will change radically.

 - This is enough to match "subb" and friends, but not much else. The next step is to
   automatically generate the matchers for individual operands.

llvm-svn: 77657
2009-07-31 02:32:59 +00:00
Evan Cheng
c9f31ae969 When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.
llvm-svn: 77642
2009-07-30 23:29:25 +00:00
Devang Patel
c3f4aa73cc Do not use abbrev while writing NamedMDNode name.
llvm-svn: 77637
2009-07-30 23:06:35 +00:00
David Goodwin
62efc71b9f Darwin assembler now recognizes "orn", so remove workaround.
llvm-svn: 77627
2009-07-30 21:51:41 +00:00