RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-22 04:22:57 +02:00
Code Issues Projects Releases Wiki Activity
49,791 Commits 4 Branches 5 Tags 704 MiB
87372c0978
Commit Graph

33 Commits

Author SHA1 Message Date
Evan Cheng
29fe8806d5 In thumb mode, r7 is used as frame register. This fixes pr4681. 
llvm-svn: 78086
 2009-08-04 18:46:17 +00:00
Evan Cheng
fabbd6219a Add VFP3 D registers to the DPR register class. 
llvm-svn: 77521
 2009-07-29 23:03:41 +00:00
Evan Cheng
2e2a1cbab7 Fix a obvious copy-n-paste bug. 
llvm-svn: 76727
 2009-07-22 06:12:40 +00:00
Evan Cheng
2f6b299d6f Model fpscr to prevent fcmped / fcmpezs etc from being deleted. 
llvm-svn: 76390
 2009-07-20 02:12:31 +00:00
Bob Wilson
a8d7dde3ce Fix an obvious copy-and-paste error. 
llvm-svn: 75566
 2009-07-14 00:23:44 +00:00
Bob Wilson
4c76b1c7fc Revert 75309. 
llvm-svn: 75562
 2009-07-14 00:01:42 +00:00
Bob Wilson
88593195a0 Add superclasses of ARM Neon quad registers. The Q2PR class contains pairs of 
quad registers and the Q4PR class holds sets of 4 quad registers.

llvm-svn: 75309
 2009-07-10 23:09:06 +00:00
Bob Wilson
6db76aaf10 Add support for ARM's Advanced SIMD (NEON) instruction set. 
This is still a work in progress but most of the NEON instruction set
is supported.

llvm-svn: 73919
 2009-06-22 23:27:02 +00:00
Bob Wilson
0c2c5f65e2 For Darwin on ARMv6 and newer, make register r9 available for use as a 
caller-saved register.

llvm-svn: 73901
 2009-06-22 21:01:46 +00:00
Evan Cheng
7426d278ae Remove UseThumbBacktraces. Just check if subtarget is darwin. 
llvm-svn: 73734
 2009-06-18 23:14:30 +00:00
Anton Korobeynikov
d08df21f36 The attached patches implement most of the ARM AAPCS-VFP hard float 
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.

Patch by Sandeep Patel!

llvm-svn: 73095
 2009-06-08 22:53:56 +00:00
Evan Cheng
ea31ec569b Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then. 
llvm-svn: 72955
 2009-06-05 19:08:58 +00:00
Jim Grosbach
e2b20a3526 PR2985 / <rdar://problem/6584986> 
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.

llvm-svn: 68545
 2009-04-07 20:34:09 +00:00
Dan Gohman
cabaec582f Rename MRegisterInfo to TargetRegisterInfo. 
llvm-svn: 46930
 2008-02-10 18:45:23 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Anton Korobeynikov
8e8473c783 Use TableGen to emit information for dwarf register numbers. 
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,

llvm-svn: 43997
 2007-11-11 19:50:10 +00:00
Evan Cheng
3d2cfd8bb1 Added ARM::CPSR to represent ARM CPSR status register. 
llvm-svn: 37897
 2007-07-05 07:17:13 +00:00
Evan Cheng
20c6a03b60 Specify S registers as D registers' sub-registers. 
llvm-svn: 36280
 2007-04-20 21:20:10 +00:00
Evan Cheng
393fd04eb4 Change register allocation order to Dale's suggestion. 
llvm-svn: 35021
 2007-03-08 02:56:40 +00:00
Evan Cheng
493960579f ARM always use register scavenger. No longer reserves R12. 
llvm-svn: 34999
 2007-03-07 02:46:23 +00:00
Evan Cheng
db591ecaa8 Make requiresRegisterScavenging determination on a per MachineFunction basis. 
llvm-svn: 34711
 2007-02-28 00:59:19 +00:00
Evan Cheng
cfb0f8cfc6 Temporary: make R12 available in ARM mode if RegScavenger is being used. 
llvm-svn: 34709
 2007-02-28 00:22:44 +00:00
Evan Cheng
4357509984 Minor tweak. Allocate r0 to r3 in reverse order, r3 is least likely to be livein to a function. 
llvm-svn: 34701
 2007-02-27 23:03:55 +00:00
Evan Cheng
903e98b477 Comment. 
llvm-svn: 33633
 2007-01-29 22:23:02 +00:00
Evan Cheng
d9d93832b0 hasFP() is now a virtual method of MRegisterInfo. 
llvm-svn: 33455
 2007-01-23 00:57:47 +00:00
Evan Cheng
a6803554ab Clean up ARM PEI code. 
llvm-svn: 33389
 2007-01-20 02:09:25 +00:00
Evan Cheng
c6e1d453d3 ARM backend contribution from Apple. 
llvm-svn: 33353
 2007-01-19 07:51:42 +00:00
Rafael Espindola
99322ef58c initial support for frame pointers 
llvm-svn: 31197
 2006-10-26 13:31:26 +00:00
Rafael Espindola
36c3e0028b fix the names of the 64bit fp register 
initial support for returning 64bit floating point numbers

llvm-svn: 30692
 2006-10-02 19:30:56 +00:00
Rafael Espindola
1b39270c95 add floating point registers 
implement SINT_TO_FP

llvm-svn: 30673
 2006-09-29 21:20:16 +00:00
Chris Lattner
db290f7479 Constify some methods. Patch provided by Anton Vayvod, thanks! 
llvm-svn: 29756
 2006-08-17 22:00:08 +00:00
Rafael Espindola
14a59f5b6e initial implementation of ARMRegisterInfo::eliminateFrameIndex 
fixes test/Regression/CodeGen/ARM/ret_arg5.ll

llvm-svn: 28854
 2006-06-18 00:08:07 +00:00
Rafael Espindola
dd49dfc0df added a skeleton of the ARM backend 
llvm-svn: 28301
 2006-05-14 22:18:28 +00:00