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Commit Graph

103543 Commits

Author SHA1 Message Date
Daniel Sanders
883f9833f0 [mips][mips64r6] Add align and dalign
Summary: Depends on D3689

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D3728

llvm-svn: 208872
2014-05-15 12:06:36 +00:00
Tim Northover
4ba95d4483 TableGen/ARM64: print aliases even if they have syntax variants.
To get at least one use of the change (and some actual tests) in with its
commit, I've enabled the AArch64 & ARM64 NEON mov aliases.

llvm-svn: 208867
2014-05-15 11:16:32 +00:00
Tim Northover
83bd592b77 ARM64: add correct vector registers during asm parsing
Previously, we ignored the difference between V64 and V128 when parsing
assembly: they both got mapped to registers in the FPR128 class. This is
basically harmless at the moment because they both print and encode the same
way. However, it will affect the printing of aliases.

llvm-svn: 208866
2014-05-15 11:16:19 +00:00
Bradley Smith
8301057544 [ARM64] Improve load/store diagnostics and forbid 32-bit register addresses
llvm-svn: 208864
2014-05-15 11:08:30 +00:00
Bradley Smith
c77dfa4453 [ARM64] Parse fixed vector lanes properly so that diagnostics can be emitted
llvm-svn: 208863
2014-05-15 11:07:57 +00:00
Bradley Smith
ffae33a2db [ARM64] Add/Fixup diagnostics for floating point immediates
llvm-svn: 208862
2014-05-15 11:07:28 +00:00
Bradley Smith
5033c221c9 [ARM64] Add condition code operand type such that proper diagnostics can be emitted
llvm-svn: 208861
2014-05-15 11:06:51 +00:00
Bradley Smith
b8ba322e07 [ARM64] Add more simple diagnostics for immediate/shift ranges
llvm-svn: 208860
2014-05-15 11:06:16 +00:00
Daniel Sanders
17f37b6f3f [mips][mips64r6] Add addiupc, aluipc, and auipc
Summary:
No support for symbols in place of the immediate yet since it requires new
relocations.

Depends on D3671

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3689

llvm-svn: 208858
2014-05-15 10:45:58 +00:00
Daniel Sanders
f29be03643 [mips][mips64r6] Add aui, daui, dahi, and dati
Summary: Depends on D3671

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3759

llvm-svn: 208857
2014-05-15 10:27:19 +00:00
Chandler Carruth
0d35e1f8fc Teach the constant folder to look through bitcast constant expressions
much more effectively when trying to constant fold a load of a constant.
Previously, we only handled bitcasts by trying to find a totally generic
byte representation of the constant and use that. Now, we look through
the bitcast to see what constant we might fold the load into, and then
try to form a constant expression cast of the found value that would be
equivalent to loading the value.

You might wonder why on earth this actually matters. Well, turns out
that the Itanium ABI causes us to create a single array for a vtable
where the first elements are virtual base offsets, followed by the
virtual function pointers. Because the array is homogenous the element
type is consistently i8* and we inttoptr the virtual base offsets into
the initial elements.

Then constructors bitcast these pointers to i64 pointers prior to
loading them. Boom, no more constant folding of virtual base offsets.
This is the first fix to LLVM to address the *insane* performance Eric
Niebler discovered with Clang on his range comprehensions[1]. There is
more to come though, this doesn't *really* fix the problem fully.

[1]: http://ericniebler.com/2014/04/27/range-comprehensions/

llvm-svn: 208856
2014-05-15 09:56:28 +00:00
Daniel Sanders
ca9cbc1b8b [mips][mips64r6] Test that branch likelies are not accepted on MIPS64r6.
Summary:
They aren't implemented for any ISA at the moment.

Depends on D3670

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3671

llvm-svn: 208855
2014-05-15 09:47:43 +00:00
Dinesh Dwivedi
2381ae3d5b Reverting r208848, reason: build failure: sanitizer-x86_64-linux-bootstrap/builds/3399
llvm-svn: 208852
2014-05-15 08:22:55 +00:00
Dinesh Dwivedi
74c9400378 Added instcombine for 'MIN(MIN(A, 27), 93)' and 'MAX(MAX(A, 93), 27)'
MIN(MIN(A, 23), 97) -> MIN(A, 23)
MAX(MAX(A, 97), 23) -> MAX(A, 97)

Differential Revision: http://reviews.llvm.org/D3629

llvm-svn: 208849
2014-05-15 06:13:40 +00:00
Dinesh Dwivedi
de41090110 Added inst combine transforms for single bit tests from Chris's note
if ((x & C) == 0) x |= C becomes x |= C
if ((x & C) != 0) x ^= C becomes x &= ~C
if ((x & C) == 0) x ^= C becomes x |= C
if ((x & C) != 0) x &= ~C becomes x &= ~C
if ((x & C) == 0) x &= ~C becomes nothing

Z3 Verifications code for above transform
http://rise4fun.com/Z3/Pmsh

Differential Revision: http://reviews.llvm.org/D3717

llvm-svn: 208848
2014-05-15 06:01:33 +00:00
Jonathan Roelofs
9a09decd36 Fix some dyslexia in an assert message
llvm-svn: 208842
2014-05-15 02:24:50 +00:00
Alp Toker
18115693f7 Fix typos
llvm-svn: 208839
2014-05-15 01:52:21 +00:00
Jiangning Liu
ecd097d587 [ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out argument stack from callee.
llvm-svn: 208837
2014-05-15 01:33:17 +00:00
Eric Christopher
e4c742a33c Remove unused functions setting MCOptions from TargetMachine.
llvm-svn: 208835
2014-05-15 01:25:04 +00:00
Eric Christopher
ac8b0b7c03 Unify command line handling of MCTargetOptions and remove extra
options and code. No functional change.

llvm-svn: 208833
2014-05-15 01:10:50 +00:00
Eric Christopher
f26f61b12b Move the TargetMachine MC options to MCTargetOptions. No functional
change.

llvm-svn: 208832
2014-05-15 01:08:00 +00:00
David Majnemer
809b8a331d InstCombine: Optimize -x s< cst
Summary:
This gets rid of a sub instruction by moving the negation to the
constant when valid.

Reviewers: nicholas

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3773

llvm-svn: 208827
2014-05-15 00:02:20 +00:00
David Blaikie
071f1f0679 DwarfDebug: Don't set frame index locations on abstract variables.
Abstract variables should never have/use locations. In this case the
data wasn't used, so no functional change intended here, just
simplification.

llvm-svn: 208820
2014-05-14 22:51:59 +00:00
David Blaikie
ef32c3bf98 DebugInfo: Sure up subprogram variable list handling with more assertions and fewer conditionals.
Many old tests using prior schemas still had some brokenness here (both
indirect arrays and arrays with single bogus elements). Fixed those up
so they don't hit the new assertions.

Also reduced nesting in some places, etc.

llvm-svn: 208817
2014-05-14 21:52:46 +00:00
David Blaikie
03965d6089 DebugInfo: Assert that a CU's subprogram list contains only subprograms.
llvm-svn: 208816
2014-05-14 21:52:37 +00:00
Kevin Enderby
7558c9cb9b Teach llvm-nm to know about fat archives (aka MachOUniversal files
containing archives).  First step as other tools will be updated next.

llvm-svn: 208812
2014-05-14 21:18:50 +00:00
Jay Foad
e0eac700cb Rename ComputeMaskedBits to computeKnownBits. "Masked" has been
inappropriate since it lost its Mask parameter in r154011.

llvm-svn: 208811
2014-05-14 21:14:37 +00:00
David Majnemer
6098432810 InstSimplify: Optimize signed icmp of -(zext V)
Summary:
We know that -(zext V) will always be <= zero, simplify signed icmps
that have these.

Uncovered using http://www.cs.utah.edu/~regehr/souper/

Reviewers: nicholas

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3754

llvm-svn: 208809
2014-05-14 20:16:28 +00:00
David Blaikie
4e2a4915ae DebugInfo: Do not delay attaching DW_AT_inline attribute to abstract definitions.
This is just unneccessary - we only create abstract definitions when
we're inlining anyway, so there's no reason to delay this to see if
we're going to inline anything.

llvm-svn: 208798
2014-05-14 17:58:53 +00:00
Christian Pirker
7dd3a40e09 ARM-BE: test files for vector argument passing
Reviewed at http://reviews.llvm.org/D3766

llvm-svn: 208793
2014-05-14 16:59:44 +00:00
Christian Pirker
f835f2f7be [ARM64-BE] Fix byte order of CIE and FDE frames for exception handling
Reviewed at http://reviews.llvm.org/D3741

llvm-svn: 208792
2014-05-14 16:51:58 +00:00
Logan Chien
fb407ff21d Fix ARM EHABI when function has landingpad and nounwind.
If the function has the landingpad instruction, then the
handlerdata should be emitted even if the function has
nouwnind attribute.  Otherwise, following code will not
work:

    void test1() noexcept {
      try {
        throw_exception();
      } catch (...) {
        log_unexpected_exception();
      }
    }

Since the cantunwind was incorrectly emitted and the
LSDA is not available.

llvm-svn: 208791
2014-05-14 16:38:30 +00:00
Logan Chien
4b117dbbaf More test case for r208715.
The commit r208166 will cause some regression on ARM EHABI.
This fix has been committed in r208715, and an assertion failure
test case has been committed in r208770.

This commit further extends the unittest so that the actual
value in the handlerdata will be checked.

llvm-svn: 208790
2014-05-14 16:37:32 +00:00
Benjamin Kramer
56a86f3d17 X86: If we have an instruction that sets a flag and a zero test on the input of that instruction try to eliminate the test.
For example
	tzcntl	%edi, %ebx
	testl %edi, %edi
	je	.label

can be rewritten into
	tzcntl	%edi, %ebx
	jb 	.label

A minor complication is that tzcnt sets CF instead of ZF when the input
is zero, we have to rewrite users of the flags from ZF to CF. Currently
we recognize patterns using lzcnt, tzcnt and popcnt.

Differential Revision: http://reviews.llvm.org/D3454

llvm-svn: 208788
2014-05-14 16:14:45 +00:00
Daniel Sanders
6072bf56a8 [mips] Test that IAS for -mcpu=mips5 does not accept MIPS64 insns and -mcpu=mips(5|64) does not accept MIPS64r2
Summary:
To limit the number of tests required, only one 64-bit ISA prior to MIPS64 are tested.

rdhwr has been deliberately left without an ISA annotation for now. This is
because the assembler and CodeGen disagree on when the instruction is
available. Strictly speaking, it is only available in MIPS32r2 and
MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is
necessary for TLS so CodeGen should emit it on older ISA's too.

Depends on D3697

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3698

llvm-svn: 208785
2014-05-14 15:35:03 +00:00
Daniel Sanders
2b18784a55 [mips][mips64r6] Add sel.s and sel.d
Summary:
Also use named constants for common opcode fields.

Depends on D3669

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D3670

llvm-svn: 208784
2014-05-14 15:29:44 +00:00
Tim Northover
0cd4ebc382 ARM64: remove unneeded InstPrinter hacks
Now that TableGen handles aliases, these are unneeded. Hopefully more will be
able to go soon.

llvm-svn: 208781
2014-05-14 14:44:18 +00:00
Evgeniy Stepanov
7fa438812a Regression test for ARM EHABI breakage in r208166.
llvm-svn: 208770
2014-05-14 11:13:31 +00:00
Evgeniy Stepanov
68438f8e17 [asan] Fix compiler warnings.
llvm-svn: 208769
2014-05-14 10:56:19 +00:00
Evgeniy Stepanov
309a0238f8 [asan] Set debug location in ASan function prologue.
Most importantly, it gives debug location info to the coverage callback.

This change also removes 2 cases of unnecessary setDebugLoc when IRBuilder
is created with the same debug location.

llvm-svn: 208767
2014-05-14 10:30:15 +00:00
Sylvestre Ledru
0e85322d85 Update of the documentation: I think we are now happy with Phabricator
llvm-svn: 208764
2014-05-14 09:22:15 +00:00
Serge Pavlov
a4228593ad Fix the case when reordering shuffle and binop produces a constant.
This resolves PR19737.

llvm-svn: 208762
2014-05-14 09:05:09 +00:00
Jay Foad
a704f5fc73 Fix strange typo in markup.
llvm-svn: 208759
2014-05-14 08:10:16 +00:00
Jay Foad
df682f6c8b Update the comments for ComputeMaskedBits, which lost its Mask parameter
in r154011.

llvm-svn: 208757
2014-05-14 08:00:07 +00:00
Simon Atanasyan
9b2d085924 [obj2yaml] Support ELF input format in the obj2yaml tool.
The ELF header e_flags field in the MIPS related test cases handled
incorrectly. The obj2yaml prints too many flags. I will fix that in the
next patches.

The patch reviewed by Michael Spencer and Sean Silva.

llvm-svn: 208752
2014-05-14 05:07:47 +00:00
Saleem Abdulrasool
a39ea3408e ARM: implement support for the UDF mnemonic
The UDF instruction is a reserved undefined instruction space.  The assembler
mnemonic was introduced with ARM ARM rev C.a.  The instruction is not predicated
and the immediate constant is ignored by the CPU.  Add support for the three
encodings for this instruction.

The changes to the invalid instruction test is due to the fact that the invalid
instructions actually overlap with the undefined instruction.  Introduction of
the new instruction results in a partial decode as an undefined sequence.  Drop
the tests as they are invalid instruction patterns anyways.

llvm-svn: 208751
2014-05-14 03:47:39 +00:00
Nick Lewycky
2f1d385135 Optimize integral reciprocal (udiv 1, x and sdiv 1, x) to not use division. This fires exactly once in a clang bootstrap, but covers a few different results from http://www.cs.utah.edu/~regehr/souper/
llvm-svn: 208750
2014-05-14 03:03:05 +00:00
David Blaikie
fac608f99b Recommit r208506: DebugInfo: Include lexical scopes in inlined subroutines.
This was reverted in r208642 due to regressions surrounding file changes
within lexical scopes causing inlining information to be lost.

The issue was in LexicalScopes::getOrCreateInlinedScope, where I was
previously testing "isLexicalBlock" which is false for
"DILexicalBlockFile" (a scope used to represent changes in the current
file name) and assuming it was then a function (breaking out of the
inlined scope path and reaching for the parent non-inlined scopes). By
inverting the condition and testing for "isSubprogram" the correct
behavior is attained.

(also found some weirdness in Clang, see r208742 when reducing this test
case - the resulting test case doesn't apply with the Clang fix, but
I've added a more realistic test case to inline-scopes.ll which does
reproduce the issue and demonstrate the fix)

llvm-svn: 208748
2014-05-14 01:08:28 +00:00
Eric Christopher
935299458d Fix typo in function name.
llvm-svn: 208743
2014-05-14 00:31:15 +00:00
Matt Arsenault
102b7be363 R600/SI: Try to fix BFE operands when moving to VALU
This was broken by r208479

llvm-svn: 208740
2014-05-13 23:45:50 +00:00