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Commit Graph

187526 Commits

Author SHA1 Message Date
Sanjay Patel
ed1d652509 [InstSimplify] add more tests for fcmp+select; NFC
The easy code fix won't catch non-canonical mismatched
constant patterns, so adding extra coverage for those in
case we decide that's important (but seems unlikely).
2019-11-04 08:23:08 -05:00
Ulrich Weigand
ec2ceb39a7 [SystemZ] Add GHC calling convention
This is a special calling convention to be used by the GHC compiler.

Author: Stefan Schulze Frielinghaus
Differential Revision: https://reviews.llvm.org/D69024
2019-11-04 13:45:51 +01:00
Sanjay Patel
bde4223336 [InstSimplify] add more tests for fcmp+select; NFC
The addition of FMF for select allows more folding for these
kinds of patterns.
2019-11-04 07:38:11 -05:00
James Henderson
8d3710516b [llvm-readobj] Change errors to warnings for symbol section name dumping
Also only print each such warning once.

LLVM-style output will now print "<?>" for sections it cannot identify,
e.g. because the section index is invalid. GNU output continues to print
the raw index. In both cases where the st_shndx value is SHN_XINDEX and
the index cannot be looked up in the SHT_SYMTAB_SHNDX section (e.g.
because it is missing), the symbol is printed like other symbols with
st_shndx >= SHN_LORESERVE.

Reviewed by: grimar, MaskRay

Differential Revision: https://reviews.llvm.org/D69671
2019-11-04 12:04:04 +00:00
Simon Pilgrim
05339919c7 [X86] SimplifyDemandedVectorElts - attempt to recombine target shuffle using DemandedElts mask (REAPPLIED)
If we don't demand all elements, then attempt to combine to a simpler shuffle.

At the moment we can only do this if Depth == 0 as combineX86ShufflesRecursively uses Depth to track whether the shuffle has really changed or not - we'll need to change this before we can properly start merging combineX86ShufflesRecursively into SimplifyDemandedVectorElts (see D66004).

This reapplies rL368307 (reverted at rL369167) after the fix for the infinite loop reported at PR43024 was applied at rG3f087e38a2e7b87a5adaaac1c1b61e51220e7ff3
2019-11-04 11:37:57 +00:00
Diogo Sampaio
2e4a9261eb [FIX] Removed duplicated v4f16 and v8f16 declarations
Reviewers: RKSimon, ostannard

Reviewed By: RKSimon

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69795
2019-11-04 11:33:21 +00:00
Luís Marques
8c26258e82 [RISCV] Implement the TargetLowering::getRegisterByName hook
Summary: The hook should work for any RISC-V register. Non-allocatable registers
do not need to be reserved, for the remaining the hook will only succeed
if you pass clang the -ffixed-xX flag. This builds upon D67185, which
currently only allows reserving GPRs.

Reviewers: asb, lenary

Reviewed By: lenary

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69130
2019-11-04 11:23:54 +00:00
David Spickett
7d79fa7e02 [hwasan] Remove lazy thread-initialisation
This was an experiment made possible by a non-standard feature of the
Android dynamic loader.

It required introducing a flag to tell the compiler which ABI was being
targeted.
This flag is no longer needed, since the generated code now works for
both ABI's.

We leave that flag untouched for backwards compatibility. This also
means that if we need to distinguish between targeted ABI's again
we can do that without disturbing any existing workflows.

We leave a comment in the source code and mention in the help text to
explain this for any confused person reading the code in the future.

Patch by Matthew Malcomson

Differential Revision: https://reviews.llvm.org/D69574
2019-11-04 10:58:46 +00:00
Jonas Paulsson
7b87fa876f [SystemZ] Improve handling of huge PC relative immediate offsets.
Demand that an immediate offset to a PC relative address fits in 32 bits, or
else load it into a register and perform a separate add.

Verify in the assembler that such immediate offsets fit the bitwidth.

Even though the final address of a Load Address Relative Long may fit in 32
bits even with a >32 bit offset (depending on where the symbol lives relative
to PC), the GNU toolchain demands the offset by itself to be in range. This
patch adapts the same behavior for llvm.

Review: Ulrich Weigand
https://reviews.llvm.org/D69749
2019-11-04 10:38:18 +01:00
Gil Rapaport
834f30016f [LV] Apply sink-after & interleave-groups as VPlan transformations (NFC)
The sink-after and interleave-group vectorization decisions were so far applied to
VPlan during initial VPlan construction, which complicates VPlan construction – also because of
their inter-dependence. This patch refactors buildVPlanWithRecipes() to construct a simpler
initial VPlan and later apply both these vectorization decisions, in order, as VPlan-to-VPlan
transformations.

Differential Revision: https://reviews.llvm.org/D68577
2019-11-04 10:37:39 +02:00
Pengfei Wang
df586abb79 Set the floating point status register as reserved
Summary:
This patch sets the FPSW (X87 floating-point status register) as a reserved
physical register and fix the test failure caused by [[ https://reviews.llvm.org/D68854| D68854 ]].

Before this patch, some tests will fail because it implicit uses FPSW without
define it. Setting the FPSW as a reserved physical register will skip liveness
analysis because it is always live.

Reviewers: pengfei, craig.topper

Reviewed By: craig.topper

Subscribers: craig.topper, hiraditya, llvm-commits

Patch by LiuChen.

Differential Revision: https://reviews.llvm.org/D69784
2019-11-03 23:14:34 -08:00
Simon Atanasyan
e64d163004 [mips] Move test case for Octeon instructions to cnmips sub-folder. NFC 2019-11-04 00:42:31 +03:00
Simon Atanasyan
aa9f240b3d [mips] Add disassembler tests for octeon CPU. NFC 2019-11-04 00:42:31 +03:00
Simon Atanasyan
e3c076d945 [mips] Add disassembler tests for sigrie instruction. NFC 2019-11-04 00:42:31 +03:00
Simon Pilgrim
19a77aa612 [X86][SSE] combineX86ShufflesRecursively - at Depth==0, only resolve KnownZero if it removes an input.
This stops infinite loops where KnownUndef elements are converted to Zeroable, resulting in KnownZero elements which are then simplified (via SimplifyDemandedElts etc.) back to KnownUndef elements........

Prep fix for PR43024 which will allow rL368307 to be re-applied.
2019-11-03 21:10:47 +00:00
Dávid Bolvanský
9d0db13c58 [SIMachineScheduler] Fixed ''then' statement is equivalent to the 'else' statement.' warning. NFCI. 2019-11-03 20:40:53 +01:00
Dávid Bolvanský
16084049d1 [SILoadStoreOptimizer] Fixed typo. NFCI. 2019-11-03 20:38:29 +01:00
Dávid Bolvanský
f0740e4860 Reland '[InstructionCombining] Fixed null check after dereferencing warning. NFCI.' 2019-11-03 20:34:54 +01:00
Dávid Bolvanský
da3b31f588 Revert "[InstructionCombining] Fixed null check after dereferencing warning. NFCI."
This reverts commit 8308187fd9bfa08ffad0a636d4dd1d25e7de5a76. This exposed a bug.
2019-11-03 20:31:05 +01:00
Dávid Bolvanský
b24c001a38 [SCEV] Fixed 'Uninitialized variable 'ContainsAddRec' used.' warning. NFCI. 2019-11-03 20:29:49 +01:00
Dávid Bolvanský
594534348b [MemorySSA] Fixed null check after dereferencing warning. NFCI. 2019-11-03 20:27:40 +01:00
Dávid Bolvanský
a56c48b307 Revert "[InstructionCompares] Fixed null check after dereferencing warning. NFCI."
This reverts commit b8685cf3042f6a2e129061922bd6b18e3c42258e.
2019-11-03 20:24:01 +01:00
Dávid Bolvanský
e7444d5bce [InstructionCompares] Fixed null check after dereferencing warning. NFCI. 2019-11-03 20:13:45 +01:00
Dávid Bolvanský
cba826f87b [InstructionCombining] Fixed null check after dereferencing warning. NFCI. 2019-11-03 20:10:46 +01:00
Dávid Bolvanský
8b2b0c477f [CHR] Fixed null check after dereferencing warning. NFCI. 2019-11-03 20:06:38 +01:00
Dávid Bolvanský
e805b61e95 [LoopUnrollRuntime] Fixed null check after dereferencing warning. NFCI. 2019-11-03 20:05:18 +01:00
Dávid Bolvanský
8cc5d81aa2 [LoopUnrollAndJam] Fixed null check after dereferencing warning. NFCI. 2019-11-03 20:02:54 +01:00
Dávid Bolvanský
978187ca78 [BitcodeReader] Fixed use after move warnings. NFCI. 2019-11-03 19:45:25 +01:00
Dávid Bolvanský
d27cb45e15 [BitcodeReader] Fixed null check after dereferencing warning. NFCI. 2019-11-03 19:42:11 +01:00
Dávid Bolvanský
60646a4ddc [BitcodeReader] Fixed null pointer dereferencing warning. NFCI. 2019-11-03 19:40:26 +01:00
Dávid Bolvanský
b24639e80e [SelectionDAG] Fixed null check after dereferencing warning. NFCI. 2019-11-03 19:34:03 +01:00
Craig Topper
7486acb77b [opaque pointer types] Add element type argument to IRBuilder CreatePreserveStructAccessIndex and CreatePreserveArrayAccessIndex
Summary:
These were the only remaining users of the GetElementPtrInst::getGEPReturnType
method that gets the element type from the pointer type.

Remove that method since its now dead.

Reviewers: jyknight, t.p.northover, arsenm

Reviewed By: arsenm

Subscribers: wdng, arsenm, arphaman, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D69756
2019-11-03 10:27:18 -08:00
Nico Weber
83efdf102e gn build: (manually) merge 3a399c09 / add76dd3c 2019-11-03 12:52:54 -05:00
Simon Pilgrim
7ca31b1d45 [X86][SSE] combineX86ShufflesRecursively - don't bother merging shuffles with empty roots. NFCI.
This doesn't affect actual codegen, but is a minor refactor toward fixing PR43024 where we need to avoid excess changes (folding zeroables etc.) to the shuffle mask at Depth == 0.
2019-11-03 17:46:00 +00:00
Simon Pilgrim
d8ba6e31b6 [X86] Convert PICStyles::Style to scoped enum class. NFCI.
Fixes MSVC static analyzer warnings about enum safety, this enum performs no integer math so it'd be better to fix its scope.
2019-11-03 17:28:04 +00:00
Bjorn Pettersson
4d274621ba [DebugInfo] Fix for DW_OP_LLVM_fragment in DIExpression::isImplicit()
DIExpression::isImplicit() did not handle DW_OP_LLVM_fragment
correctly. It was scanning the elements in the expression by
iterating from the end. But we do not know the position of
ops unless we iterate from the beginning of the expression,
since DW_OP:s and their operands are stored flat in the expression
list. The old code also assumed that a DW_OP_LLVM_fragment
only occupied one element in the expression list, but it actually
occupies three elements.
2019-11-03 17:37:49 +01:00
Yonghong Song
9028839e94 [BPF] fix a bug in __builtin_preserve_field_info() with FIELD_BYTE_SIZE
During deriving proper bitfield access FIELD_BYTE_SIZE,
function Member->getStorageOffsetInBits() is used to
get llvm IR type storage offset in bits so that
the byte size can permit aligned loads/stores with previously
derived FIELD_BYTE_OFFSET.

The function should only be used with bitfield members and it will
assert if ASSERT is turned on during cmake build.
  Constant *getStorageOffsetInBits() const {
    assert(getTag() == dwarf::DW_TAG_member && isBitField());
    if (auto *C = cast_or_null<ConstantAsMetadata>(getExtraData()))
      return C->getValue();
    return nullptr;
  }

This patch fixed the issue by using Member->isBitField()
directly and a test case is added to cover this missing case.
This issue is discovered when running Andrii's linux kernel CO-RE
tests.

Differential Revision: https://reviews.llvm.org/D69761
2019-11-03 08:18:28 -08:00
Simon Pilgrim
c78d2b2e7d SymbolRecord - fix more uninitialized variable warnings. NFCI. 2019-11-03 11:27:57 +00:00
Simon Pilgrim
ca6a4c4c78 Fix uninitialized variable warnings. NFCI. 2019-11-03 11:23:53 +00:00
Simon Pilgrim
85198c771c Fix line_iterator uninitialized variable warnings. NFCI.
Allows us to auto define the default constructor as well.
2019-11-03 11:20:12 +00:00
Simon Pilgrim
fd5f6041b1 Ensure VPlanPrinter::Depth is initialized to fix static analyzer warning. NFCI. 2019-11-03 11:17:05 +00:00
Simon Pilgrim
41500bf410 Fix uninitialized variable warning. NFCI. 2019-11-03 11:15:55 +00:00
shkzhang
f24f9150a0 [CodeGen] [ExpandReduction] Fix the bug for ExpandReduction() when vector size isn't power of 2
Summary:
For below test case, we will get assert error except for AArch64 and ARM:

declare i8 @llvm.experimental.vector.reduce.and.i8.v3i8(<3 x i8> %a)
define i8 @test_v3i8(<3 x i8> %a) nounwind {
  %b = call i8 @llvm.experimental.vector.reduce.and.i8.v3i8(<3 x i8> %a)
  ret i8 %b
}
In the function getShuffleReduction (), we can see it needs the vector size must be power of 2.

This patch is fix below error when the number of element is not power of 2 for those llvm.experimental.vector.reduce.* function.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D68625
2019-11-02 23:59:12 -04:00
Simon Pilgrim
02298af81b Stop static analyzer warnings about using bitwise operators on booleans. NFCI.
Call each of the rebase_if() calls separately.
2019-11-02 22:40:04 +00:00
Simon Pilgrim
d55a685d43 TargetParserTest - testARMArch - stop bitwise operators on boolean warnings. NFCI.
Ensure the test still runs all target checks but stop the static analyzer warnings.
2019-11-02 22:40:04 +00:00
Fangrui Song
aeb4df5894 CodeGen/DIE.h: prefer the default member initializer to the member initializers in the constructor. NFC 2019-11-02 14:57:50 -07:00
Simon Atanasyan
ab8db1eb99 [mips] Remove trailing spaces. NFC 2019-11-03 00:50:52 +03:00
Simon Atanasyan
bb3e46c8fe [mips] Split long lines in the code. NFC 2019-11-03 00:50:52 +03:00
Simon Pilgrim
50ba5815e2 A15SDOptimizer::getPrefSPRLane - fix null dereference warning. NFCI 2019-11-02 21:49:12 +00:00
Simon Pilgrim
6daaf620de isConditionalBranch/isUnconditionalBranch - use boolean operators. NFCI.
Stop static analyzer warnings about using bitwise operators on booleans.
2019-11-02 21:38:46 +00:00