Jim Grosbach
2c2140a128
ARM assembly parsing allows constant expressions for lane indices.
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llvm-svn: 147028
2011-12-21 01:19:23 +00:00
Jim Grosbach
6bd1044b03
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
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llvm-svn: 147025
2011-12-21 00:38:54 +00:00
Jim Grosbach
7baaa0fc64
ARM .req register name aliases are case insensitive, just like regnames.
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llvm-svn: 147009
2011-12-20 23:11:00 +00:00
Jim Grosbach
ff31b81fe2
Move comment to appropriate place.
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llvm-svn: 147000
2011-12-20 22:26:38 +00:00
Jim Grosbach
8978194025
ARM assembly parsing and encoding for VST2 single-element, double spaced.
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llvm-svn: 146990
2011-12-20 20:46:29 +00:00
Jim Grosbach
8156a5dcee
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
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llvm-svn: 146983
2011-12-20 19:21:26 +00:00
Jason W Kim
139dd49440
First steps in ARM AsmParser support for .eabi_attribute and .arch
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(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)
llvm-svn: 146977
2011-12-20 17:38:12 +00:00
Jim Grosbach
3f5493c136
ARM assembly shifts by zero should be plain 'mov' instructions.
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"mov r1, r2, lsl #0 " should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
llvm-svn: 146937
2011-12-20 00:59:38 +00:00
Jim Grosbach
b1b83d2f58
ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.
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e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117 "
rdar://10603913
llvm-svn: 146925
2011-12-19 23:51:07 +00:00
Jim Grosbach
343f270350
ARM assembly parsing and encoding support for LDRD(label).
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rdar://9932658
llvm-svn: 146921
2011-12-19 23:06:24 +00:00
Jim Grosbach
f9910809c5
ARM VFP pre-UAL mnemonic aliases for fmul[sd].
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llvm-svn: 146892
2011-12-19 19:43:50 +00:00
Jim Grosbach
6e9471925b
ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
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llvm-svn: 146887
2011-12-19 19:02:41 +00:00
Jim Grosbach
f4ca84a7ab
ARM NEON relax parse time diagnostics for alignment specifiers.
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There's more variation that we need to handle. Error checking will need
to be on operand predicates.
llvm-svn: 146884
2011-12-19 18:31:43 +00:00
Jim Grosbach
3ee3c6dc3e
Silence warning.
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llvm-svn: 146686
2011-12-15 21:54:55 +00:00
Jim Grosbach
8ed1253ef3
ARM NEON two-register double spaced register list parsing support.
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llvm-svn: 146685
2011-12-15 21:44:33 +00:00
Jim Grosbach
b09a003fa6
ARM NEON better assembly operand range checking for lane indices of VLD/VST.
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llvm-svn: 146608
2011-12-14 23:35:06 +00:00
Jim Grosbach
75db252aee
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
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llvm-svn: 146605
2011-12-14 23:25:46 +00:00
Jim Grosbach
628ae663ef
ARM assembler support for the target-specific .req directive.
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rdar://10549683
llvm-svn: 146543
2011-12-14 02:16:11 +00:00
Jim Grosbach
089ad574d8
Thumb2 assembler aliases for "mov(shifted register)"
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rdar://10549767
llvm-svn: 146520
2011-12-13 22:45:11 +00:00
Jim Grosbach
bd33fc6efd
ARM LDM/STM system instruction variants.
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rdar://10550269
llvm-svn: 146519
2011-12-13 21:48:29 +00:00
Jim Grosbach
b2547b424c
Thumb2 tweak for ccout handling in RSB parsing.
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llvm-svn: 146516
2011-12-13 21:06:41 +00:00
Jim Grosbach
13d3509445
ARM thumb2 parsing of "rsb rd, rn, #0 ".
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rdar://10549741
llvm-svn: 146515
2011-12-13 20:50:38 +00:00
Jim Grosbach
1738a66371
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
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llvm-svn: 146508
2011-12-13 20:13:48 +00:00
Daniel Dunbar
30d6a45140
LLVMBuild: Remove trailing newline, which irked me.
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llvm-svn: 146409
2011-12-12 19:48:00 +00:00
Jim Grosbach
ece09e5e6b
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
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llvm-svn: 146300
2011-12-10 00:01:02 +00:00
Jim Grosbach
2356c1f141
ARM add some pre-UAL VFP mnemonics for convenience when porting old code.
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llvm-svn: 146296
2011-12-09 23:34:09 +00:00
Jim Grosbach
43cade9bb2
ARM allows '' syntax, not just '#imm' for assembly.
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Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.
llvm-svn: 146285
2011-12-09 22:25:03 +00:00
Jim Grosbach
5f3c519248
ARM convenience aliases for VSQRT.
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llvm-svn: 146201
2011-12-08 22:51:25 +00:00
Jim Grosbach
a33fa8aa88
ARM VSHR implied destination operand form aliases.
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llvm-svn: 146192
2011-12-08 22:06:06 +00:00
Jim Grosbach
01485b7e6e
ARM asm parser, just issue a warning for a duplicate reg in a list.
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For better 'gas' compatibility.
llvm-svn: 146185
2011-12-08 21:34:20 +00:00
Jim Grosbach
f79eacae90
ARM assembler support for register name aliases.
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rdar://10550084
llvm-svn: 146170
2011-12-08 19:27:38 +00:00
Jim Grosbach
e1fe053f6e
ARM NEON two-operand aliases for VSHL(immediate).
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llvm-svn: 146125
2011-12-08 01:30:04 +00:00
Jim Grosbach
597cb99d62
ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
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llvm-svn: 146116
2011-12-08 00:52:55 +00:00
Jim Grosbach
fa73a483a9
ARM VFP support 'flds/fldd' aliases for 'vldr'
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llvm-svn: 146115
2011-12-08 00:49:29 +00:00
Jim Grosbach
c1cf417595
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
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llvm-svn: 146111
2011-12-08 00:31:07 +00:00
Jim Grosbach
6146f79b7d
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
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For 'gas' compatibility.
llvm-svn: 146106
2011-12-07 23:40:58 +00:00
Jim Grosbach
81cb9952c9
ARM support the .arm and .thumb directives for assembly mode switching.
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llvm-svn: 146042
2011-12-07 18:04:19 +00:00
Jim Grosbach
57478f4961
ARM: NEON SHLL instruction immediate operand range checking.
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llvm-svn: 146003
2011-12-07 01:07:24 +00:00
Jim Grosbach
8bdbe92631
Thumb2 encoding choice correction for PLD.
...
Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
llvm-svn: 145919
2011-12-06 04:49:29 +00:00
Jim Grosbach
74bbb6454e
Tweak ADDrr fix. Bad check for explicit .w
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llvm-svn: 145863
2011-12-05 22:27:04 +00:00
Jim Grosbach
898ab7e4ec
Thumb2 prefer ADD register encoding T2 to T3 when possible.
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rdar://10529664
llvm-svn: 145860
2011-12-05 22:16:39 +00:00
Jim Grosbach
655b017748
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
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rdar://10529348
llvm-svn: 145851
2011-12-05 21:06:26 +00:00
Jim Grosbach
fb734dff3c
ARM NEON VEXT aliases for data type suffices.
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llvm-svn: 145726
2011-12-02 23:34:39 +00:00
Jim Grosbach
3b245f9c39
ARM VST1 single lane assembly parsing.
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llvm-svn: 145718
2011-12-02 22:34:51 +00:00
Jim Grosbach
82ae7f46ea
ARM VLD1 single lane assembly parsing.
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llvm-svn: 145712
2011-12-02 22:01:52 +00:00
Jim Grosbach
a568ef0db6
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
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Add the 16-bit lane variants while I'm at it.
llvm-svn: 145693
2011-12-02 18:52:30 +00:00
Jim Grosbach
d5c0c63223
ARM start parsing VLD1 single lane instructions.
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The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.
llvm-svn: 145655
2011-12-02 00:35:16 +00:00
Jim Grosbach
fa9f6ccd62
ARM parsing for VLD1 two register all lanes, no writeback.
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llvm-svn: 145504
2011-11-30 18:21:25 +00:00
Jim Grosbach
693ce8291c
ARM parsing aliases for VLD1 single register all lanes.
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llvm-svn: 145464
2011-11-30 01:09:44 +00:00
Jim Grosbach
9adabf4dde
Tidy up a bit.
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llvm-svn: 145458
2011-11-29 23:51:09 +00:00