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57 Commits

Author SHA1 Message Date
Krzysztof Parzyszek
d531e71318 [Hexagon] Foundation of support for Hexagon V66 
llvm-svn: 348407
 2018-12-05 20:18:09 +00:00
Krzysztof Parzyszek
2d539eff53 [Hexagon] Remove -mhvx-double and the corresponding subtarget feature 
Specifying the HVX vector length should be done via the -mhvx-length
option.

llvm-svn: 329079
 2018-04-03 16:06:36 +00:00
Krzysztof Parzyszek
4bedb2b21f [Hexagon] Add guest registers 
llvm-svn: 326450
 2018-03-01 17:03:26 +00:00
Krzysztof Parzyszek
c2af269623 [Hexagon] Implement basic vector operations on vectors vNi1 
In addition to that, make sure that there are no boolean vector types that
are associated with multiple register classes. Specifically, remove v32i1
and v64i1 from integer register classes. These types will correspond to
results of vector comparisons, and as such should belong to the vector
predicate class. Having them in scalar registers as well makes legalization
ambiguous.

llvm-svn: 323229
 2018-01-23 17:53:59 +00:00
Krzysztof Parzyszek
b90ded8ab6 [Hexagon] Allow construction of HVX vector predicates 
Handle BUILD_VECTOR of boolean values.

llvm-svn: 321220
 2017-12-20 20:49:43 +00:00
Krzysztof Parzyszek
1eb78fb8be [Hexagon] Generate HVX code for comparisons and selects 
llvm-svn: 320744
 2017-12-14 21:28:48 +00:00
Krzysztof Parzyszek
f4e269a95c [Hexagon] Remove vectors of i64 from valid HVX types 
HVX does not support operations on 64-bit integers.

llvm-svn: 320722
 2017-12-14 18:35:24 +00:00
Krzysztof Parzyszek
da717aa099 [Hexagon] Add support for Hexagon V65 
llvm-svn: 320404
 2017-12-11 18:57:54 +00:00
Krzysztof Parzyszek
671ad0a881 [Hexagon] Remove trailing spaces, NFC 
llvm-svn: 318875
 2017-11-22 20:43:00 +00:00
Sumanth Gundapaneni
262321d1ff [Hexagon] New HVX target features. 
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"

For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"

Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.

Differential Revision: https://reviews.llvm.org/D38851

llvm-svn: 316101
 2017-10-18 18:07:07 +00:00
Krzysztof Parzyszek
325bb38667 [Hexagon] Switch to parameterized register classes for HVX 
This removes the duplicate HVX instruction set for the 128-byte mode.
Single instruction set now works for both modes (64- and 128-byte).

llvm-svn: 313362
 2017-09-15 15:46:05 +00:00
Krzysztof Parzyszek
dd2ec2e770 [Hexagon] Remove C6 and C7 as separate registers 
These are M0 and M1. Removing duplicated registers reduces the number
of explicit register aliasing.

llvm-svn: 302306
 2017-05-05 22:12:12 +00:00
Krzysztof Parzyszek
f44562707e [Hexagon] Improving error reporting for writing to read only registers 
Patch by Colin LeMahieu.

llvm-svn: 301828
 2017-05-01 20:10:41 +00:00
Krzysztof Parzyszek
578d2eb656 [Hexagon] Implement @llvm.readcyclecounter() 
llvm-svn: 295892
 2017-02-22 22:28:47 +00:00
Krzysztof Parzyszek
3eceaa547a [Hexagon] Start using regmasks on calls 
Reapply r295371 with a fix for the Windows bot failures.

llvm-svn: 295504
 2017-02-17 22:14:51 +00:00
Rafael Espindola
94aead7e8f Revert "[Hexagon] Start using regmasks on calls" 
This reverts commit r295371.

It broke windows bots:

http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio

llvm-svn: 295402
 2017-02-17 02:08:58 +00:00
Krzysztof Parzyszek
f31e4da09b [Hexagon] Start using regmasks on calls 
All the cool targets are doing it...

llvm-svn: 295371
 2017-02-16 20:25:23 +00:00
Krzysztof Parzyszek
5f0b4b1ff0 [Hexagon] Introduce Hexagon V62 
llvm-svn: 294805
 2017-02-10 23:46:45 +00:00
Krzysztof Parzyszek
45ad4809a2 [Hexagon] Replace instruction definitions with auto-generated ones 
llvm-svn: 294753
 2017-02-10 15:33:13 +00:00
Krzysztof Parzyszek
d7827facd5 [Hexagon] Explicitly reserve aliases of reserved registers 
llvm-svn: 292836
 2017-01-23 22:13:05 +00:00
Krzysztof Parzyszek
4e7a3e05a1 [Hexagon] Separate Hexagon subreg indices for different register classes 
For pairs of 32-bit registers: isub_lo, isub_hi.
For pairs of vector registers: vsub_lo, vsub_hi.

Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function
  HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg)
that returns the appropriate subreg index for RegClass.

llvm-svn: 286377
 2016-11-09 16:19:08 +00:00
Krzysztof Parzyszek
adcaed920a [Hexagon] Relocate pattern-related bits to proper places 
llvm-svn: 286049
 2016-11-05 21:44:50 +00:00
Krzysztof Parzyszek
047695086f [Hexagon] Remove USR_OVF from CtrRegs register class 
USR_OVF is a subregister of USR, which is a member of CtrRegs. Having both
a register and its proper subregister in the same register class has bad
consequences for lane mask calculation: based solely on the lane mask info,
USR_OVF would not appear to be a subregister of USR.

llvm-svn: 282192
 2016-09-22 20:59:41 +00:00
Krzysztof Parzyszek
af88633ebc [Hexagon] Minor updates to register definitions 
llvm-svn: 279269
 2016-08-19 16:40:19 +00:00
Krzysztof Parzyszek
421d04a22a [Hexagon] Separate C8 and USR to avoid unwanted subregister composition 
Composing subreg_loreg with subreg_oveflow leads to strange results with
lane masks for register classes with subreg_loreg. In particular, dead
lane detection generates incorrect code.

llvm-svn: 271087
 2016-05-28 01:51:16 +00:00
Krzysztof Parzyszek
59ba2ba8f4 [Hexagon] Properly recognize register alt names 
llvm-svn: 267038
 2016-04-21 19:49:53 +00:00
Krzysztof Parzyszek
882483351a [Hexagon] Mark HVX registers as volatile 
llvm-svn: 260753
 2016-02-12 22:26:44 +00:00
Krzysztof Parzyszek
128795bb47 [Hexagon] HVX vector register classes and more isel patterns 
llvm-svn: 254132
 2015-11-26 04:33:11 +00:00
Colin LeMahieu
350f96d137 [Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing tests. General updating of the code emission. 
llvm-svn: 252443
 2015-11-09 04:07:48 +00:00
Colin LeMahieu
fa53018d3f [Hexagon] Adding skeleton of HVX extension instructions. 
llvm-svn: 250600
 2015-10-17 01:33:04 +00:00
Colin LeMahieu
e39bce1b3f [Hexagon] Adding vector shift instructions and tests. 
llvm-svn: 227619
 2015-01-30 21:58:46 +00:00
Colin LeMahieu
d1253ac69a [Hexagon] Adding alu vector instructions 
llvm-svn: 227493
 2015-01-29 21:09:30 +00:00
Colin LeMahieu
9cc2ac99d5 [Hexagon] Updating muxir/ri/ii intrinsics. Setting predicate registers as compatible with i32 rather than doing custom type conversion. 
llvm-svn: 226500
 2015-01-19 20:31:18 +00:00
Colin LeMahieu
286196b24f [Hexagon] Adding deallocframe and circular addressing loads. 
llvm-svn: 224869
 2014-12-26 20:30:58 +00:00
Colin LeMahieu
1602e43331 [Hexagon] Adding doubleregs for control registers. Renaming control register class. 
llvm-svn: 224598
 2014-12-19 18:56:10 +00:00
Colin LeMahieu
ab28d2b2e6 [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. 
llvm-svn: 224556
 2014-12-19 00:06:53 +00:00
Colin LeMahieu
069ff897d0 Reverting 224550, was not ready for commit. 
llvm-svn: 224552
 2014-12-18 23:36:15 +00:00
Colin LeMahieu
260ab2afbd [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. 
llvm-svn: 224550
 2014-12-18 23:27:51 +00:00
Colin LeMahieu
4316fd4269 [Hexagon] Reconfiguring register alternate names. 
llvm-svn: 224455
 2014-12-17 20:35:11 +00:00
Colin LeMahieu
490a0f9c58 [Hexagon] Adding JR class predicated call reg instructions. 
llvm-svn: 223933
 2014-12-10 18:24:16 +00:00
Colin LeMahieu
e3767ba748 [Hexagon] Adding xtype parity, min, minu, max, maxu instructions. 
llvm-svn: 223693
 2014-12-08 21:19:18 +00:00
Colin LeMahieu
663e36e9b8 [Hexagon] Adding add/sub with saturation. Removing unused def. Cleaning up shift patterns. 
llvm-svn: 223680
 2014-12-08 18:33:49 +00:00
Sid Manning
f50e99f69a Loop instead of individual def's for each GPR. 
Differential Revision: http://reviews.llvm.org/D5450

llvm-svn: 218305
 2014-09-23 13:55:50 +00:00
Sid Manning
5bfddd3329 Add missing HWEncoding to base register class. 
This change gives tblgen the information needed to fill in the
HexagonRegEncodingTable.

llvm-svn: 217500
 2014-09-10 13:09:25 +00:00
Jyotsna Verma
9134441949 reverting r209132 
llvm-svn: 209139
 2014-05-19 16:22:11 +00:00
Jyotsna Verma
dc58cfbd79 Hexagon: Add encoding bits to the mpy instructions. 
llvm-svn: 209132
 2014-05-19 15:32:07 +00:00
Ahmed Bougacha
2263547c8f Make SubRegIndex size mandatory, following r183020. 
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.

llvm-svn: 183061
 2013-05-31 23:45:26 +00:00
Sirish Pande
7fbfe4a1d6 Hexagon V5 FP Support. 
llvm-svn: 156568
 2012-05-10 20:20:25 +00:00
Jakob Stoklund Olesen
7bdae32bfd Remove the SubRegClasses field from RegisterClass descriptions. 
This information in now computed by TableGen.

llvm-svn: 156152
 2012-05-04 03:30:34 +00:00
Chandler Carruth
9460759e4f Revert r155365, r155366, and r155367. All three of these have regression 
test suite failures. The failures occur at each stage, and only get
worse, so I'm reverting all of them.

Please resubmit these patches, one at a time, after verifying that the
regression test suite passes. Never submit a patch without running the
regression test suite.

llvm-svn: 155372
 2012-04-23 18:25:57 +00:00