Chad Rosier
8cfccc356e
Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures.
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llvm-svn: 144492
2011-11-13 05:14:43 +00:00
Chad Rosier
0770c4834a
Fix comments.
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llvm-svn: 144490
2011-11-13 04:25:02 +00:00
Chad Rosier
acd199b5a4
Add support for emitting both signed- and zero-extend loads. Fix
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SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3). This enables a load followed by an integer
extend to be folded into a single load.
For example:
ldrb r1, [r0] ldrb r1, [r0]
uxtb r2, r1 =>
mov r3, r2 mov r3, r1
llvm-svn: 144488
2011-11-13 02:23:59 +00:00
Daniel Dunbar
73d41b0f03
build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies.
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- The hope is that we have a tool/test to verify these are accurate (and tight) soon.
llvm-svn: 144444
2011-11-12 02:10:57 +00:00
Jim Grosbach
7e41554aa7
ARM refactor simple immediate asm operand render methods.
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These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.
llvm-svn: 144439
2011-11-12 00:58:43 +00:00
Jim Grosbach
312b583950
Re-apply 144430, this time with the associated isel and disassmbler bits.
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Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'
llvm-svn: 144437
2011-11-12 00:31:53 +00:00
Jim Grosbach
7fccd540c9
Oops. Missed the isel half of this. revert while I sort that out.
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llvm-svn: 144431
2011-11-11 23:51:31 +00:00
Jim Grosbach
13af5276a1
ARM assembly parsing for VST1 two-register encoding.
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llvm-svn: 144430
2011-11-11 23:45:47 +00:00
Jim Grosbach
13b7ab7527
ARM optional size suffix for VLDR/VSTR syntax.
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llvm-svn: 144427
2011-11-11 23:34:43 +00:00
Chad Rosier
a2a0fbeded
Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.
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llvm-svn: 144426
2011-11-11 23:31:03 +00:00
Jim Grosbach
bc077320e1
ARM vldm and vstm VFP instructions can take a data type suffix.
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It's ignored by the assembler when present, but is legal syntax. Other
instructions have something similar, but for some mnemonics it's
only sometimes not significant, so this quick check in the parser will
need refactored into something more robust soon-ish. This gets some
basics working in the meantime.
Partial for rdar://10435264
llvm-svn: 144422
2011-11-11 23:08:10 +00:00
Jim Grosbach
01a7117803
Nuke no longer accurate comment.
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llvm-svn: 144411
2011-11-11 22:30:06 +00:00
Andrew Trick
6ff75a5d8d
Preserve MachineMemOperands in ARMLoadStoreOptimizer.
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Fixes PR8113.
llvm-svn: 144409
2011-11-11 22:18:09 +00:00
Jim Grosbach
1d581ecb00
ARM allow Q registers in vldm/vstm register lists.
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rdar://9672822
llvm-svn: 144407
2011-11-11 21:27:40 +00:00
Benjamin Kramer
e5295a772e
Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.
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llvm-svn: 144384
2011-11-11 12:39:41 +00:00
Chad Rosier
98f48b009e
Rename variables to avoid confusion. No functionallity change intended.
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llvm-svn: 144377
2011-11-11 06:27:41 +00:00
Chad Rosier
feb72bfc08
Add support for using immediates with select instructions.
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rdar://10412592
llvm-svn: 144376
2011-11-11 06:20:39 +00:00
Eli Friedman
285b451941
Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.
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llvm-svn: 144361
2011-11-11 03:16:38 +00:00
Chad Rosier
38f07d3f9c
When loading a value, treat an i1 as an i8.
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llvm-svn: 144356
2011-11-11 02:38:59 +00:00
Chad Rosier
ac92994773
Add support for using MVN to materialize negative constants.
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rdar://10412592
llvm-svn: 144348
2011-11-11 00:36:21 +00:00
Daniel Dunbar
846fb32afc
LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler.
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llvm-svn: 144344
2011-11-11 00:23:56 +00:00
Jim Grosbach
ddf85f6be2
Thumb2 ldm/stm updating w/ one register in the list are LDR/STR.
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rdar://10429490
llvm-svn: 144338
2011-11-10 23:58:34 +00:00
Jim Grosbach
d1d04109ff
ARM let processInstruction() tranforms chain.
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llvm-svn: 144337
2011-11-10 23:42:14 +00:00
Jim Grosbach
bd7df609b7
Thumb2 parsing for push/pop w/ hi registers in the reglist.
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rdar://10130228.
llvm-svn: 144331
2011-11-10 23:17:11 +00:00
Jim Grosbach
615c824de4
Thumb1 diagnostics for reglist on PUSH/POP fix.
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Was not checking the first register in the register list.
llvm-svn: 144329
2011-11-10 23:01:27 +00:00
Jim Grosbach
c3651cb620
Thumb MUL assembly parsing for 3-operand form.
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Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.
rdar://10428630
llvm-svn: 144322
2011-11-10 22:10:12 +00:00
Chad Rosier
7b7dced006
When in ARM mode, LDRH/STRH require special handling of negative offsets.
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For correctness, disable this for now.
rdar://10418009
llvm-svn: 144316
2011-11-10 21:09:49 +00:00
Jim Grosbach
614f35bb30
ARM .thumb_func directive for quoted symbol names.
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Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.
rdar://10428015
llvm-svn: 144315
2011-11-10 20:48:53 +00:00
Jim Grosbach
f5943e4c5e
ARM assembly parsing for LSR/LSL/ROR(immediate).
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More of rdar://9704684
llvm-svn: 144301
2011-11-10 19:18:01 +00:00
Jim Grosbach
b66dfc2999
ARM assembly parsing for ASR(immediate).
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Start of rdar://9704684
llvm-svn: 144293
2011-11-10 16:44:55 +00:00
Chad Rosier
69cdae5eb9
For immediate encodings of icmp, zero or sign extend first. Then
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determine if the value is negative and flip the sign accordingly.
rdar://10422026
llvm-svn: 144258
2011-11-10 01:30:39 +00:00
Daniel Dunbar
f0c4aed0ab
llvm-build: Add --native-target and --enable-targets options, and add logic to
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handle defining the "magic" target related components (like native,
nativecodegen, and engine).
- We still require these components to be in the project (currently in
lib/Target) so that we have a place to document them and hopefully make it
more obvious that they are "magic".
llvm-svn: 144253
2011-11-10 00:50:07 +00:00
Daniel Dunbar
c09b47db8f
llvm-build: Add an explicit component type to represent targets.
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- Gives us a place to hang target specific metadata (like whether the target has a JIT).
llvm-svn: 144250
2011-11-10 00:49:51 +00:00
Jim Grosbach
ee70556a4e
Tidy up.
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llvm-svn: 144244
2011-11-10 00:02:33 +00:00
Jim Grosbach
8591bd2bab
Thumb2 assembly parsing STMDB w/ optional .w suffix.
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rdar://10422955
llvm-svn: 144242
2011-11-09 23:44:23 +00:00
Eli Friedman
c93f8aa514
Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.
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llvm-svn: 144241
2011-11-09 23:36:02 +00:00
Chad Rosier
f47b941510
The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.
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rdar://10418009
llvm-svn: 144213
2011-11-09 21:30:12 +00:00
Chad Rosier
e32fed6868
Add support for encoding immediates in icmp and fcmp. Hopefully, this will
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remove a fair number of unnecessary materialized constants.
rdar://10412592
llvm-svn: 144163
2011-11-09 03:22:02 +00:00
Evan Cheng
2b29230fcf
Hide cpu name checking in ARMSubtarget.
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llvm-svn: 144154
2011-11-09 01:57:03 +00:00
Evan Cheng
08e61752f2
Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs.
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llvm-svn: 144123
2011-11-08 21:21:09 +00:00
Chad Rosier
24a6e399f8
ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this.
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No functional change intended.
llvm-svn: 144122
2011-11-08 21:12:00 +00:00
Lang Hames
ee7de1cff0
Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.
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Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.
llvm-svn: 144102
2011-11-08 18:56:23 +00:00
Pete Cooper
224434deec
Added invariant field to the DAG.getLoad method and changed all calls.
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When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
llvm-svn: 144100
2011-11-08 18:42:53 +00:00
Eli Friedman
d5ba38a3d2
Make sure to mark vector extload's as expand on ARM. Fixes PR11319.
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llvm-svn: 144057
2011-11-08 01:43:53 +00:00
Chad Rosier
4b12a5b7fc
Enable support for returning i1, i8, and i16. Nothing special todo as it's the
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callee's responsibility to sign or zero-extend the return value. The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).
llvm-svn: 144047
2011-11-08 00:03:32 +00:00
Chad Rosier
7e0e075322
Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling convention as well.
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llvm-svn: 144021
2011-11-07 21:43:40 +00:00
Benjamin Kramer
89ebc7ab4b
Simplify some uses of utohexstr.
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As a side effect hex is printed lowercase instead of uppercase now.
llvm-svn: 144013
2011-11-07 21:00:59 +00:00
Benjamin Kramer
c597902ecc
Replace (Lower|Upper)caseString in favor of StringRef's newest methods.
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llvm-svn: 143891
2011-11-06 20:37:06 +00:00
Chad Rosier
806ffd8918
Add support for passing i1, i8, and i16 call parameters. Also, be sure to
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zero-extend the constant integer encoding. Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.
llvm-svn: 143821
2011-11-05 20:16:15 +00:00
Chad Rosier
af23ffd465
Allow i1 to be promoted to i32 for ARM APCS calling convention.
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llvm-svn: 143755
2011-11-05 00:02:56 +00:00