Chris Lattner
86ab578e3e
Remove some regs that are not used.
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llvm-svn: 22975
2005-08-22 22:32:13 +00:00
Chris Lattner
362eff4ccd
Nate noticed that 30% of the malloc/frees in llc come from calls to LowercaseString
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in the asmprinter. This changes the .td files to use lower case register names,
avoiding the need to do this call. This speeds up the asmprinter from 1.52s
to 1.06s on kc++ in a release build.
llvm-svn: 22974
2005-08-22 22:00:02 +00:00
Chris Lattner
aee36bb527
Revamp the Register class, and allow the use of the RegisterGroup class to
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specify aliases directly in register definitions.
Patch contributed by Jason Eckhardt!
llvm-svn: 16330
2004-09-14 04:17:02 +00:00
Misha Brukman
35826543f8
Register classes are target-dependent
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llvm-svn: 15861
2004-08-17 05:10:31 +00:00
Nate Begeman
00a1951fb1
Fix frame pointer handling:
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Reserve R0 in store/load from stack slot for building >32k offsets from SP
or FP. This also requires we use R11 rather than R0 for holding the LR
value we want to save or restore. Also, tell the register allocator not
to use R31 (our FP) in functions that have a frame pointer. These changes
fix Burg.
llvm-svn: 15807
2004-08-16 01:52:12 +00:00
Chris Lattner
cf6878b6c9
Reenable the CCRC
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llvm-svn: 15752
2004-08-15 05:31:15 +00:00
Misha Brukman
d9b3a360fc
Mark R2 as available for allocation on Darwin/PPC32, but not AIX/PPC64
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llvm-svn: 15673
2004-08-12 00:10:01 +00:00
Misha Brukman
42e53e4d94
* Set the is64bit boolean flag in PowerPCRegisterInfo
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* Doubles are 8 bytes in 64-bit PowerPC, and use the general register class
* Use double-word loads and stores for restoring from/saving to stack
* Do not allocate R2 if compiling for AIX
llvm-svn: 15670
2004-08-11 23:44:55 +00:00
Misha Brukman
3f79fbe93f
Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targets
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llvm-svn: 15631
2004-08-10 22:47:03 +00:00
Misha Brukman
148ad01de1
Renamed files:
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* PowerPCReg.td => PowerPCRegisterinfo.td
* PowerPCInstrs.td => PowerPCInstrInfo.td
llvm-svn: 15295
2004-07-27 23:29:16 +00:00
Misha Brukman
6fec7336fe
LR is a 32-bit int reg
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llvm-svn: 15273
2004-07-27 17:15:32 +00:00
Misha Brukman
468900296b
* Enable allocation of registers r2-r10
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* Allocate registers 13-31 backwards (to be able to store them all at once)
llvm-svn: 14896
2004-07-16 20:35:20 +00:00
Misha Brukman
e409874a9f
* Do not allocate r0 as we use it indiscriminantly in the instr selector.
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* Do not define CR register class because we don't (yet) have the i4 type
llvm-svn: 14551
2004-07-01 21:24:50 +00:00
Misha Brukman
7089b3d426
* Allow more registers to be allocated from the general register pool
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* Define the condition register class
llvm-svn: 14510
2004-06-30 21:54:50 +00:00
Misha Brukman
a0721ac147
Only allocate non-volatile registers R13-31 (for now).
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llvm-svn: 14500
2004-06-29 23:35:32 +00:00
Misha Brukman
269034c151
Initial revision
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llvm-svn: 14283
2004-06-21 16:55:25 +00:00
