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3225 Commits

Author SHA1 Message Date
Bill Wendling
787de8fe38 Readd testcase. 
llvm-svn: 103335
 2010-05-08 04:47:54 +00:00
Dan Gohman
4ca74b9c6c When pruning candidate formulae out of an LSRUse, update the 
LSRUse's Regs set after all pruning is done, rather than trying
to do it on the fly, which can produce an incomplete result.

This fixes a case where heuristic pruning was stripping all
formulae from a use, which led the solver to enter an infinite
loop.

Also, add a few asserts to diagnose this kind of situation.

llvm-svn: 103328
 2010-05-07 23:36:59 +00:00
Bill Wendling
4241941b52 Remove. Don't XFAIL. 
llvm-svn: 103321
 2010-05-07 23:09:17 +00:00
Bill Wendling
3846ec7889 Temorarily revert r101984. 
llvm-svn: 103314
 2010-05-07 22:45:36 +00:00
Dan Gohman
95040c18f4 SDDbgValues are apparently not being legalized. Fix a symptom of the problem, 
and not the real problem itself, by dropping debug info for i128 values.
rdar://7958162.

llvm-svn: 103310
 2010-05-07 22:19:08 +00:00
Dale Johannesen
1ee37ac5d4 Fix PR 7087, and probably other things, by extending 
getConstantFP to accept the two supported long double
target types.  This was not the original intent, but
there are other places that assume this works and it's
easy enough to do.

llvm-svn: 103299
 2010-05-07 21:35:53 +00:00
Jim Grosbach
2db1618b44 Clean up the conditional for handling of sign_extend_inreg based on 
whether the extract instructions are available.

rdar://7956878

llvm-svn: 103277
 2010-05-07 18:34:55 +00:00
Duncan Sands
ed2ef5a987 Correct some bogus target triples. 
llvm-svn: 103265
 2010-05-07 17:03:48 +00:00
Nick Lewycky
3e5720a898 Revert r103133 and add testcase from PR7066. 
llvm-svn: 103233
 2010-05-07 01:45:38 +00:00
Dan Gohman
f863ad3dc5 Disable the new unknown-location code for now. It causes a major 
increase in the debug line info section, and it's causing
regressions in a gdb testsuite.

llvm-svn: 103226
 2010-05-07 01:08:53 +00:00
Dan Gohman
497e752655 Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 
doesn't have to guess.

llvm-svn: 103194
 2010-05-06 20:33:48 +00:00
Dan Gohman
3190e5c292 Add a testcase for r103135, explicitly representing unknown 
locations in debug line info.

llvm-svn: 103189
 2010-05-06 17:49:17 +00:00
Chris Lattner
014a954e3d Fix PR7054 - Assertion `Symbol->isUndefined() && "Cannot define a symbol twice!"' failed. 
Users can write broken code that emits the same label twice with asm renaming,
detect this and emit a fatal backend error instead of aborting.

llvm-svn: 103140
 2010-05-06 00:05:37 +00:00
Jim Grosbach
e04cc6cb43 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136
 2010-05-05 23:44:43 +00:00
Jakob Stoklund Olesen
2e5d12acfa Fix PR6520. An earlyclobber physreg must not be allocated to anything else. 
llvm-svn: 103133
 2010-05-05 23:07:41 +00:00
Jim Grosbach
7eb0b4d646 fix copy/paste oops. 
llvm-svn: 103122
 2010-05-05 21:07:46 +00:00
Jim Grosbach
25fc725b2a Add tests for ARMV7M divide instruction use 
llvm-svn: 103120
 2010-05-05 20:47:15 +00:00
Jim Grosbach
9b7ae2027f remove unneeded underscores. 
llvm-svn: 103114
 2010-05-05 19:55:58 +00:00
Jim Grosbach
7ea67d346f Convert to filecheck 
llvm-svn: 103113
 2010-05-05 19:41:11 +00:00
Chris Lattner
b4696853af "on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'." 
Patch by Kalle Raiskila!

llvm-svn: 103021
 2010-05-04 17:58:46 +00:00
Dale Johannesen
b10ca6bf4c Implement builtin_return_address(x) and builtin_frame_address(x) 
on PPC for x!=0.  7624113.

llvm-svn: 102972
 2010-05-03 22:59:34 +00:00
Jakob Stoklund Olesen
51ab2653d5 Check that subregisters don't have independent values in RemoveCopyByCommutingDef(). 
This fixes PR6941.

llvm-svn: 102970
 2010-05-03 22:40:32 +00:00
Dan Gohman
c024fd43c9 Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul, 
when the type is floating-point.

llvm-svn: 102969
 2010-05-03 22:36:46 +00:00
Dan Gohman
15cb983f55 Fix a bug which prevented tail merging of return instructions in 
beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and
test/CodeGen/ARM/ifcvt2.ll for details.

The fix is to change HashEndOfMBB to hash at most one instruction,
instead of trying to apply heuristics about when it will be profitable to
consider more than one instruction. The regular tail-merging heuristics
are already prepared to handle the same cases, and they're more precise.

Also, make test/CodeGen/ARM/ifcvt5.ll and
test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they
continue to test what they're intended to test.

And, this eliminates the problem in
test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from
PR5204. Update it accordingly.

llvm-svn: 102907
 2010-05-03 14:35:47 +00:00
Duncan Sands
153ad3b903 Remove the -enable-sjlj-eh option, which doesn't do anything. 
Remove the -enable-eh option which is only used by the JIT,
and replace it with -jit-enable-eh.

llvm-svn: 102865
 2010-05-02 15:36:26 +00:00
Anton Korobeynikov
a3726088fa Insert ANY_EXTEND node instead of invalid truncate during DAG Combining (X & 1), 
when needed. This fixes PR7001

llvm-svn: 102838
 2010-05-01 12:52:34 +00:00
Anton Korobeynikov
f31181a0cc Do folding for indirect branches, where possible 
llvm-svn: 102836
 2010-05-01 12:28:21 +00:00
Anton Korobeynikov
9b724bd446 Implement indirect branches on MSP430 
llvm-svn: 102835
 2010-05-01 12:04:32 +00:00
Bill Wendling
7b6527b94b Test failing too much on too many platforms. 
llvm-svn: 102812
 2010-05-01 00:12:33 +00:00
Bill Wendling
a348ff69b8 Maybe it needs sse2? 
llvm-svn: 102802
 2010-04-30 23:19:29 +00:00
Bill Wendling
d1c5f11f72 Force 64-bit. 
llvm-svn: 102800
 2010-04-30 22:45:20 +00:00
Bill Wendling
95a4929ac7 EXTRACT_VECTOR_ELT of an INSERT_VECTOR_ELT may have the same index, but the 
indexes could be of a different value type. Or not even using the same SDNode
for the constant (weird, I know). Compare the actual values instead of the
pointers.

llvm-svn: 102791
 2010-04-30 22:19:17 +00:00
Jakob Stoklund Olesen
fac584ed9e The local register allocator has to spill dirty callee saved registers before a 
call that might throw. The landing pad assumes that all registers are in stack
slots.

We used to spill those dirty CSRs after the call, and the stack slots would be
wrong when arriving at the landing pad.

llvm-svn: 102770
 2010-04-30 21:19:29 +00:00
Evan Cheng
fc86d7fbdc Fix test. 
llvm-svn: 102694
 2010-04-30 06:00:56 +00:00
Evan Cheng
9303b11e47 Another sibcall bug. If caller and callee calling conventions differ, then it's only safe to do a tail call if the results are returned in the same way. 
llvm-svn: 102683
 2010-04-30 01:12:32 +00:00
Jakob Stoklund Olesen
01254ea96d Reject really weird coalescer case when trying to merge identical subregisters 
of different register classes. e.g.

  %reg1048:3<def> = EXTRACT_SUBREG %RAX<kill>, 3

Where %reg1048 is a GR32 register. This is not impossible to handle, but it is
pretty hard and very rare.

This should unbreak the dragonegg builder.

llvm-svn: 102672
 2010-04-29 23:47:46 +00:00
Evan Cheng
da89f22f3d Load folding tail call should not use ebp / rbp after it's popped. PEI 
should use esp / rsp to reference frame instead.

llvm-svn: 102596
 2010-04-29 05:08:22 +00:00
Chris Lattner
9867c1a075 Rework global alignment computation again. Now we do round up 
alignment of globals to the preferred alignment, but only when
there is no section specified on the global (by far the common
case).

llvm-svn: 102515
 2010-04-28 19:58:07 +00:00
Evan Cheng
d4fe387eb8 Enable i16 to i32 promotion by default. 
llvm-svn: 102493
 2010-04-28 08:30:49 +00:00
Evan Cheng
08e5f737d2 Update tests. 
llvm-svn: 102487
 2010-04-28 01:53:13 +00:00
Devang Patel
570e9d53a7 Emit debug info for byval parameters. 
llvm-svn: 102486
 2010-04-28 01:39:28 +00:00
Evan Cheng
2aaefc6167 Do not count kill, implicit_def instructions as printed instructions. 
llvm-svn: 102453
 2010-04-27 19:38:45 +00:00
Chris Lattner
a9c1328501 round zero-byte .zerofill directives up to 1 byte. This 
should fix some "g++.dg-struct-layout-1" failures, 
rdar://7886017

llvm-svn: 102421
 2010-04-27 07:41:44 +00:00
Chris Lattner
9292bad5f5 on darwin empty functions need to codegen into something of non-zero length, 
otherwise labels get incorrectly merged.  We handled this by emitting a 
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes.  Handle this by emitting a noop.  This
is more gross than it should be because arm/ppc are not fully mc'ized yet.

This fixes rdar://7908505

llvm-svn: 102400
 2010-04-26 23:37:21 +00:00
Bob Wilson
ece63716aa Handle register-to-register copies within the tGPR class. 
Radar 7896289

llvm-svn: 102396
 2010-04-26 23:20:08 +00:00
Dan Gohman
40561dd0ba When checking whether the special handling for an addrec increment which 
doesn't dominate the header is needed, don't check whether the increment
expression has computable loop evolution. While the operands of an
addrec are required to be loop-invariant, they're not required to 
dominate any part of the loop. This fixes PR6914.

llvm-svn: 102389
 2010-04-26 21:46:36 +00:00
Chris Lattner
4854eab087 fix PR6921 a different way. Intead of increasing the 
alignment of globals with a specified alignment, we fix
common variables to obey their alignment.  Add a comment
explaining why this behavior is important.

llvm-svn: 102365
 2010-04-26 18:46:46 +00:00
Chris Lattner
a8cd2ac893 Revert r102300/102301, which serious broke objc apps. 
llvm-svn: 102359
 2010-04-26 18:30:45 +00:00
Chris Lattner
e4a25eb35a Fix PR6921: globals were not getting correctly rounded up to their 
preferred alignment unless they were common or some other special
case.

llvm-svn: 102300
 2010-04-25 05:30:43 +00:00
Dan Gohman
42337e0ee9 Generalize LSR's OptimizeMax to handle the new kinds of max expressions 
that indvars may use, now that indvars is recognizing le and ge loops.

llvm-svn: 102235
 2010-04-24 03:13:44 +00:00
Stuart Hastings
85b5c330f2 Per Chris, fuse four trivial tests using grep (r102199) into one that uses FileCheck. 
llvm-svn: 102216
 2010-04-23 22:12:57 +00:00
Dan Gohman
6a48222bd8 Change TargetData's algorithm for computing defualt vector type 
alignment to match what's used in clang and GCC for __alignof, rather
than trying to guess what Legalize is going to be doing.

llvm-svn: 102206
 2010-04-23 19:41:15 +00:00
Stuart Hastings
ad81819149 Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU testcases. Radar 6881029. 
llvm-svn: 102199
 2010-04-23 19:03:32 +00:00
Dan Gohman
38949c2f1f Fix LSR to tolerate cases where ScalarEvolution initially 
misses an opportunity to fold add operands, but folds them
after LSR has separated them out. This fixes rdar://7886751.

llvm-svn: 102157
 2010-04-23 01:55:05 +00:00
Jim Grosbach
b9dccb6103 Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield 
extraction. This fixes PR5998.

llvm-svn: 102144
 2010-04-22 23:24:18 +00:00
Evan Cheng
a324da99ae Do not try to optimize a copy that has already been marked for deletion. 
llvm-svn: 102027
 2010-04-21 20:57:54 +00:00
Evan Cheng
dbfb7dc438 Implement -disable-non-leaf-fp-elim which disable frame pointer elimination 
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181

llvm-svn: 101984
 2010-04-21 03:18:23 +00:00
Evan Cheng
a0c4b2952f - Clean up some crappy code which deals with coalescing of copies which look at 
extract_subreg / insert_subreg, etc.
- Add support for more aggressive insert_subreg coalescing.

llvm-svn: 101971
 2010-04-21 00:44:22 +00:00
Dan Gohman
570b621976 Add another variant of this test which found a place where 
CodeGen's ComputeMaskedBits was being over-conservative when computing
bits for an ADD.

llvm-svn: 101963
 2010-04-21 00:19:28 +00:00
Chris Lattner
6db0f451a7 teach the x86 address matching stuff to handle 
(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.

This finishes off PR1135.  Before we compiled the block to:
to:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	leaq	2(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	leaq	1(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	addq	$3, %rdx
	movl	%esi, (%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1

Now we produce:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	movl	%esi, 8(%rdi,%rdx,4)
	movl	%esi, 4(%rdi,%rdx,4)
	movl	%esi, 12(%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1

llvm-svn: 101958
 2010-04-20 23:18:40 +00:00
Bill Wendling
a87efb5d0f Move CodeGen/X86/2010-04-19-DAGCombineCrash.ll into CodeGen/X86/crash.ll. Also 
reduce.

llvm-svn: 101925
 2010-04-20 18:14:47 +00:00
Chris Lattner
b66b0c36cd Bill's change in r95336 broke empty aggregates embedded 
in other types.  fix this by only bumping zero-byte globals
up to a single byte if the *entire global* is zero size,
fixing PR6340.

This also fixes empty arrays etc to be handled correctly,
and only does this on subsection-via-symbols targets (aka
darwin) which is the only place where this matters.

llvm-svn: 101879
 2010-04-20 06:20:21 +00:00
Chris Lattner
04fb51984f teach cellspu how to return i8 and i16 from calls, 
patch by Kalle Raiskila!

llvm-svn: 101875
 2010-04-20 05:36:09 +00:00
Bill Wendling
887dac2aa6 The visitXOR method can return the same SDNode. If so, we don't want to delete 
it as it's not dead.

llvm-svn: 101855
 2010-04-20 01:25:01 +00:00
Bob Wilson
2e6cd50a50 Fix tests for Neon load/store intrinsics to match the i8* types expected by 
the intrinsics.  The reason for those i8* types is that the intrinsics are
overloaded on the vector type and we don't have a way to declare an intrinsic
where one argument is an overloaded vector type and another argument is a
pointer to the vector element type.  The bitcasts added here will match what
the frontend will typically generate when these intrinsics are used.

llvm-svn: 101840
 2010-04-20 00:17:16 +00:00
Nick Lewycky
c639c07492 Fix declarations in a few more tests. 
llvm-svn: 101676
 2010-04-17 21:29:25 +00:00
Chris Lattner
99d17acb35 fix PR6332, allowing an index of zero into a zero sized array 
even if the element of the array has no size.

llvm-svn: 101662
 2010-04-17 19:02:33 +00:00
Dan Gohman
5736cd1e47 Start function numbering at 0. 
llvm-svn: 101638
 2010-04-17 16:29:15 +00:00
Evan Cheng
d3d5e6793a Add nounwind. 
llvm-svn: 101613
 2010-04-17 03:43:36 +00:00
Jakob Stoklund Olesen
7e77f60652 Add test case for machine-sink on critical edges 
llvm-svn: 101416
 2010-04-15 23:19:16 +00:00
Evan Cheng
c843326d60 Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2. 
llvm-svn: 101410
 2010-04-15 22:20:34 +00:00
Jakob Stoklund Olesen
a40915cc26 Fix PR6847. RegScavenger should ignore DebugValues. 
llvm-svn: 101392
 2010-04-15 20:28:39 +00:00
Evan Cheng
2f6d7ecd1b ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908 
llvm is generating poor code for dynamic alloca, I'll fix that later.

llvm-svn: 101383
 2010-04-15 18:42:28 +00:00
Chris Lattner
1b7ecfdf60 enhance the load/store narrowing optimization to handle a 
tokenfactor in between the load/store.  This allows us to 
optimize test7 into:

_test7:                                 ## @test7
## BB#0:                                ## %entry
	movl	(%rdx), %eax
                                        ## kill: SIL<def> ESI<kill>
	movb	%sil, 5(%rdi)
	ret

instead of:

_test7:                                 ## @test7
## BB#0:                                ## %entry
	movl	4(%esp), %ecx
	movl	$-65281, %eax           ## imm = 0xFFFFFFFFFFFF00FF
	andl	4(%ecx), %eax
	movzbl	8(%esp), %edx
	shll	$8, %edx
	addl	%eax, %edx
	movl	12(%esp), %eax
	movl	(%eax), %eax
	movl	%edx, 4(%ecx)
	ret

llvm-svn: 101355
 2010-04-15 06:10:49 +00:00
Chris Lattner
8c5a5c9094 teach codegen to turn trunc(zextload) into load when possible. 
This doesn't occur much at all, it only seems to formed in the case
when the trunc optimization kicks in due to phase ordering.  In that
case it is saves a few bytes on x86-32.

llvm-svn: 101350
 2010-04-15 05:40:59 +00:00
Chris Lattner
510d19e597 add a simple dag combine to replace trivial shl+lshr with 
and.  This happens with the store->load narrowing stuff.

llvm-svn: 101348
 2010-04-15 05:28:43 +00:00
Chris Lattner
3282f3d34f Implement rdar://7860110 (also in target/readme.txt) narrowing 
a load/or/and/store sequence into a narrower store when it is
safe.  Daniel tells me that clang will start producing this sort
of thing with bitfields, and this does  trigger a few dozen times
on 176.gcc produced by llvm-gcc even now.

This compiles code like CodeGen/X86/2009-05-28-DAGCombineCrash.ll 
into:

        movl    %eax, 36(%rdi)

instead of:

        movl    $4294967295, %eax       ## imm = 0xFFFFFFFF
        andq    32(%rdi), %rax
        shlq    $32, %rcx
        addq    %rax, %rcx
        movq    %rcx, 32(%rdi)

and each of the testcases into a single store.  Each of them used
to compile into craziness like this:

_test4:
	movl	$65535, %eax            ## imm = 0xFFFF
	andl	(%rdi), %eax
	shll	$16, %esi
	addl	%eax, %esi
	movl	%esi, (%rdi)
	ret

llvm-svn: 101343
 2010-04-15 04:48:01 +00:00
Chris Lattner
553267e9cc further tweak this to do something useful. 
llvm-svn: 101341
 2010-04-15 04:31:42 +00:00
Chris Lattner
a4b3756baf remove undef control flow. 
llvm-svn: 101340
 2010-04-15 04:30:19 +00:00
Jakob Stoklund Olesen
7343a90490 Remove unneeded types from test. 
llvm-svn: 101286
 2010-04-14 20:56:09 +00:00
Bob Wilson
7b19d89e3a Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand 
does not have a legal type.  The legalizer does not know how to handle those
nodes.  Radar 7854640.

llvm-svn: 101282
 2010-04-14 20:45:23 +00:00
Evan Cheng
172f2f9e2d Add test for post-ra machine licm. 
llvm-svn: 101182
 2010-04-13 22:10:03 +00:00
Bob Wilson
526e615ff9 Handle a v2f64 formal parameter that is split between registers and memory 
such that the entire second half is in memory.  Radar 7855014.

llvm-svn: 101181
 2010-04-13 22:03:22 +00:00
Evan Cheng
6ffb1ed4fb Fix test on non-x86 hosts. 
llvm-svn: 101163
 2010-04-13 18:54:04 +00:00
Evan Cheng
b8861dcb04 Re-apply 101075 and fix it properly. Just reuse the debug info of the branch instruction being optimized. There is no need to --I which can deref off start of the BB. 
llvm-svn: 101162
 2010-04-13 18:50:27 +00:00
Eric Christopher
330ca0c937 Temporarily revert r101075, it's causing invalid iterator assertions 
in a nightly tester.

llvm-svn: 101158
 2010-04-13 18:37:58 +00:00
Chris Lattner
dabcd9738c add llvm codegen support for -ffunction-sections and -fdata-sections, 
patch by Sylvere Teissier!

llvm-svn: 101106
 2010-04-13 00:36:43 +00:00
Evan Cheng
ec21a36774 Use .set expression for x86 pic jump table reference to reduce assembly relocation. rdar://7738756 
llvm-svn: 101085
 2010-04-12 23:07:17 +00:00
Bill Wendling
5a56f7fc20 Third time's a charm... 
llvm-svn: 101081
 2010-04-12 22:43:21 +00:00
Bill Wendling
e1bf74de52 Genericize the label test. 
llvm-svn: 101079
 2010-04-12 22:40:37 +00:00
Bill Wendling
fd58812c95 Correct test to test what I mean it to test. 
llvm-svn: 101077
 2010-04-12 22:25:42 +00:00
Bill Wendling
1f2e71928c Micro-optimization: 
If we have this situation:

    jCC  L1
    jmp  L2
L1:
  ...
L2:
  ...

We can get a small performance boost by emitting this instead:

    jnCC L2
L1:
  ...
L2:
  ...

This testcase shows an example of this:

float func(float x, float y) {
    double product = (double)x * y;
    if (product == 0.0)
        return product;
    return product - 1.0;
}

llvm-svn: 101075
 2010-04-12 22:19:57 +00:00
Evan Cheng
90788354c9 Enable post regalloc machine licm by default. 
llvm-svn: 101023
 2010-04-12 06:25:28 +00:00
Benjamin Kramer
f040734da3 Make sure this test tests something. 
llvm-svn: 100879
 2010-04-09 19:03:31 +00:00
Bob Wilson
ee7665078a Add a testcase for svn r100568. 
llvm-svn: 100876
 2010-04-09 18:29:29 +00:00
Chris Lattner
5408e8a62b "On SPU, variables in the .bss section that are allocated with the .lcomm directive are not aligned on 16 byte boundaries. This causes misaligned loads, as the generated assembly assumes this "default" alignment. 
this patch disables .lcomm in favour of '.local .comm'

Patch by Kalle Raisklia!

llvm-svn: 100875
 2010-04-09 18:27:03 +00:00
Dan Gohman
a451b859f9 Merge a few fast-isel tests. 
llvm-svn: 100860
 2010-04-09 15:03:55 +00:00
Evan Cheng
619f1b8a94 Coalescer should not delete copy instructions whose defs are partially dead. e.g. 
%RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def>

llvm-svn: 100804
 2010-04-08 20:02:37 +00:00
Evan Cheng
3fa0b6fb03 Avoid using f64 to lower memcpy from constant string. It's cheaper to use i32 store of immediates. 
llvm-svn: 100751
 2010-04-08 07:37:57 +00:00
Dan Gohman
0a77dd29de When expanding expressions which are using post-inc mode for multiple loops, 
ensure that the expansion is dominated by the increments of those loops.

llvm-svn: 100748
 2010-04-08 05:57:57 +00:00