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Commit Graph

181068 Commits

Author SHA1 Message Date
Dmitry Venikov
90bf1784c8 [APInt] Fix getBitsNeeded for INT_MIN values
Summary: This patch fixes behaviour of APInt::getBitsNeeded for INT_MIN 10 bits values.

Reviewers: regehr, RKSimon

Reviewed By: RKSimon

Subscribers: grandinj, dexonsmith, kristina, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63691

llvm-svn: 364710
2019-06-29 11:38:12 +00:00
Nikita Popov
82bf7cc229 [LFTR] Fix post-inc pointer IV with truncated exit count (PR41998)
Fixes https://bugs.llvm.org/show_bug.cgi?id=41998. Usually when we
have a truncated exit count we'll truncate the IV when comparing
against the limit, in which case exit count overflow in post-inc
form doesn't matter. However, for pointer IVs we don't do that, so
we have to be careful about incrementing the IV in the wide type.

I'm fixing this by removing the IVCount variable (which was
ExitCount or ExitCount+1) and replacing it with a UsePostInc flag,
and then moving the actual limit adjustment to the individual cases
(which are: pointer IV where we add to the wide type, integer IV
where we add to the narrow type, and constant integer IV where we
add to the wide type).

Differential Revision: https://reviews.llvm.org/D63686

llvm-svn: 364709
2019-06-29 09:24:12 +00:00
Sam Clegg
a5a2205776 Partial revert of "[llvm-ar] Document response file support in --help"
This is partial revert of 70a8027c60fe1f95e8a8a1ff6575ebf8778d3544.

The test apparently failed on win32 bots due to the way slashes in
pathnames are handled.

llvm-svn: 364705
2019-06-29 01:53:26 +00:00
Matt Arsenault
d13ac7e93c AMDGPU/GlobalISel: Add some more tests for icmp select
llvm-svn: 364703
2019-06-29 00:55:16 +00:00
Matt Arsenault
9eb156737f AMDGPU/GlobalISel: RegBankSelect for update.dpp
llvm-svn: 364701
2019-06-29 00:44:36 +00:00
Matt Arsenault
5dd3fb80c4 AMDGPU/GlobalISel: RegBankSelect for atomic.inc/atomic.dec
llvm-svn: 364699
2019-06-29 00:39:20 +00:00
Matt Arsenault
75e02974f3 AMDGPU/GlobalISel: RegBankSelect for some DS intrinsics
llvm-svn: 364698
2019-06-29 00:33:13 +00:00
Matt Arsenault
a229c10e69 AMDGPU/GlobalISel: RegBankSelect for some easy intrinsics
llvm-svn: 364697
2019-06-29 00:29:56 +00:00
Matt Arsenault
f2f3b70381 AMDGPU/GlobalISel: RegBankSelect for icmp/fcmp intrinsics
llvm-svn: 364696
2019-06-29 00:28:52 +00:00
Matt Arsenault
6c3d7544cc AMDGPU/GlobalISel: RegBankSelect for amdgcn.div.fmas
llvm-svn: 364695
2019-06-29 00:25:53 +00:00
Matt Arsenault
30df001b5d AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
llvm-svn: 364694
2019-06-29 00:22:28 +00:00
Philip Reames
4e43cc3a25 [IndVars] Remove a bit of manual constant folding [NFC]
SCEV is more than capable of folding (add x, trunc(0)) to x.  

llvm-svn: 364693
2019-06-29 00:19:31 +00:00
Matt Arsenault
25324b5081 AMDGPU: Add baseline test for packed shufflevector
llvm-svn: 364691
2019-06-28 23:43:40 +00:00
Wouter van Oortmerssen
1ff5ed90df [WebAssembly] Assembler: support .int16/32/64 directives.
Reviewers: sbc100

Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63959

llvm-svn: 364689
2019-06-28 22:20:33 +00:00
Wouter van Oortmerssen
cc716d78a8 [WebAssembly] Allow @object in .type directives.
Reviewers: sbc100

Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63955

llvm-svn: 364688
2019-06-28 21:53:11 +00:00
Sanjay Patel
3620c94af7 [x86] remove stale comment about cmov; NFC
The cmov node used to sometimes return a glue result (and that's what
'flag' meant in this context), but that was removed with D38664.

llvm-svn: 364687
2019-06-28 21:45:55 +00:00
Cameron McInally
e7a7f50943 [NFC][NewGVN] Explicitly check fpmath metadata in fpmath.ll
Suggested in D63933.

llvm-svn: 364685
2019-06-28 21:39:08 +00:00
Sanjay Patel
a04e50b4eb [Lanai] auto-generate complete test checks; NFC
This file will fail with a common codegen transform that
I'm looking at, and I can't tell if that's an improvement
or regression based on the sparse checking.

llvm-svn: 364684
2019-06-28 20:45:32 +00:00
Wouter van Oortmerssen
d3dc642675 [WebAssembly] Assembler: Allow offsets and p2align in symbol load.
Reviewers: sbc100

Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63951

llvm-svn: 364682
2019-06-28 20:31:13 +00:00
Wouter van Oortmerssen
34f2e2f14b [WebAssembly] Assembler: Improve section parsing.
Reviewers: sbc100

Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63947

llvm-svn: 364681
2019-06-28 20:29:16 +00:00
Cameron McInally
aa9574f6e6 [NewGVN] Add unary FNeg support to NewGVN pass
Differential Revision: https://reviews.llvm.org/D63933

llvm-svn: 364680
2019-06-28 20:09:32 +00:00
Cameron McInally
f51987bd8e [GVNSink] Add unary FNeg support to GVNSink pass
Differential Revision: https://reviews.llvm.org/D63900

llvm-svn: 364678
2019-06-28 19:57:31 +00:00
Erik Pilkington
e48e888008 [demangle] Support for C++2a char8_t
llvm-svn: 364677
2019-06-28 19:54:19 +00:00
Brad Smith
1137ec78d2 Default to Secure PLT on PPC for musl libc.
This matches the default settings of clang.

llvm-svn: 364675
2019-06-28 19:48:31 +00:00
Sam Clegg
b388897043 [llvm-ar] Document response file support in --help
Also a test for this.

Differential Revision: https://reviews.llvm.org/D63836

llvm-svn: 364673
2019-06-28 18:48:05 +00:00
Lang Hames
4890f2a545 Re-apply r364600 with fixes.
Fix: MachO/X86_64_RELOC_GOT is a 32-bit reloc, so only compare 32 bits.
llvm-svn: 364672
2019-06-28 18:36:59 +00:00
Rainer Orth
20567f8219 [unittests][Support] Fix LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions on Solaris
LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions currently
FAILs on Solaris:

  FAIL: LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions (2940 of 51555)
  ******************** TEST 'LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions' FAILED ********************
  Note: Google Test filter = FileSystemTest.permissions
  [==========] Running 1 test from 1 test case.
  [----------] Global test environment set-up.
  [----------] 1 test from FileSystemTest
  [ RUN      ] FileSystemTest.permissions
  /opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1705: Failure
  Value of: CheckPermissions(fs::sticky_bit)
    Actual: false
  Expected: true
  /opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1712: Failure
  Value of: CheckPermissions(fs::set_uid_on_exe | fs::set_gid_on_exe | fs::sticky_bit)
    Actual: false
  Expected: true
  /opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1719: Failure
  Value of: CheckPermissions(fs::all_read | fs::set_uid_on_exe | fs::set_gid_on_exe | fs::sticky_bit)
    Actual: false
  Expected: true
  /opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1722: Failure
  Value of: CheckPermissions(fs::all_perms)
    Actual: false
  Expected: true
  [  FAILED  ] FileSystemTest.permissions (0 ms)
  [----------] 1 test from FileSystemTest (0 ms total)
  
  [----------] Global test environment tear-down
  [==========] 1 test from 1 test case ran. (1 ms total)
  [  PASSED  ] 0 tests.
  [  FAILED  ] 1 test, listed below:
  [  FAILED  ] FileSystemTest.permissions
  
   1 FAILED TEST

Checking with truss reveals that this is the same issue as on AIX and
documented in chmod(2):

  If the process is not a privileged process and the file is not a direc-
  tory, mode bit 01000 (S_ISVTX, the sticky bit) is cleared.

The following patch fixes this in the same way.  Tested on amd64-pc-solaris2.11.

Differential Revision: https://reviews.llvm.org/D63598

llvm-svn: 364671
2019-06-28 18:29:18 +00:00
Jinsong Ji
d8b5b763b2 [UpdateChecks] Add support for armv7-apple-darwin
armv7-apple-darwin was not supported well, the script can't generate
checks.

https://reviews.llvm.org/D60601/new/#inline-568671

Differential Revision: https://reviews.llvm.org/D63939

llvm-svn: 364668
2019-06-28 18:07:19 +00:00
Simon Pilgrim
b52c8f5066 [X86] CombineShuffleWithExtract - recurse through EXTRACT_SUBVECTOR chain
llvm-svn: 364667
2019-06-28 17:57:32 +00:00
Peter Collingbourne
ac22a944f7 hwasan: Remove the old frame descriptor mechanism.
Differential Revision: https://reviews.llvm.org/D63470

llvm-svn: 364665
2019-06-28 17:53:26 +00:00
Roman Lebedev
e751570ab5 [NFC][Codegen] Revisit test coverage for X % C == 0 fold once more (add tests with '1' divisor)
llvm-svn: 364661
2019-06-28 17:26:28 +00:00
Wouter van Oortmerssen
4f70d23e34 [WebAssembly] Added visibility and ident directives to WasmAsmParser.
Summary:
These are output by clang -S, so can now be roundtripped thru clang.

(partially) fixes: https://bugs.llvm.org/show_bug.cgi?id=34544

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63901

llvm-svn: 364658
2019-06-28 16:51:06 +00:00
Roman Lebedev
5e1e493a46 [NFC][InstCombine] Shift amount reassociation: revisit flag preservation tests
llvm-svn: 364657
2019-06-28 16:36:53 +00:00
Dmitry Preobrazhensky
6c92b88d5f [AMDGPU][MC] Fix 2 for sanitizer failure in 364645
llvm-svn: 364656
2019-06-28 16:28:46 +00:00
Sam Tebbs
9cb186cbd7 [ARM] Add support for the MVE long shift instructions
MVE adds the lsll, lsrl and asrl instructions, which perform a shift on a 64 bit value separated into two 32 bit registers.

The Expand64BitShift function is modified to accept ISD::SHL, ISD::SRL and ISD::SRA and convert it into the appropriate opcode in ARMISD. An SHL is converted into an lsll, an SRL is converted into an lsrl for the immediate form and a negation and lsll for the register form, and SRA is converted into an asrl.

test/CodeGen/ARM/shift_parts.ll is added to test the logic of emitting these instructions.

Differential Revision: https://reviews.llvm.org/D63430

llvm-svn: 364654
2019-06-28 15:43:31 +00:00
Max Moroz
33e65f7a8d [llvm-cov[ Fix lcov coverage report contains functions from other compilation units.
Summary: Patch by Chuan Qiu (@eagleonhill).

Reviewers: Dor1s

Reviewed By: Dor1s

Subscribers: lebedev.ri, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63571

llvm-svn: 364653
2019-06-28 15:38:25 +00:00
Roman Lebedev
fe0c0ec855 [NFC][InstCombine] Shift amount reassociation: add flag preservation test
As discussed in https://reviews.llvm.org/D63812#inline-569870
* exact on both lshr => exact https://rise4fun.com/Alive/plHk
* exact on both ashr => exact https://rise4fun.com/Alive/QDAA
* nuw on both shl => nuw https://rise4fun.com/Alive/5Uk
* nsw on both shl => nsw https://rise4fun.com/Alive/0plg

So basically if the same flag is set on both original shifts -> set it on new shift.
Don't think we can do anything with non-matching flags on shl.

llvm-svn: 364652
2019-06-28 15:32:52 +00:00
Dmitry Preobrazhensky
8f59e33cae [AMDGPU][MC] Fix for sanitizer failure in 364645
llvm-svn: 364651
2019-06-28 15:22:47 +00:00
Cameron McInally
191ce2d78b [NFC][Float2Int] Pre-commit unary FNeg test to basic.ll
llvm-svn: 364649
2019-06-28 15:12:15 +00:00
Cameron McInally
35f315d6b5 [NFC][NewGVN] Pre-commit unary FNeg test to fpmath.ll
llvm-svn: 364646
2019-06-28 14:39:58 +00:00
Dmitry Preobrazhensky
fa8b9a2b13 [AMDGPU][MC] Enabled constant expressions as operands of sendmsg
See bug 40820: https://bugs.llvm.org/show_bug.cgi?id=40820

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D62735

llvm-svn: 364645
2019-06-28 14:14:02 +00:00
Simon Pilgrim
b3a9936a52 [X86] CombineShuffleWithExtract - only require 1 source to be EXTRACT_SUBVECTOR
We were requiring that both shuffle operands were EXTRACT_SUBVECTORs, but we can relax this to only require one of them to be.

Also, we shouldn't bother attempting this if both operands are from the lowest subvector (or not EXTRACT_SUBVECTOR at all).

llvm-svn: 364644
2019-06-28 12:24:49 +00:00
David Green
b31fe8a61f [ARM] Add MVE mul patterns
This simply adds integer and floating point VMUL patterns for MVE, same as we
have add and sub.

Differential Revision: https://reviews.llvm.org/D63866

llvm-svn: 364643
2019-06-28 11:44:03 +00:00
Roman Lebedev
ca607f6065 [NFC][Codegen] Revisit test coverage for X % C == 0 fold
llvm-svn: 364642
2019-06-28 11:36:34 +00:00
David Green
ccaf3a8289 [ARM] Mark math routines as non-legal for MVE
This adds handling and tests for a number of floating point math routines,
which have no MVE instructions.

Differential Revision: https://reviews.llvm.org/D63725

llvm-svn: 364641
2019-06-28 11:17:38 +00:00
David Green
3fe9ee1573 [ARM] MVE patterns for VABS and VNEG
This simply adds the required patterns for fp neg and abs.

Differential Revision: https://reviews.llvm.org/D63861

llvm-svn: 364640
2019-06-28 10:25:35 +00:00
Fangrui Song
edf3226d9f [DebugInfo] Fix setStartAddress after r364637
llvm-svn: 364638
2019-06-28 10:10:10 +00:00
Fangrui Song
3c005f1680 [DebugInfo] Simplify GSYM::AddressRange and GSYM::AddressRanges
Delete unnecessary getters of AddressRange.
Simplify AddressRange::size(): Start <= End check should be checked in an upper layer.
Delete isContiguousWith() that doesn't make sense.
Simplify AddressRanges::insert. Delete commented code. Fix it when more than 1 ranges are to be deleted.
Delete trailing newline.

llvm-svn: 364637
2019-06-28 10:06:11 +00:00
David Green
a82cfd92f0 [ARM] Widening loads and narrowing stores
MVE has instructions to widen as it loads, and narrow as it stores. This adds
the required patterns and legalisation to make them work including specifying
that they are legal, patterns to select them and test changes.

Patch by David Sherwood.

Differential Revision: https://reviews.llvm.org/D63839

llvm-svn: 364636
2019-06-28 09:47:55 +00:00
Simon Tatham
71bd4491d3 [ARM] Fix integer UB in MVE load/store immediate handling.
llvm-svn: 364635
2019-06-28 09:28:39 +00:00