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Commit Graph

93359 Commits

Author SHA1 Message Date
Ulrich Weigand
90cbe0a2da [PowerPC] Add support for TLS data relocations
This adds support for TLS data relocations and modifiers:
       .quad target@dtpmod
       .quad target@tprel
       .quad target@dtprel
Currently exploited by the asm parser only.

llvm-svn: 185394
2013-07-01 23:33:29 +00:00
Jakob Stoklund Olesen
43f394b1c6 Remove floating point computations form SpillPlacement.cpp.
Patch by Benjamin Kramer!

Use the BlockFrequency class instead of floats in the Hopfield network
computations. This rescales the node Bias field from a [-2;2] float
range to two block frequencies BiasN and BiasP pulling in opposite
directions. This construct has a more predictable behavior when block
frequencies saturate.

The per-node scaling factors are no longer necessary, assuming the block
frequencies around a bundle are consistent.

This patch can cause the register allocator to make different spilling
decisions. The differences should be small.

llvm-svn: 185393
2013-07-01 23:19:39 +00:00
Richard Trieu
e3ad5f5650 Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ...
llvm-svn: 185392
2013-07-01 23:06:23 +00:00
Ulrich Weigand
0bbaa6dd10 [PowerPC] Fix 32-bit PowerPC TLS relocs
Some TLS relocs were copied incorrectly from ppc64 to ppc32,
and some were missing completely.

llvm-svn: 185390
2013-07-01 22:27:57 +00:00
David Blaikie
b019759ec4 PR16493: DebugInfo with TLS on PPC crashing due to invalid relocation
Restrict the current TLS support to X86 ELF for now. Test that we don't
produce it on PPC & we can flesh that test case out with the right thing
once someone implements it.

llvm-svn: 185389
2013-07-01 21:45:25 +00:00
Ulrich Weigand
534abefa5c [PowerPC] Support all condition register logical instructions
This adds support for all missing condition register logical
instructions and extended mnemonics to the asm parser.

llvm-svn: 185387
2013-07-01 21:40:54 +00:00
Chad Rosier
6343db9e94 Add a newline.
llvm-svn: 185385
2013-07-01 21:31:10 +00:00
Manman Ren
8b22b0ee27 Debug Info: clean up usage of Verify.
No functionality change. It should suffice to check the type of a debug info
metadata, instead of calling Verify.

llvm-svn: 185383
2013-07-01 21:02:01 +00:00
Bill Schmidt
4e099704b5 Index: test/CodeGen/PowerPC/reloc-align.ll
===================================================================
--- test/CodeGen/PowerPC/reloc-align.ll	(revision 0)
+++ test/CodeGen/PowerPC/reloc-align.ll	(revision 0)
@@ -0,0 +1,34 @@
+; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s
+
+; This test verifies that the peephole optimization of address accesses
+; does not produce a load or store with a relocation that can't be
+; satisfied for a given instruction encoding.  Reduced from a test supplied
+; by Hal Finkel.
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.S1 = type { [8 x i8] }
+
+@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1
+
+; Function Attrs: nounwind readonly
+define signext i32 @main() #0 {
+entry:
+  %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*))
+; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l
+  ret i32 %call
+}
+
+; Function Attrs: nounwind readonly
+define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 {
+entry:
+  %0 = bitcast %struct.S1* %p_91 to i64*
+  %bf.load = load i64* %0, align 1
+  %bf.shl = shl i64 %bf.load, 26
+  %bf.ashr = ashr i64 %bf.shl, 54
+  %bf.cast = trunc i64 %bf.ashr to i32
+  ret i32 %bf.cast
+}
+
+attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
Index: lib/Target/PowerPC/PPCAsmPrinter.cpp
===================================================================
--- lib/Target/PowerPC/PPCAsmPrinter.cpp	(revision 185327)
+++ lib/Target/PowerPC/PPCAsmPrinter.cpp	(working copy)
@@ -679,7 +679,26 @@ void PPCAsmPrinter::EmitInstruction(const MachineI
       OutStreamer.EmitRawText(StringRef("\tmsync"));
       return;
     }
+    break;
+  case PPC::LD:
+  case PPC::STD:
+  case PPC::LWA: {
+    // Verify alignment is legal, so we don't create relocations
+    // that can't be supported.
+    // FIXME:  This test is currently disabled for Darwin.  The test
+    // suite shows a handful of test cases that fail this check for
+    // Darwin.  Those need to be investigated before this sanity test
+    // can be enabled for those subtargets.
+    if (!Subtarget.isDarwin()) {
+      unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1;
+      const MachineOperand &MO = MI->getOperand(OpNum);
+      if (MO.isGlobal() && MO.getGlobal()->getAlignment() < 4)
+        llvm_unreachable("Global must be word-aligned for LD, STD, LWA!");
+    }
+    // Now process the instruction normally.
+    break;
   }
+  }
 
   LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
   OutStreamer.EmitInstruction(TmpInst);
Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelDAGToDAG.cpp	(revision 185327)
+++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp	(working copy)
@@ -1530,6 +1530,14 @@ void PPCDAGToDAGISel::PostprocessISelDAG() {
       if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
         SDLoc dl(GA);
         const GlobalValue *GV = GA->getGlobal();
+        // We can't perform this optimization for data whose alignment
+        // is insufficient for the instruction encoding.
+        if (GV->getAlignment() < 4 &&
+            (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
+             StorageOpcode == PPC::LWA)) {
+          DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
+          continue;
+        }
         ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
       } else if (ConstantPoolSDNode *CP =
                  dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {

llvm-svn: 185380
2013-07-01 20:52:27 +00:00
Chad Rosier
54c8df1202 [ARMAsmParser] Sort the ARM register lists based on the encoding value, not the
tablegen enum values.  This should be the last fix due to fallout from r185094.

llvm-svn: 185379
2013-07-01 20:49:23 +00:00
Lang Hames
fa00d243cb Make PBQP require/preserve MachineLoopInfo - the spiller requires it.
llvm-svn: 185378
2013-07-01 20:47:47 +00:00
Sean Silva
01748e811b [docs] Amend confusing title
"Writing an LLVM Compiler Backend" can be misinterpreted as meaning
"backend" in the sense of "using LLVM as a backend for your compiler for
your new language". This new name is less ambiguous.

As a bonus, this brings the title in line with the file name.

llvm-svn: 185377
2013-07-01 20:45:12 +00:00
Akira Hatanaka
c5fa7b5e51 [mips] Reverse the order of source operands of shift and rotate instructions that
have three register operands.

No intended functionality changes.

llvm-svn: 185376
2013-07-01 20:39:53 +00:00
Ulrich Weigand
4261958c61 [PowerPC] Also add "msync" alias
This adds an alias for "msync" (which is used on Book E
systems instead of "sync").

llvm-svn: 185375
2013-07-01 20:39:50 +00:00
Akira Hatanaka
3787fb8dc0 [mips] Increase the number of floating point control registers available to 32.
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.

llvm-svn: 185373
2013-07-01 20:31:44 +00:00
Akira Hatanaka
a704ad94d7 [mips] Fix test case to check that mips64 instructions are generated.
llvm-svn: 185371
2013-07-01 20:18:58 +00:00
Anton Korobeynikov
a6a4ed92ee Really fix the test. Sorry for the breakage...
llvm-svn: 185369
2013-07-01 19:51:36 +00:00
Anton Korobeynikov
8e5dfb5ca4 Fix the test which relies on uncommitted change
llvm-svn: 185368
2013-07-01 19:50:31 +00:00
Cameron Zwarich
6fa864e601 Fix the build after r185363. Use llvm::next instead of raw next.
llvm-svn: 185367
2013-07-01 19:49:48 +00:00
Anton Korobeynikov
f6e50fd093 Add jump tables handling for MSP430.
Patch by Job Noorman!

llvm-svn: 185364
2013-07-01 19:44:44 +00:00
Cameron Zwarich
7af5158621 Fix PR16508.
When phis get lowered, destination copies are inserted using an iterator that is
determined once for all phis in the block, which BuildMI interprets as a request
to insert an instruction directly before the iterator. In the case of a cyclic
phi, source copies may also be inserted directly before this iterator, which can
cause source copies to be inserted before destination copies. The fix is to keep
an iterator to the last phi and then advance it while lowering each phi in order
to insert destination copies directly after the phis.

llvm-svn: 185363
2013-07-01 19:42:46 +00:00
Hal Finkel
0b854b8c04 Don't form PPC CTR loops for over-sized exit counts
Although you can't generate this from C on PPC64, if you have a loop using a
64-bit counter on PPC32 then you can't form a CTR-based loop for it. This had
been cauing the PPCCTRLoops pass to assert.

Thanks to Joerg Sonnenberger for providing a test case!

llvm-svn: 185361
2013-07-01 19:34:59 +00:00
Tim Northover
c1348880dc AArch64: correct CodeGen of MOVZ/MOVK combinations.
According to the AArch64 ELF specification (4.6.8), it's the
assembler's responsibility to make sure the shift amount is correct in
relocated MOVZ/MOVK instructions.

This wasn't being obeyed by either the MCJIT CodeGen or RuntimeDyldELF
(which happened to work out well for JIT tests). This commit should
make us compliant in this area.

llvm-svn: 185360
2013-07-01 19:23:10 +00:00
Matt Beaumont-Gay
aae6843783 (1) Add ".test" to test/Other/lit.local.cfg, so llvm-cov.test is actually run.
(2) Rename llvm-cov test inputs so the string "llvm-cov" doesn't get
substituted by lit within the input filenames on the RUN line.
(3) XFAIL llvm-cov.test because it asserts:
include/llvm/ADT/SmallVector.h:140: reference llvm::SmallVectorTemplateCommon<llvm::GCOVBlock *, void>::operator[](unsigned int) [T = llvm::GCOVBlock *]: Assertion `begin() + idx < end()' failed.

llvm-svn: 185358
2013-07-01 18:58:53 +00:00
Tim Northover
51fd747de9 Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst")
Turns out I'd misread the architecture reference manual and thought
that was a load/store-store barrier, when it's not.

Thanks for pointing it out Eli!

llvm-svn: 185356
2013-07-01 18:37:33 +00:00
Manman Ren
3985839b7f Debug Info: Scope of a DebugLoc should not be null.
No functionality change. Remove handling for the null case.

llvm-svn: 185354
2013-07-01 18:20:30 +00:00
Ulrich Weigand
bd21c2da50 [PowerPC] Fix @got references to local symbols
A @got reference must always result in a relocation, so that
the linker has a chance to set up the GOT entry, even if the
symbol happens to be local.

Add a PPCELFObjectWriter::ExplicitRelSym routine that enforces
a relocation to be emitted for GOT references.

llvm-svn: 185353
2013-07-01 18:19:56 +00:00
Ulrich Weigand
27e2e6a158 [PowerPC] Add "wait" instruction
This adds the "wait" instruction and its extended mnemonics.

llvm-svn: 185350
2013-07-01 17:21:23 +00:00
Ulrich Weigand
22cc4fd86f [PowerPC] Support "eieio" instruction
This adds support for the "eieio" instruction to
the asm parser.

llvm-svn: 185349
2013-07-01 17:06:26 +00:00
Michael Gottesman
61e2254d15 Added c++ mode selector to head of SelectionDAGBuilder.h so editors open it in c++ mode instead of c mode.
llvm-svn: 185348
2013-07-01 16:53:41 +00:00
Ulrich Weigand
ec5b1279ef [PowerPC] Add some existing instructions to ppc64-encoding-bookII.s
The test case had a couple of FIXMEs where the instruction is in
fact already supported by the back-end.  In some other case, while
the generic form of the instruction is not yet supported, a
specialized form is.  This adds tests for those already supported
instructions / instruction forms.

llvm-svn: 185347
2013-07-01 16:52:55 +00:00
Ulrich Weigand
9dfc60786f [PowerPC] Add variants of "sync" instruction
This adds support for the "sync $L" instruction with operand,
and provides aliases for "lwsync" and "ptesync".

llvm-svn: 185344
2013-07-01 16:37:52 +00:00
Tim Northover
25286e5b71 ARM: relax the atomic release barrier to "dmb ishst"
I believe the full "dmb ish" barrier is not required to guarantee release
semantics for atomic operations. The weaker "dmb ishst" prevents previous
operations being reordered with a store executed afterwards, which is enough.

A key point to note (fortunately already correct) is that this barrier alone is
*insufficient* for sequential consistency, no matter how liberally placed.

llvm-svn: 185339
2013-07-01 14:48:48 +00:00
Justin Holewinski
d88c5d6e19 [NVPTX] Add support for module-scope inline asm
Since we were explicitly not calling AsmPrinter::doInitialization,
any module-scope inline asm was not being printed.

llvm-svn: 185336
2013-07-01 13:00:14 +00:00
Justin Holewinski
f5ae252158 [NVPTX] We dont use NVBuiltin anymore
llvm-svn: 185335
2013-07-01 12:59:08 +00:00
Justin Holewinski
942960b94a [NVPTX] Cut down on physical register defs
We are using virtual registers throughout now, but we still need
to keep a few physical registers per class around to keep the
infrastructure happy.

llvm-svn: 185334
2013-07-01 12:59:06 +00:00
Justin Holewinski
89a1f98197 [NVPTX] 64-bit ADDC/ADDE are not legal
llvm-svn: 185333
2013-07-01 12:59:04 +00:00
Justin Holewinski
6284a5cea6 [NVPTX] Fix vector loads from parameters that span multiple loads, and fix some typos
llvm-svn: 185332
2013-07-01 12:59:01 +00:00
Justin Holewinski
77ba2f5ed9 [NVPTX] Handle signext/zeroext attributes properly
Fix a case where we were incorrectly sign-extending a value when we should have been zero-extending the value.

Also change some SIGN_EXTEND to ANY_EXTEND because we really dont care and may have more opportunity to fold subexpressions

llvm-svn: 185331
2013-07-01 12:58:58 +00:00
Justin Holewinski
46fe052e1f [NVPTX] Add support for native SIGN_EXTEND_INREG where available
llvm-svn: 185330
2013-07-01 12:58:56 +00:00
Justin Holewinski
46d3cad4d8 [NVPTX] Add isel patterns for [reg+offset] form of ldg/ldu.
llvm-svn: 185329
2013-07-01 12:58:52 +00:00
Justin Holewinski
c254f0f839 [NVPTX] Make sure we zero out high-order 24 bits for 8-bit load into 32-bit value
llvm-svn: 185328
2013-07-01 12:58:48 +00:00
NAKAMURA Takumi
49cb43826a llvm-symbolizer: Recognize a drive letter on win32. Then "REQUIRES: shell" can be removed.
FIXME: Could we use llvm::sys::Path here?
llvm-svn: 185322
2013-07-01 09:51:42 +00:00
Serge Pavlov
8e65c835cb Added the test missed from r185080.
llvm-svn: 185316
2013-07-01 09:02:33 +00:00
Sylvestre Ledru
78dbd1cae5 The build system is currently miss-identifying GNU/kFreeBSD as FreeBSD.
This kind of simplification is sometimes useful, but in general it's not correct. 

As GNU/kFreeBSD is an hybrid system, for kernel-related issues we want to match the
build definitions used for FreeBSD, whereas for userland-related issues we want to
match the definitions used for other systems with Glibc.

The current modification adjusts the build system so that they can be distinguished,
and explicitly adds GNU/kFreeBSD to the build checks in which it belongs.

Fixes bug #16444.

Patch by Robert Millan in the context of Debian.

llvm-svn: 185311
2013-07-01 08:07:52 +00:00
Arnold Schwaighofer
26461b04c7 LoopVectorize: Math functions only read rounding mode
Math functions are mark as readonly because they read the floating point
rounding mode. Because we don't vectorize loops that would contain function
calls that set the rounding mode it is safe to ignore this memory read.

llvm-svn: 185299
2013-07-01 00:54:44 +00:00
Vincent Lejeune
8a53bf61f4 R600: Fix an unitialized variable in R600InstrInfo.cpp
llvm-svn: 185294
2013-06-30 21:44:06 +00:00
Ahmed Bougacha
1560b2eb19 X86: POP*rmm: move address operand to (ins) from (outs).
llvm-svn: 185292
2013-06-30 20:44:50 +00:00
Stephen Lin
d9ddb58848 DeadArgumentElimination: keep return value on functions that have a live argument with the 'returned' attribute (rather than generate invalid IR); however, if both can be eliminated, both will be
llvm-svn: 185290
2013-06-30 20:26:21 +00:00
Benjamin Kramer
dc3c6d36e0 ConstantFold: Check that truncating the other side is safe under a sext when trying to remove a sext from a compare.
Fixes PR16462.

llvm-svn: 185284
2013-06-30 13:47:43 +00:00