1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-31 16:02:52 +01:00
Commit Graph

90686 Commits

Author SHA1 Message Date
Hal Finkel
9191cdb5f2 Fix a bad assert in PPCTargetLowering
llvm-svn: 178489
2013-04-01 18:42:58 +00:00
Hal Finkel
9cd1e5e93c Add triple to test/CodeGen/PowerPC/stfiwx-2
llvm-svn: 178486
2013-04-01 18:18:44 +00:00
Shuxin Yang
74f54ae4b2 Correct assertion condition
llvm-svn: 178484
2013-04-01 18:13:05 +00:00
Arnold Schwaighofer
a2a475a83d Merge load/store sequences with adresses: base + index + offset
We would also like to merge sequences that involve a variable index like in the
example below.

    int index = *idx++
    int i0 = c[index+0];
    int i1 = c[index+1];
    b[0] = i0;
    b[1] = i1;

By extending the parsing of the base pointer to handle dags that contain a
base, index, and offset we can handle examples like the one above.

The dag for the code above will look something like:

 (load (i64 add (i64 copyfromreg %c)
                (i64 signextend (i8 load %index))))

 (load (i64 add (i64 copyfromreg %c)
                (i64 signextend (i32 add (i32 signextend (i8 load %index))
                                         (i32 1)))))

The code that parses the tree ignores the intermediate sign extensions. However,
if there is a sign extension it needs to be on all indexes.

 (load (i64 add (i64 copyfromreg %c)
                (i64 signextend (add (i8 load %index)
                                     (i8 1))))
 vs

 (load (i64 add (i64 copyfromreg %c)
                (i64 signextend (i32 add (i32 signextend (i8 load %index))
                                         (i32 1)))))
radar://13536387

llvm-svn: 178483
2013-04-01 18:12:58 +00:00
Hal Finkel
f184647a53 Add more PPC floating-point conversion instructions
The P7 and A2 have additional floating-point conversion instructions which
allow a direct two-instruction sequence (plus load/store) to convert from all
combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores,
only some combinations were directly available).

llvm-svn: 178480
2013-04-01 17:52:07 +00:00
Hal Finkel
6ce9279e28 Use ImmToIdxMap.count in PPCRegisterInfo
Code improvement suggested by Jakob (in review of r178450). No functionality
change intended.

llvm-svn: 178473
2013-04-01 17:02:06 +00:00
Hal Finkel
55f144f923 Fix PowerPC/cttz.ll to specify a cpu (and use FileCheck)
llvm-svn: 178472
2013-04-01 16:31:56 +00:00
Hal Finkel
9eed3ac928 Add the PPC popcntw instruction
The popcntw instruction is available whenever the popcntd instruction is
available, and performs a separate popcnt on the lower and upper 32-bits.
Ignoring the high-order count, this can be used for the 32-bit input case
(saving on the explicit zero extension otherwise required to use popcntd).

llvm-svn: 178470
2013-04-01 15:58:15 +00:00
Nadav Rotem
fe272b52da Add support for vector data types in the LLVM interpreter.
Patch by:
Veselov, Yuri <Yuri.Veselov@intel.com>

llvm-svn: 178469
2013-04-01 15:53:30 +00:00
Hal Finkel
91e522ef96 Treat PPCISD::STFIWX like the memory opcode that it is
PPCISD::STFIWX is really a memory opcode, and so it should come after
FIRST_TARGET_MEMORY_OPCODE, and we should use DAG.getMemIntrinsicNode to create
nodes using it.

No functionality change intended (although there could be optimization benefits
from preserving the MMO information).

llvm-svn: 178468
2013-04-01 15:37:53 +00:00
Duncan Sands
3137dc79c4 Remove unused typedef.
llvm-svn: 178462
2013-04-01 13:46:15 +00:00
Arnold Schwaighofer
38aac11be0 ARM Scheduler Model: Add resources instructions, map resources in subtargets
Reapply r177968:
After commit 178074 we can now have undefined scheduler variants.

Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.

Incooperate Andrew's feedback.

llvm-svn: 178460
2013-04-01 13:07:05 +00:00
Benjamin Kramer
7634eefc37 X86TTI: Add accurate costs for itofp operations, based on the actual instruction counts.
llvm-svn: 178459
2013-04-01 10:23:49 +00:00
Joe Abbey
f809052035 Whitespace cleanup
llvm-svn: 178454
2013-04-01 02:28:07 +00:00
Vincent Lejeune
30dc10604e R600: Emit native instructions for tex
llvm-svn: 178452
2013-03-31 19:33:04 +00:00
Duncan Sands
25d8fd3fd9 There is no longer any need to silence this compiler warning as the warning has
been turned off globally.

llvm-svn: 178451
2013-03-31 17:44:09 +00:00
Hal Finkel
7e07daa3d5 Cleanup ImmToIdxMap and noImmForm in PPCRegisterInfo
ImmToIdxMap should be a DenseMap (not a std::map) because there
is no ordering requirement. Also, we don't need a separate list
of instructions for noImmForm in eliminateFrameIndex, because this
list is essentially the complement of the keys in ImmToIdxMap.

No functionality change intended.

llvm-svn: 178450
2013-03-31 14:43:31 +00:00
Benjamin Kramer
790bd5fb50 X86: Promote sitofp <8 x i16> to <8 x i32> when AVX is available.
A vector sext + sitofp is a lot cheaper than 8 scalar conversions.

llvm-svn: 178448
2013-03-31 12:49:15 +00:00
Hal Finkel
085f61160f Add the PPC lfiwax instruction
This instruction is available on modern PPC64 CPUs, and is now used
to improve the SINT_TO_FP lowering (by eliminating the need for the
separate sign extension instruction and decreasing the amount of
needed stack space).

llvm-svn: 178446
2013-03-31 10:12:51 +00:00
Hal Finkel
7bdfbd6570 Cleanup PPC(64) i32 -> float/double conversion
The existing SINT_TO_FP code for i32 -> float/double conversion was disabled
because it relied on broken EXTSW_32/STD_32 instruction definitions. The
original intent had been to enable these 64-bit instructions to be used on CPUs
that support them even in 32-bit mode.  Unfortunately, this form of lying to
the infrastructure was buggy (as explained in the FIXME comment) and had
therefore been disabled.

This re-enables this functionality, using regular DAG nodes, but only when
compiling in 64-bit mode. The old STD_32/EXTSW_32 definitions (which were dead)
are removed.

llvm-svn: 178438
2013-03-31 01:58:02 +00:00
Benjamin Kramer
86e90ea8b4 DAGCombine: visitXOR can replace a node without returning it, bail out in that case.
Fixes the crash reported in PR15608.

llvm-svn: 178429
2013-03-30 21:28:18 +00:00
Justin Holewinski
8e3d59929c Add start of user documentation for NVPTX
Summary: This is the beginning of user documentation for the NVPTX back-end.  I want to ensure I am integrating this properly into the rest of the LLVM documentation.

Differential Revision: http://llvm-reviews.chandlerc.com/D600

llvm-svn: 178428
2013-03-30 16:41:14 +00:00
Benjamin Kramer
50725426cb Change '@SECREL' suffix to GAS-compatible '@SECREL32'.
'@SECREL' is what is used by the Microsoft assembler, but GNU as expects '@SECREL32'.
With the patch, the MC-generated code works fine in combination with a recent GNU as (2.23.51.20120920 here).

Patch by David Nadlinger!
Differential Revision: http://llvm-reviews.chandlerc.com/D429

llvm-svn: 178427
2013-03-30 16:21:50 +00:00
Sean Silva
f1daa4e46b [docs] llvmbugs is not the place for patches.
llvm-svn: 178426
2013-03-30 15:33:02 +00:00
Sean Silva
b2e6eb0354 [docs] Annotate mailing lists with their "name".
Nobody says "the developer's list" or "commits archive"; they always say
"llvmdev" or "llvm-commits". It makes sense for our documentation to
at least make that association explicitly.

llvm-svn: 178425
2013-03-30 15:33:01 +00:00
Sean Silva
61ad8bcdeb [docs] Reorganize mailing lists.
Order them roughly by "which one should a newbie join first".

llvm-svn: 178424
2013-03-30 15:32:54 +00:00
Sean Silva
7a23f14fdb [docs] Pull IRC and Mailing Lists under a new "Community" heading.
llvm-svn: 178423
2013-03-30 15:32:51 +00:00
Sean Silva
dd29200a97 [docs] The GEP FAQ is not "design and overview"
llvm-svn: 178422
2013-03-30 15:32:50 +00:00
Sean Silva
b35b1c47e9 [docs] Put DeveloperPolicy under "Development Process Documentation"
llvm-svn: 178421
2013-03-30 15:32:47 +00:00
Benjamin Kramer
19e3b89136 Put private class into an anonmyous namespace.
llvm-svn: 178420
2013-03-30 15:23:08 +00:00
Justin Holewinski
21480942b2 [NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.
llvm-svn: 178417
2013-03-30 14:29:30 +00:00
Justin Holewinski
23056edada [NVPTX] Add NVVMReflect pass to allow compile-time selection of
specific code paths.

This allows us to write code like:

  if (__nvvm_reflect("FOO"))
    // Do something
  else
    // Do something else

and compile into a library, then give "FOO" a value at kernel
compile-time so the check becomes a no-op.

llvm-svn: 178416
2013-03-30 14:29:25 +00:00
Justin Holewinski
707786b174 [NVPTX] Run clang-format on all NVPTX sources.
Hopefully this resolves any outstanding style issues and gives us
an automated way of ensuring we conform to the style guidelines.

llvm-svn: 178415
2013-03-30 14:29:21 +00:00
Benjamin Kramer
1b48942ea8 Object: Turn a couple of degenerate for loops into while loops.
No functionality change.

llvm-svn: 178413
2013-03-30 13:07:51 +00:00
Shuxin Yang
c53fc5dc4c Implement XOR reassociation. It is based on following rules:
rule 1: (x | c1) ^ c2 => (x & ~c1) ^ (c1^c2),
     only useful when c1=c2
  rule 2: (x & c1) ^ (x & c2) = (x & (c1^c2))
  rule 3: (x | c1) ^ (x | c2) = (x & c3) ^ c3 where c3 = c1 ^ c2
  rule 4: (x | c1) ^ (x & c2) => (x & c3) ^ c1, where c3 = ~c1 ^ c2

 It reduces an application's size (in terms of # of instructions) by 8.9%.
 Reviwed by Pete Cooper. Thanks a lot!

 rdar://13212115  

llvm-svn: 178409
2013-03-30 02:15:01 +00:00
Akira Hatanaka
bc81d23802 [mips] Add patterns for DSP indexed load instructions.
llvm-svn: 178408
2013-03-30 02:14:45 +00:00
Akira Hatanaka
fd5850047c [mips] Define reg+imm load/store pattern templates.
llvm-svn: 178407
2013-03-30 02:01:48 +00:00
Akira Hatanaka
5ff9493456 [mips] Fix DSP instructions to have explicit accumulator register operands.
Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.

llvm-svn: 178406
2013-03-30 01:58:00 +00:00
Akira Hatanaka
7573219c13 Remove unused variables.
llvm-svn: 178405
2013-03-30 01:46:28 +00:00
Akira Hatanaka
6c9ddf6943 [mips] Move the code which does dag-combine for multiply-add/sub nodes to
derived class MipsSETargetLowering.

We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16
doesn't have support for multipy-add/sub instructions.

llvm-svn: 178404
2013-03-30 01:42:24 +00:00
Akira Hatanaka
b8c6fcef56 [mips] Fix definitions of multiply, multiply-add/sub and divide instructions.
The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.

Mips16's instructions are unaffected by this change.

llvm-svn: 178403
2013-03-30 01:36:35 +00:00
Akira Hatanaka
01ec458f56 [mips] Remove function getFPBranchCodeFromCond. Rename invertFPCondCodeAdd.
llvm-svn: 178396
2013-03-30 01:16:38 +00:00
Akira Hatanaka
106cf732df Fix indentation.
llvm-svn: 178395
2013-03-30 01:15:17 +00:00
Akira Hatanaka
33684b1e2e [mips] Add mips-specific nodes which will be used to select multiply and divide
instructions.

llvm-svn: 178394
2013-03-30 01:14:04 +00:00
Akira Hatanaka
aa7cae6b45 [mips] Implement getRepRegClassFor in MipsSETargetLowering. This function is
called in several places in ScheduleDAGRRList.cpp.

llvm-svn: 178393
2013-03-30 01:12:05 +00:00
Akira Hatanaka
438e940329 [mips] Fix MipsSEInstrInfo::copyPhysReg, loadRegFromStack and storeRegToStack
to handle accumulator registers.

llvm-svn: 178392
2013-03-30 01:08:05 +00:00
Akira Hatanaka
51b8645403 [mips] Expand pseudo load, store and copy instructions right before
callee-saved scan.

The code makes use of register's scavenger's capability to spill multiple
registers.

llvm-svn: 178391
2013-03-30 01:04:11 +00:00
Akira Hatanaka
86302e607d [mips] Define pseudo instructions for spilling and copying accumulator
registers.

llvm-svn: 178390
2013-03-30 00:54:52 +00:00
Eric Christopher
05df599ea8 Use SmallVectorImpl instead of SmallVector at the uses.
llvm-svn: 178386
2013-03-29 23:34:06 +00:00
Bob Wilson
7e366d2845 Run the ObjCARCContract pass for LTO. <rdar://problem/13538084>
llvm-svn: 178385
2013-03-29 23:28:55 +00:00