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9215947c83
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16591 Commits

Author SHA1 Message Date
Rafael Espindola
9215947c83 There are two reasons why we might want to use 
foo = a - b
.long foo
instead of just
.long a - b

First, on darwin9 64 bits the assembler produces the wrong result. Second,
if "a" is the end of the section all darwin assemblers (9, 10 and mc) will not
consider a - b to be a constant but will if the dummy foo is created.

Split how we handle these cases. The first one is something MC should take care
of. The second one has to be handled by the caller.

llvm-svn: 120889
 2010-12-04 03:21:47 +00:00
Jim Grosbach
4c10ffa7c3 Encode condition code for Thumb1 conditional branch instruction. 
llvm-svn: 120865
 2010-12-04 00:20:40 +00:00
Jim Grosbach
1dac8796d5 Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible. 
tCMPzhir has undefined behavior when both source registers are low registers.
rdar://8728577

llvm-svn: 120858
 2010-12-03 23:54:18 +00:00
Bill Wendling
7e27f17312 Use correct variable names to match the patterns. 
llvm-svn: 120857
 2010-12-03 23:44:24 +00:00
Jim Grosbach
3b5c857f01 Match pattern operand names to expected encoding field names. This corrects the 
operand encoding ordering of the instruction.

llvm-svn: 120852
 2010-12-03 23:21:25 +00:00
Jim Grosbach
dbefb3e7e5 Remove incorrect BL target encoding (it's similar to, but not the same as the 
ARM instruction). Add encoding of bits 13 and 11.

llvm-svn: 120849
 2010-12-03 22:33:42 +00:00
Jim Grosbach
8cef570ed9 Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order 
halfword being emitted to the stream first. rdar://8728174

llvm-svn: 120848
 2010-12-03 22:31:40 +00:00
Nate Begeman
d4310b6d7c Revert this change since it breaks a couple of the AVX tests. 
I'm unclear if the tests are actually correct or not, but reverting for now.

llvm-svn: 120847
 2010-12-03 22:29:15 +00:00
Nate Begeman
deb26223bd Scalar f32/f64 are also subregs of ymm regs 
llvm-svn: 120844
 2010-12-03 21:54:39 +00:00
Nate Begeman
3911dcfd71 Remove SSE1-4 disable when AVX is enabled. While this may be useful for development, 
it completely breaks scalar fp in xmm regs when AVX is enabled.

llvm-svn: 120843
 2010-12-03 21:54:14 +00:00
Jim Grosbach
c69ad2176a When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the 
32-bit wide version by adding the .w suffix.

llvm-svn: 120838
 2010-12-03 20:33:01 +00:00
Benjamin Kramer
e27eff8888 Remove unused variable. 
llvm-svn: 120836
 2010-12-03 19:55:37 +00:00
Jim Grosbach
c8ce9a3453 Reduce t2 ldr/str instructions to the correct t1 versions when there's an 
immediate offset.

llvm-svn: 120833
 2010-12-03 19:47:11 +00:00
Jason W Kim
27bbab7e31 fix ARM::fixup_arm_branch, cleanup, and share more code between ELF and Darwin 
llvm-svn: 120832
 2010-12-03 19:40:23 +00:00
Jim Grosbach
25da270139 No need to declare EncoderMethod property anymore; just assign to it. 
llvm-svn: 120831
 2010-12-03 19:31:00 +00:00
Jim Grosbach
d0db6c9f0e Add FIXMEs. 
llvm-svn: 120824
 2010-12-03 18:37:17 +00:00
Jim Grosbach
dca34b5da7 Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD. 
llvm-svn: 120822
 2010-12-03 18:31:03 +00:00
Bill Wendling
b7df584ef7 Don't overwrite the opcode passed into the T1Special pattern. 
llvm-svn: 120782
 2010-12-03 02:02:58 +00:00
Bill Wendling
c4858cb4c3 Add Thumb encoding for some more instructions. 
llvm-svn: 120780
 2010-12-03 01:55:47 +00:00
Rafael Espindola
3e119b0bb4 Try to resolve symbol differences early, and if successful create a plain 
data fragment. This reduces the time to assemble the test in 8711 from 60s to
54s.

llvm-svn: 120767
 2010-12-03 00:55:40 +00:00
Bill Wendling
2f6a820abe The tLDR instruction wasn't encoded properly: 
<MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>>

Notice that the "reg" here is 0, which is an invalid register. Put a check in
the code for this to prevent crashing.

llvm-svn: 120766
 2010-12-03 00:53:22 +00:00
Jim Grosbach
0bd3b0fd6c Trailing whitespace. 
llvm-svn: 120748
 2010-12-02 23:05:38 +00:00
Devang Patel
822facd787 Use set directive for StartMinusEndExpr. 
This is a fix for llvm-gcc-i386-darwin9 buildbot failure.

llvm-svn: 120742
 2010-12-02 21:32:30 +00:00
Jim Grosbach
b6d0c8d5b1 When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes, 
not thumb2.

llvm-svn: 120711
 2010-12-02 16:42:25 +00:00
Jim Grosbach
78ef3199c8 Fix copy/pasto in vmin.f32 encoding. 
llvm-svn: 120709
 2010-12-02 16:30:58 +00:00
Wesley Peck
09a4bffe09 Teaching MBlaze backend how to reverse branch conditions. 
llvm-svn: 120707
 2010-12-02 16:17:11 +00:00
Jim Grosbach
0e71db6919 Add support for binary encoding of ARM 'adr' instructions referencing constant 
pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.

llvm-svn: 120635
 2010-12-02 00:28:45 +00:00
Devang Patel
409a5ff824 Revert r120580. 
llvm-svn: 120630
 2010-12-02 00:22:29 +00:00
Evan Cheng
4118b24aca Fix and re-enable tail call optimization of expanded libcalls. 
llvm-svn: 120622
 2010-12-01 22:59:46 +00:00
Jason W Kim
7d4b30652e fixing style nit: move class static to global static 
llvm-svn: 120619
 2010-12-01 22:46:50 +00:00
Bill Wendling
d85ff071c0 Add a post encoder method to the VFP instructions to convert them to the Thumb2 
encoding if we're in that mode.

llvm-svn: 120608
 2010-12-01 21:54:50 +00:00
Jim Grosbach
b1b1ff4271 Use the correct fixup type for ARM VLDR* 
llvm-svn: 120604
 2010-12-01 21:09:40 +00:00
Jim Grosbach
b2a12afa5f Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR 
instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.

llvm-svn: 120594
 2010-12-01 19:47:31 +00:00
Owen Anderson
8802c68592 Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax. 
llvm-svn: 120589
 2010-12-01 19:18:46 +00:00
Jason W Kim
d468d24fc9 kill trailing space 
llvm-svn: 120586
 2010-12-01 19:07:22 +00:00
Jim Grosbach
25b2b536f3 10 bits, not 12. 
llvm-svn: 120584
 2010-12-01 18:51:32 +00:00
Devang Patel
e68cb5a5cf Disable debug info for x86-darwin9 and earlier until PR 8715 and radar 8709290 are fixed. 
llvm-svn: 120580
 2010-12-01 16:59:34 +00:00
Duncan Sands
cd4f56b8e2 I don't think it makes any sense to assert that the target supports SSE3 here. 
The user (i.e. whoever generated a call to the intrinsic in the first place) is
essentially asking for a particular instruction to be placed in the assembler.
If that instruction won't execute on the target machine, that's their problem
not ours.  Two buildbots with processors that don't support SSE3 were barfing
on the apm.ll test in CodeGen/X86 because of this assertion.

llvm-svn: 120574
 2010-12-01 12:58:13 +00:00
Che-Liang Chiou
c61d8fa0e3 ptx: bug fix: use after free 
llvm-svn: 120571
 2010-12-01 11:45:53 +00:00
Jim Grosbach
a3e6ffffe5 Elaborate on FIXME. 
llvm-svn: 120552
 2010-12-01 04:01:17 +00:00
Jim Grosbach
b2044fcba1 Move the ARMAsmPrinter class defintiion into a header file. 
llvm-svn: 120551
 2010-12-01 03:45:07 +00:00
Evan Cheng
84162760b7 Speculatively disable x86 portion of r120501 to appease the x86_64 buildbot. 
llvm-svn: 120549
 2010-12-01 03:27:20 +00:00
Bill Wendling
e62557dc3c Remove "comparison of integers of different signs" warning by making the 
variable unsigned.

llvm-svn: 120541
 2010-12-01 02:49:04 +00:00
Bill Wendling
4fc1c4ee84 General cleanups of comments. 
llvm-svn: 120536
 2010-12-01 02:42:55 +00:00
Jason W Kim
4d960e071c ARM/MC/ELF relocation "hello world" for movw/movt. 
Lifted adjustFixupValue() from Darwin for sharing w ELF.
Test added
TODO:
  refactor ELFObjectWriter::RecordRelocation more.
  Possibly share more code with Darwin?
  Lots more relocations...

llvm-svn: 120534
 2010-12-01 02:40:06 +00:00
Bill Wendling
b7635b1ed3 Formatting. It's all the rage! 
llvm-svn: 120533
 2010-12-01 02:36:55 +00:00
Bill Wendling
8861fb7484 More refactoring. This time the T1pI pattern. 
llvm-svn: 120532
 2010-12-01 02:28:08 +00:00
Eric Christopher
5f7eeae6ba Refactor load/store handling again. Simplify and make some room for 
reg+reg handling.

llvm-svn: 120526
 2010-12-01 01:40:24 +00:00
Jan Wen Voung
c34fbc5bb1 Initialize an ARMConstantPoolValue field. 
llvm-svn: 120525
 2010-12-01 01:38:58 +00:00
Bill Wendling
ccfea264ff s/T1pIEncode/T1pILdStEncode/g 
s/T1pIEncodeImm/T1pILdStEncodeImm/g

llvm-svn: 120524
 2010-12-01 01:38:08 +00:00