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Commit Graph

133678 Commits

Author SHA1 Message Date
Sanjay Patel
93d8c284d1 [InstCombine] update to use FileCheck with autogenerated exact checking
llvm-svn: 273180
2016-06-20 18:23:40 +00:00
Matt Arsenault
54c6bb533a Generalize DiagnosticInfoStackSize to support other limits
Backends may want to report errors on resources other than
stack size.

llvm-svn: 273177
2016-06-20 18:13:04 +00:00
Sanjay Patel
c7bc4ff700 [InstCombine] update to use FileCheck with autogenerated exact checking
llvm-svn: 273173
2016-06-20 17:56:13 +00:00
Matt Arsenault
92fdfd4d72 AMDGPU: Use correct method for determining instruction size
llvm-svn: 273172
2016-06-20 17:51:32 +00:00
Adrian McCarthy
24f3bbf929 Properly handle short file names on the command line in Windows [TAKE 2]
Trying to expand short names with a relative path doesn't work, so this
first gets the module name to get a full path (which can still have short
names).

llvm-svn: 273171
2016-06-20 17:51:27 +00:00
Sanjay Patel
df106547a0 [InstCombine] regenerate checks
llvm-svn: 273170
2016-06-20 17:48:48 +00:00
Rafael Espindola
5a790c1a6d Use shouldAssumeDSOLocal.
With this ARM fast isel knows that PIE variable are not preemptable.

llvm-svn: 273169
2016-06-20 17:45:33 +00:00
Tom Stellard
49873ba9d6 AMDGPU: Add support for R_AMDGPU_REL32 relocations
Reviewers: arsenm, kzhuravl, rafael

Subscribers: arsenm, llvm-commits, kzhuravl

Differential Revision: http://reviews.llvm.org/D21401

llvm-svn: 273168
2016-06-20 17:33:43 +00:00
Rafael Espindola
aecb7bb795 Simplify. NFC.
llvm-svn: 273167
2016-06-20 17:00:13 +00:00
Tom Stellard
0b8b2d60ae AMDGPU: Emit R_AMDGPU_ABS32_{HI,LO} for scratch buffer relocations
Reviewers: arsenm, rafael, kzhuravl

Subscribers: rafael, arsenm, llvm-commits, kzhuravl

Differential Revision: http://reviews.llvm.org/D21400

llvm-svn: 273166
2016-06-20 16:59:44 +00:00
Sam Parker
c8e74a623c [ARM] Enable isel of UMAAL
TargetLowering and DAGToDAG are used to combine ADDC, ADDE and UMLAL
dags into UMAAL. Selection is split into the two phases because it
is easier to match the two patterns at those different times.

Differential Revision: http://http://reviews.llvm.org/D21461

llvm-svn: 273165
2016-06-20 16:47:09 +00:00
Rafael Espindola
97ddc93fc6 Add a isPositionIndependent predicate.
Reduces a bit of code duplication and clarify where we are interested
just on position independence and no the location of the symbol.

llvm-svn: 273164
2016-06-20 16:43:17 +00:00
David Majnemer
2c4b3f46da Forgot to update callers of deleteDeadInstruction
llvm-svn: 273163
2016-06-20 16:07:38 +00:00
David Majnemer
ef67820e4c Reapply "[LoopIdiom] Don't remove dead operands manually"
This reverts commit r273160, reapplying r273132.
RecursivelyDeleteTriviallyDeadInstructions cannot be called on a
parentless Instruction.

llvm-svn: 273162
2016-06-20 16:03:25 +00:00
Aaron Ballman
afc47a144c Removing an unused switch statement that has only a default label. This happens to also eliminate an instance of switchception. NFC intended.
llvm-svn: 273161
2016-06-20 15:37:15 +00:00
Cong Liu
f1a6d0f004 Revert "[LoopIdiom] Don't remove dead operands manually"
This reverts commit r273132.
Breaks multiple test under /llvm/test:Transforms (e.g.
llvm/test:Transforms/LoopIdiom/basic.ll.test) under asan.

llvm-svn: 273160
2016-06-20 15:22:15 +00:00
Simon Pilgrim
0e0ff04b0f [X86][F16C] Added half <-> double conversion tests
llvm-svn: 273153
2016-06-20 12:51:55 +00:00
Patrik Hagglund
81a7b97fbf Fix formatting of r273144. NFC.
llvm-svn: 273149
2016-06-20 11:19:58 +00:00
Pankaj Gode
62398e4da8 [AARCH64] Add support for Broadcom Vulcan
Adding core tuning support for new Broadcom Vulcan core (ARMv8.1A).

Differential Revision: http://reviews.llvm.org/D21500

llvm-svn: 273148
2016-06-20 11:13:31 +00:00
Patrik Hagglund
b78892cc35 Avoid output indeterminism between GCC and Clang builds.
Remove dependency of the evalution order of function arguments, which
is unspecified.

Patch by David Stenberg.

llvm-svn: 273145
2016-06-20 10:19:04 +00:00
Patrik Hagglund
747f3e0b3e Avoid output indeterminism between GCC and Clang builds.
Remove dependency of the evalution order of function arguments, which
is unspecified.

The following test previously failed when built with GCC (but succeded
when built with Clang):

  ; RUN: opt -sroa -S < %s | FileCheck %s

  target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
  target triple = "x86_64-unknown-linux-gnu"

  %A = type {i16}

  @a = global %A* null
  @b = global i16 0

  ; CHECK-LABEL: @f1(
  ; CHECK: alloca %A
  ; CHECK-NEXT: extractvalue %A
  ; CHECK-NEXT: getelementptr inbounds %A

  define void @f1 (%A %a) {
    %1 = alloca %A
    store %A %a, %A* %1
    %2 = load i16, i16* @b
    %3 = icmp ne i16 %2, 0
    br i1 %3, label %bb1, label %bb2
  bb1:
    store %A* %1, %A** @a
    br label %bb2
  bb2:
    ret void
  }

Patch by David Stenberg.

Differential Revision: http://reviews.llvm.org/D21226

llvm-svn: 273144
2016-06-20 10:19:00 +00:00
Patrik Hagglund
346fc62815 Fix for PR27940
After a store has been eliminated, when making sure that the
instruction iterator points to a valid instruction, dbg intrinsics are
now ignored as a new instruction.

Patch by Henric Karlsson.

Reviewed by Daniel Berlin.

Differential Revision: http://reviews.llvm.org/D21076

llvm-svn: 273141
2016-06-20 09:10:10 +00:00
Rui Ueyama
a3f4dc8da4 [codeview] Add an extra check for TPI hash values.
This patch adds a function that corresponds to `fUDTAnon`
and use that to compute TPI hash values as the reference does.

llvm-svn: 273139
2016-06-20 07:31:29 +00:00
Igor Breger
8384cb8d2e [AVX512] [AVX512/AVX][Intrinsics] Fix Variable Bit Shift Right Arithmetic intrinsic lowering.
Differential Revision: http://reviews.llvm.org/D20897

llvm-svn: 273138
2016-06-20 07:05:43 +00:00
Craig Topper
4a4a79f3d3 [X86] Pass the SDLoc and Mask ArrayRef down from lowerVectorShuffle through all of the other routines instead of recreating them in the handlers for each type. NFC
llvm-svn: 273137
2016-06-20 04:00:55 +00:00
Craig Topper
748594977b [X86] Use existing ArrayRef variable instead of calling SVOp->getMask() repeatedly. Remove nearby else after return as well. NFC
llvm-svn: 273136
2016-06-20 04:00:53 +00:00
Craig Topper
76b030ed20 [X86] Avoid making a copy of a shuffle mask until we're sure we really need to. And just use a SmallVector to do the copy because its easy.
llvm-svn: 273135
2016-06-20 04:00:50 +00:00
Eli Friedman
e2586910ce Fix dynamically linked debug builds.
On the surface, this might not look like it does anything... but
actually it brings in the declaration "extern template class
AnalysisManager<Loop>;", which suppresses the instantiation of the
constructor, which avoids the funny interaction between "extern
template" and -fvisibility-inlines-hidden.

llvm-svn: 273133
2016-06-20 02:48:11 +00:00
David Majnemer
c005b782f1 [LoopIdiom] Don't remove dead operands manually
Removing dead instructions requires remembering which operands have
already been removed.  RecursivelyDeleteTriviallyDeadInstructions has
this logic, don't partially reimplement it in LoopIdiomRecognize.

This fixes PR28196.

llvm-svn: 273132
2016-06-20 02:33:29 +00:00
NAKAMURA Takumi
24b157d37a Reformat blank lines.
llvm-svn: 273131
2016-06-20 01:05:15 +00:00
NAKAMURA Takumi
f81f554f6c Trailing whitespace.
llvm-svn: 273130
2016-06-20 00:49:20 +00:00
NAKAMURA Takumi
01c29da292 Untabify.
llvm-svn: 273129
2016-06-20 00:37:41 +00:00
Sanjay Patel
7c33bb064f [InstSimplify] add tests for PR27689; regenerate checks
llvm-svn: 273128
2016-06-19 21:40:12 +00:00
David Majnemer
3302aab6a9 Address Eli's post-commit comments
Use an APInt to handle pointers of arbitrary width, let
accumulateConstantOffset handle overflow issues.

llvm-svn: 273126
2016-06-19 21:36:35 +00:00
Simon Pilgrim
a95787d855 [X86][AVX512] Added 512-bit BITREVERSE tests and enabled AVX512BW lowering support
llvm-svn: 273125
2016-06-19 20:59:19 +00:00
Simon Pilgrim
3ed1c10523 Strip trailing whitespace. NFCI.
llvm-svn: 273124
2016-06-19 20:22:43 +00:00
Simon Pilgrim
f2812a60c9 Fixed signed/unsigned warning.
llvm-svn: 273120
2016-06-19 18:20:44 +00:00
Simon Pilgrim
d2e5703e8b [X86][SSE] Allow target shuffle combining to match masks with SM_Sentinel values
We currently only allow exact matches of shuffle mask patterns during target shuffle combining.

This patch relaxes this to permit SM_SentinelUndef in the combined shuffle to always be accepted as well as allowing exact matching of the SM_SentinelZero value.

I've adjusted some tests that were requiring exact shuffle masks to now include undef values.

Differential Revision: http://reviews.llvm.org/D21495

llvm-svn: 273119
2016-06-19 18:03:52 +00:00
Sanjay Patel
a0a797b7f0 fix formatting, typo; NFC
llvm-svn: 273118
2016-06-19 17:20:27 +00:00
Craig Topper
612cf9108d [X86] Add an assert to ensure that a routine is only used with 128-bit vectors. Reduce SmallVector size accordingly.
llvm-svn: 273117
2016-06-19 15:37:39 +00:00
Craig Topper
383e926959 [X86] Make is128BitLaneRepeatedShuffleMask correct the indices of the second vector for the smaller mask. This removes some custom correction code and can potentially provide other benefits in the future.
llvm-svn: 273116
2016-06-19 15:37:37 +00:00
Craig Topper
dc1da823ac [X86] Remove a dead path through one of the shuffle lowering routines. It's only called on single input shuffles masks already. Add an assert instead to verify.
llvm-svn: 273115
2016-06-19 15:37:35 +00:00
Craig Topper
b0aa499cbe [X86] Pre-allocate a SmallVector instead of using push_back in a loop. NFC
llvm-svn: 273114
2016-06-19 15:37:33 +00:00
Craig Topper
47954f314e [X86] Use SmallVector::assign instead of resize to ensure we really start with a vector of all -1s. Otherwise we're trusting the caller to pass the right thing.
This should be no functional change with current code.

llvm-svn: 273113
2016-06-19 15:37:30 +00:00
Vassil Vassilev
d18bf91e79 Add the corresponding modulemap entry, following up r273066.
llvm-svn: 273112
2016-06-19 15:31:12 +00:00
Chris Dewhurst
6ae2372872 [SPARC] Additional condition required for DelaySlot fixing erratum in revision r273108.
llvm-svn: 273111
2016-06-19 12:56:42 +00:00
Chris Dewhurst
bd10255714 [SPARC[ Correcting out-of-date unit tests checked in as part of r273108
llvm-svn: 273110
2016-06-19 12:52:39 +00:00
Joerg Sonnenberger
398d6220ab Indent consistently.
llvm-svn: 273109
2016-06-19 12:37:52 +00:00
Chris Dewhurst
f418c98924 [SPARC] Fixes for hardware errata on LEON processor.
Passes to fix three hardware errata that appear on some LEON processor variants.

The instructions FSMULD, FMULS and FDIVS do not work as expected on some LEON processors. This change allows those instructions to be substituted for alternatives instruction sequences that are known to work.

These passes only run when selected individually, or as part of a processor defintion. They are not included in general SPARC processor compilations for non-LEON processors or for those LEON processors that do not have these hardware errata.

llvm-svn: 273108
2016-06-19 11:03:28 +00:00
David Majnemer
c70f2f44a4 [LoadCombine] Combine Loads formed from GEPS with negative indexes
Change the underlying offset and comparisons to use int64_t instead of
uint64_t.

Patch by River Riddle!

Differential Revision: http://reviews.llvm.org/D21499

llvm-svn: 273105
2016-06-19 06:14:56 +00:00