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Commit Graph

218902 Commits

Author SHA1 Message Date
Simon Pilgrim
94824eaca5 [InstCombine] Regenerate gep-custom-dl.ll test checks 2021-07-21 14:29:34 +01:00
Sebastian Neubauer
5f547ad156 [AMDGPU] Improve killed check for vgpr optimization
The killed flag is not always set. E.g. when a variable is used in a
loop, it is never marked as killed, although it is unused in following
basic blocks. Also, we try to deprecate kill flags and not use them.

Check if the register is live in the endif block. If not, consider it
killed in the then and else blocks.

The vgpr-liverange tests have two new tests with loops
(pre-committed, so the diff is visible).
I also needed to change the subtarget to gfx10.1, otherwise calls
are not working.

Differential Revision: https://reviews.llvm.org/D106291
2021-07-21 15:24:59 +02:00
Sebastian Neubauer
9894eb12d3 [AMDGPU] Precommit vgpr-liverange tests 2021-07-21 15:24:59 +02:00
Guillaume Chatelet
a29bc1a45f [llvm] Add enum iteration to Sequence
This patch allows iterating typed enum via the ADT/Sequence utility.

It also changes the original design to better separate concerns:
 - `StrongInt` only deals with safe `intmax_t` operations,
 - `SafeIntIterator` presents the iterator and reverse iterator
 interface but only deals with safe `StrongInt` internally.
 - `iota_range` only deals with `SafeIntIterator` internally.

 This design ensures that operations are always valid. In particular,
 "Out of bounds" assertions fire when:
  - the `value_type` is not representable as an `intmax_t`
  - iterator operations make internal computation underflow/overflow
  - the internal representation cannot be converted back to `value_type`

Differential Revision: https://reviews.llvm.org/D106279
2021-07-21 12:48:53 +00:00
Simon Pilgrim
912cf6c6cb [InstCombine] Add multiuse test for D106352 2021-07-21 13:48:15 +01:00
Roman Lebedev
aeb244cb4e [NFC][VectorCombine] Load widening: add a few more negative tests 2021-07-21 15:21:37 +03:00
Simon Pilgrim
33f952ff1c IFSStub.cpp - consistently use default case to silence 'not all control paths return' MSVC warnings. NFCI. 2021-07-21 11:59:34 +01:00
David Green
ddd62877c6 [LV] Make use of PatternMatchers in getReductionPatternCost. NFC
Pulled out of D106166, this modifies getReductionPatternCost to use
PatternMatchers, hopefully simplifying the code a little.
2021-07-21 11:34:30 +01:00
Jay Foad
fd3020376e [AMDGPU] NFC refactoring in isel for buffer access intrinsics
Rename getBufferOffsetForMMO to updateBufferMMO and pass in the MMO to
be updated, in preparation for the bug fix in D106284.

Call updateBufferMMO consistently for all buffer intrinsics, even the
ones that use setBufferOffsets to decompose a combined offset
expression.

Add a getIdxEn helper function.

Differential Revision: https://reviews.llvm.org/D106354
2021-07-21 11:12:49 +01:00
Rosie Sumpter
b11b07e0b8 [LoopFlatten][LoopInfo] Use Loop to identify latch compare instruction
Make getLatchCmpInst non-static and use it in LoopFlatten as a more
robust way of identifying the compare.

Differential Revision: https://reviews.llvm.org/D106256
2021-07-21 10:14:18 +01:00
Kerry McLaughlin
8625c5dcda [LV] Use lookThroughAnd with logical reductions
If a reduction Phi has a single user which `AND`s the Phi with a type mask,
`lookThroughAnd` will return the user of the Phi and the narrower type represented
by the mask. Currently this is only used for arithmetic reductions, whereas loops
containing logical reductions will create a reduction intrinsic using the widened
type, for example:

  for.body:
    %phi = phi i32 [ %and, %for.body ], [ 255, %entry ]
    %mask = and i32 %phi, 255
    %gep = getelementptr inbounds i8, i8* %ptr, i32 %iv
    %load = load i8, i8* %gep
    %ext = zext i8 %load to i32
    %and = and i32 %mask, %ext
    ...

^ this will generate an and reduction intrinsic such as the following:
    call i32 @llvm.vector.reduce.and.v8i32(<8 x i32>...)

The same example for an add instruction would create an intrinsic of type i8:
    call i8 @llvm.vector.reduce.add.v8i8(<8 x i8>...)

This patch changes AddReductionVar to call lookThroughAnd for other integer
reductions, allowing loops similar to the example above with reductions such
as and, or & xor to vectorize.

Reviewed By: david-arm, dmgreen

Differential Revision: https://reviews.llvm.org/D105632
2021-07-21 09:56:00 +01:00
Cullen Rhodes
23e61e0bd4 [AArch64][SME] Support .arch and .arch_extension assembler directives
Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D105566
2021-07-21 08:40:27 +00:00
Tim Northover
a5f7171155 ARM: don't return by popping PC if we have to adjust the stack afterwards.
In mandatory tail calling conventions we might have to deallocate stack
space used by our arguments before return. This happens after popping
CSRs, so the pop cannot be turned into the return itself in this case.

The else branch here was already a nop, so removing it as a tidy-up.
2021-07-21 09:35:14 +01:00
Tim Northover
bd9402142a AArch64: support 8 & 16-bit atomic operations in GlobalISel
We have SelectionDAG patterns for 8 & 16-bit atomic operations, but they
assume the value types will have been legalized to 32-bits. So this adds
the ability to widen them to both AArch64 & generic GISel
infrastructure.
2021-07-21 09:35:14 +01:00
Cullen Rhodes
f8b2068905 [AArch64][SME] Add mova instructions
This patch adds the mova instruction to insert/extract an SVE vector
register to/from a ZA tile vector.

The preferred MOV aliases are also implemented.

Depends on D105572.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06

Reviewed By: david-arm, CarolineConcatto

Differential Revision: https://reviews.llvm.org/D105574
2021-07-21 08:20:01 +00:00
Cullen Rhodes
db780333ba [AArch64][SME] Add ldr and str instructions
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06

Reviewed By: kmclaughlin

Differential Revision: https://reviews.llvm.org/D105573
2021-07-21 08:17:13 +00:00
Timm Bäder
e396e90533 [llvm][tools] Hide more unrelated LLVM tool options
Differential Revision: https://reviews.llvm.org/D106366
2021-07-21 09:14:04 +02:00
Lang Hames
864fe23f53 [ORC][ORC-RT] Revert MachO TLV patches while I investigate more bot failures.
This reverts commit d4abdefc998a1ee19d5edc79ec233774cbf64f6a ("[ORC-RT] Rename
macho_tlv.x86-64.s to macho_tlv.x86-64.S (uppercase suffix)", and
a7733e9556b5a6334c910f88bcd037e84e17e3fc ("Re-apply "[ORC][ORC-RT] Add initial
native-TLV support to MachOPlatform."), while I investigate failures on
ccache builders (e.g. https://lab.llvm.org/buildbot/#/builders/109/builds/18981)
2021-07-21 15:52:33 +10:00
Lang Hames
248727a066 Re-apply "[ORC][ORC-RT] Add initial native-TLV support to MachOPlatform."
Reapplies fe1fa43f16beac1506a2e73a9f7b3c81179744eb, which was reverted in
6d8c63946cc259c0af02584b7cc690dde11dea35, with fixes:

1. Remove .subsections_via_symbols directive from macho_tlv.x86-64.s (it's
not needed here anyway).

2. Return error from pthread_key_create to the MachOPlatform to silence unused
variable warning.
2021-07-21 15:11:22 +10:00
Tianqing Wang
5f5c9808cd [X86] Update MachineLoopInfo in CMOV conversion.
If a CMOV is in a loop and is converted to branches, CMOV conversion wouldn't
add newly created basic blocks to loop info. Since the candidates is collected
based on loops, instructions in these basic blocks will be ignored.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D104623
2021-07-21 10:53:46 +08:00
Ben Shi
6b99631a69 [RISCV][test] Add tests for mul optimization in the zba extension with SH*ADD
These tests will show the following optimization by future patches.

(mul x, 11) -> (SH1ADD (SH2ADD x, x), x)
(mul x, 19) -> (SH1ADD (SH3ADD x, x), x)
(mul x, 13) -> (SH2ADD (SH1ADD x, x), x)
(mul x, 21) -> (SH2ADD (SH2ADD x, x), x)
(mul x, 37) -> (SH2ADD (SH3ADD x, x), x)
(mul x, 25) -> (SH3ADD (SH1ADD x, x), x)
(mul x, 41) -> (SH3ADD (SH2ADD x, x), x)
(mul x, 73) -> (SH3ADD (SH3ADD x, x), x)

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106031
2021-07-21 10:16:56 +08:00
Vitaly Buka
9d59adc48f [NFC][hwasan] Remove "pragma GCC poison"
With ifdefs they make code less readable.
2021-07-20 19:10:05 -07:00
Vitaly Buka
91284a6419 [NFC][hwasan] Simplify expression 2021-07-20 19:10:05 -07:00
Alexander Yermolovich
7c0f448127 [DWP] Fix for Refactoring llvm-dwp in to a library
Fix build for https://reviews.llvm.org/D106198 when -DBUILD_SHARED_LIBS=ON. Test Plan:

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D106414
2021-07-20 18:17:24 -07:00
Jon Roelofs
5f81593d96 [MachineVerifier] Diagnose invalid INSERT_SUBREGs
Differential revision: https://reviews.llvm.org/D105953
2021-07-20 17:32:29 -07:00
LLVM GN Syncbot
2c7e558308 [gn build] Port 403e67d34d03 2021-07-21 00:19:59 +00:00
Alexander Yermolovich
ba558b5d3e [DWP] Refactoring llvm-dwp in to a library.
This is a step1, mechanical refactor, of moving the bulk of llvm-dwp functionality in to a library. This should allow other tools, like BOLT, to re-use some of the llvm-dwp functionality.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D106198
2021-07-20 17:19:26 -07:00
Jon Roelofs
22051ac0d6 [GlobalISel] Tail call memcpy/memmove/memset even in the presence of copies
Differentail revision: https://reviews.llvm.org/D105382
2021-07-20 17:04:33 -07:00
Jon Roelofs
98d4971f24 [GlobalISel] Mark memcpy/memmove/memset as thisreturn
https://clang.godbolt.org/z/9az64j8W6

rdar://77466123

Differential revision: https://reviews.llvm.org/D105370
2021-07-20 17:04:33 -07:00
Lang Hames
53129328a6 Revert "[ORC][ORC-RT] Add initial native-TLV support to MachOPlatform."
Reverts commit fe1fa43f16beac1506a2e73a9f7b3c81179744eb while I investigate
failures on Linux.
2021-07-21 09:22:55 +10:00
Lang Hames
ad6b1171f3 [ORC][ORC-RT] Add initial native-TLV support to MachOPlatform.
Adds code to LLVM (MachOPlatform) and the ORC runtime to support native MachO
thread local variables. Adding new TLVs to a JITDylib at runtime is supported.

On the LLVM side MachOPlatform is updated to:

1. Identify thread local variables in the LinkGraph and lower them to GOT
accesses to data in the __thread_data or __thread_bss sections.

2. Merge and report the address range of __thread_data and thread_bss sections
to the runtime.

On the ORC runtime a MachOTLVManager class introduced which records the address
range of thread data/bss sections, and creates thread-local instances from the
initial data on demand. An orc-runtime specific tlv_get_addr implementation is
included which saves all register state then calls the MachOTLVManager to get
the address of the requested variable for the current thread.
2021-07-21 09:10:10 +10:00
Lang Hames
b5215e41fc [JITLink][MachO] Detect MachO::S_THREAD_LOCAL_ZEROFILL sections as zero-fill.
This will be used in upcoming MachO native TLV support patches to LLVM and
the ORC runtime.
2021-07-21 09:10:10 +10:00
Lang Hames
255fc69d3a [JITLink] Add support for moving blocks and symbols between sections.
LinkGraph::transferBlock can be used to move a block and all associated symbols
from one section to another.

LinkGraph::mergeSections moves all blocks and sections from a source section to
a destination section.
2021-07-21 09:10:09 +10:00
Albion Fung
d88c540901 [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins
Implemented builtins for mtmsr, mfspr, mtspr on PowerPC;
the patch is intended for XL Compatibility.

Differential revision: https://reviews.llvm.org/D106130
2021-07-20 17:51:00 -05:00
Aditya Nandakumar
3b84dfd020 [NFC][AssemblyWriter] Allow AssemblyWriter::printBasicBlock() to print blocks that don't have parents.
Remove the assert in AssemblyWriter::printBasicBlock() and
in BasicBlock::isEntryBlock() that require blocks to have parents.
Instead, have BasicBlock::isEntryBlock() return false for unattached
blocks. This allows us to call these functions for blocks that are
not yet added to a module which is a useful debugging capability.

Committing for xiaoqing_wu

https://reviews.llvm.org/D106127k
2021-07-20 15:46:31 -07:00
Jon Roelofs
efa9e99cf1 [tests] Move new tests into the PowerPC folder
That way they get marked as UNSUPPORTED by LIT when the ppc backend has not
been built.
2021-07-20 15:37:56 -07:00
Jon Roelofs
ff40770cd1 [AArch64][GlobalISel] Legalize ctpop for v2s64, v2s32, v4s32, v4s16, v8s16
https://llvm.godbolt.org/z/nTTK6M5qe

Differential revision: https://reviews.llvm.org/D106388
2021-07-20 15:37:56 -07:00
Sanjay Patel
cc2611c224 [ConstantFolding] avoid crashing on a fake math library call
https://llvm.org/PR50960
2021-07-20 18:25:21 -04:00
LLVM GN Syncbot
a36faebe1f [gn build] Port 808bbc2c4702 2021-07-20 21:53:24 +00:00
Alex Lorenz
e6cc4def5d [clang][darwin] Add support for macOS -> Mac Catalyst
version remapping to the Darwin SDK Info

Differential Revision: https://reviews.llvm.org/D105958
2021-07-20 14:25:33 -07:00
Roman Lebedev
8dc35a0179 [NFC][VectorCombine] Add tests for widening of partial vector load 2021-07-21 00:24:47 +03:00
Eli Friedman
b6a5af5997 [AArch64] Add tests for 128-bit atomic loads with casp available.
We currently don't use casp; maybe we should?
2021-07-20 14:02:44 -07:00
Sami Tolvanen
515d9b0199 Revert "ThinLTO: Fix inline assembly references to static functions with CFI"
This reverts commit 700d07f8ce6f2879610fd6b6968b05c6f17bb915.

Reverting due to a ThinLTO+CFI breakage on -msvc targets.
2021-07-20 13:59:46 -07:00
LLVM GN Syncbot
e479de9d16 [gn build] Port 05a6d74c4845 2021-07-20 20:51:01 +00:00
Albion Fung
63ce4846c7 [PowerPC] Store, load, move from and to registers related builtins
This patch implements store, load, move from and to registers related
builtins, as well as the builtin for stfiw. The patch aims to provide
feature parady with xlC on AIX.

Differential revision: https://reviews.llvm.org/D105946
2021-07-20 15:46:14 -05:00
Sterling Augustine
c4088202b5 Consolidate string types into ptr and length representations.
After rGbbbc4f110e35ac709b943efaa1c4c99ec073da30, we can move
any string type that has convenient pointer and length fields
into the PtrAndLengthKind, reducing the amount of code.

Differential Revision: https://reviews.llvm.org/D106381
2021-07-20 13:29:57 -07:00
Jessica Paquette
16d5479ea5 [AArch64][GlobalISel] Select llvm.aarch64.neon.st2 intrinsics
Add manual selection code similar to the code in AArch64ISelDAGToDAG, and add
`createTuple` helpers similar to the code there as well.

This accounted for around 111 fallbacks while building clang for AArch64 with
GlobalISel.

This also should make it easy to add selection code for other store
intrinsics.

As a minor cleanup, this uses `createQTuple` in the other place where we use
REG_SEQUENCE.

Differential Revision: https://reviews.llvm.org/D106332
2021-07-20 13:23:46 -07:00
Eli Friedman
a773ea23aa [AArch64] Use the CMP_SWAP_128 variants added in 843c6140.
Accidentally forgot to flip the opcode... and I didn't notice because it
was working fine for the GlobalISel.
2021-07-20 13:23:27 -07:00
Fangrui Song
2174d3b961 [LTO] Add SelectionKind to IRSymtab and use it in ld.lld/LLVMgold
In PGO, a C++ external linkage function `foo` has a private counter
`__profc_foo` and a private `__profd_foo` in a `comdat nodeduplicate`.

A `__attribute__((weak))` function `foo` has a weak hidden counter `__profc_foo`
and a private `__profd_foo` in a `comdat nodeduplicate`.

In `ld.lld a.o b.o`, say a.o defines an external linkage `foo` and b.o
defines a weak `foo`. Currently we treat `comdat nodeduplicate` as `comdat any`,
ld.lld will incorrectly consider `b.o:__profc_foo` non-prevailing.  In the worst
case when `b.o:__profd_foo` is retained and `b.o:__profc_foo` isn't, there will
be dangling reference causing an `undefined hidden symbol` error.

Add SelectionKind to `Comdat` in IRSymtab and let linkers ignore nodeduplicate comdat.

Differential Revision: https://reviews.llvm.org/D106228
2021-07-20 13:22:00 -07:00
Fangrui Song
afd2d1339a [AArch64] Delete unused Opcode after D106039 2021-07-20 12:51:44 -07:00