Evan Cheng
94f3d276c6
Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
...
llvm-svn: 55590
2008-08-31 18:32:16 +00:00
Gabor Greif
7db742d8c2
fix a bunch of 80-col violations
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llvm-svn: 55588
2008-08-31 15:37:04 +00:00
Bill Wendling
297eb080b6
Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR
...
instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.
llvm-svn: 55582
2008-08-31 02:59:23 +00:00
Bill Wendling
8faa2f3ec4
Expand for ROTR with MVT::i64.
...
Dale, Could you please review this?
llvm-svn: 55581
2008-08-31 02:53:19 +00:00
Gabor Greif
8fa04b6eb0
fix some 80-col violations
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llvm-svn: 55565
2008-08-30 10:09:02 +00:00
Evan Cheng
c3c439a624
For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these.
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llvm-svn: 55562
2008-08-30 08:54:22 +00:00
Evan Cheng
4bc8c9652e
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).
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llvm-svn: 55558
2008-08-30 02:03:58 +00:00
Dale Johannesen
1cfbb25e75
Add ppc partial-word ATOMIC_CMP_SWAP.
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llvm-svn: 55554
2008-08-30 00:08:53 +00:00
Evan Cheng
c1c53221c5
Swap fp comparison operands and change predicate to allow load folding (safely this time).
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llvm-svn: 55553
2008-08-29 23:22:12 +00:00
Evan Cheng
a884330e08
Use static_cast instead of C style cast.
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llvm-svn: 55552
2008-08-29 23:21:31 +00:00
Evan Cheng
17382f9ffb
Backing out 55521. Not safe.
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llvm-svn: 55548
2008-08-29 22:13:21 +00:00
Dale Johannesen
bc977ce106
Add partial word version of ATOMIC_SWAP.
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llvm-svn: 55546
2008-08-29 18:29:46 +00:00
Owen Anderson
3aa3841da2
Add initial support for fast isel of instructions that have inputs pinned to physical registers.
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llvm-svn: 55545
2008-08-29 17:45:56 +00:00
Evan Cheng
3fb02ae0b6
TableGen'ing instruction encodings.
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llvm-svn: 55533
2008-08-29 07:42:03 +00:00
Evan Cheng
b38decd917
addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.
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llvm-svn: 55531
2008-08-29 07:40:52 +00:00
Evan Cheng
5150e3da45
MVN is addrmode1.
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llvm-svn: 55530
2008-08-29 07:36:24 +00:00
Evan Cheng
f90bc9a050
More refactoring.
...
llvm-svn: 55528
2008-08-29 06:41:12 +00:00
Evan Cheng
cdd06ba3f4
Swap fp comparison operands and change predicate to allow load folding.
...
llvm-svn: 55521
2008-08-28 23:48:31 +00:00
Evan Cheng
c50df85672
Refactor ARM instruction format definitions into a separate file. No functionality changes.
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llvm-svn: 55518
2008-08-28 23:39:26 +00:00
Dan Gohman
c7b8401b77
Add a target callback for FastISel.
...
llvm-svn: 55512
2008-08-28 23:21:34 +00:00
Gabor Greif
5ec5f19852
remove tabs, fix > 80 cols
...
llvm-svn: 55511
2008-08-28 23:19:51 +00:00
Gabor Greif
86c795a8ca
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
...
llvm-svn: 55504
2008-08-28 21:40:38 +00:00
Mon P Wang
7566974359
In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN
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llvm-svn: 55499
2008-08-28 21:04:05 +00:00
Rafael Espindola
1cd4fc3111
Use resize instead of reserve. Reserve doesn't change size().
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llvm-svn: 55486
2008-08-28 18:32:53 +00:00
Dale Johannesen
e9a1266213
Implement partial-word binary atomics on ppc.
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llvm-svn: 55478
2008-08-28 17:53:09 +00:00
Evan Cheng
419506a149
FsFLD0S{S|D} and V_SETALLONES are as cheap as moves.
...
llvm-svn: 55466
2008-08-28 07:52:25 +00:00
Dale Johannesen
490c016734
Split the ATOMIC NodeType's to include the size, e.g.
...
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.
This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad. This is the alternative.
llvm-svn: 55457
2008-08-28 02:44:49 +00:00
Bill Wendling
0b5b31a0be
Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the
...
SSE2 registers as well as the MMX registers.
llvm-svn: 55436
2008-08-27 21:32:04 +00:00
Dan Gohman
3976cccecd
Reinstate the x86-64 portion of r55190. When doing extloads into
...
64-bit registers from 16-bit and smaller memory locations, prefer
instructions that define the entire 64-bit register, to avoid
partial-register updates.
llvm-svn: 55422
2008-08-27 17:33:15 +00:00
Gabor Greif
4b86114f92
disallow direct access to SDValue::ResNo, provide a getter instead
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llvm-svn: 55394
2008-08-26 22:36:50 +00:00
Owen Anderson
fc7b8f3073
These assertions should be return false's instead, allowing the client to detect the failure.
...
llvm-svn: 55377
2008-08-26 18:50:40 +00:00
Owen Anderson
5fef19facf
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
...
was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
llvm-svn: 55375
2008-08-26 18:03:31 +00:00
Chris Lattner
c5c00890e5
If an xmm register is referenced explicitly in an inline asm, make sure to
...
assign it to a version of the xmm register with the regclass that matches its
type. This fixes PR2715, a bug handling some crazy xpcom case in mozilla.
llvm-svn: 55358
2008-08-26 06:19:02 +00:00
Evan Cheng
65d29b2553
This is done.
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llvm-svn: 55348
2008-08-26 01:13:44 +00:00
Dale Johannesen
f201a3aaf3
Implement 32 & 64 bit versions of PPC atomic
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binary primitives.
llvm-svn: 55343
2008-08-25 22:34:37 +00:00
Evan Cheng
19738e3956
80 col. violations.
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llvm-svn: 55341
2008-08-25 21:58:43 +00:00
Evan Cheng
569b489cf5
Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot.
...
llvm-svn: 55338
2008-08-25 21:27:18 +00:00
Dale Johannesen
fbb408de74
Remove PPC-specific lowering for atomics; the
...
generic stuff works fine.
Mark rewritten cmp-and-swap as not using CR1.
llvm-svn: 55336
2008-08-25 21:09:52 +00:00
Dale Johannesen
39bd83dbc0
It's important for the cmp-and-swap to balance
...
loads and stores but it's even more important for
it to store the right value.:(
llvm-svn: 55319
2008-08-25 18:53:26 +00:00
Bill Wendling
7f52506926
Nevermind. This broke the bootstrap (?!).
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llvm-svn: 55318
2008-08-25 18:32:39 +00:00
Bill Wendling
f86b246fdb
MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these
...
instructions on having SSE2.
llvm-svn: 55317
2008-08-25 18:20:52 +00:00
Evan Cheng
2b9f879a99
Fix asm printing of MOVSDto64mr and MOV64toSDrm.
...
llvm-svn: 55300
2008-08-25 04:11:42 +00:00
Bill Wendling
5728cf59fd
Temporarily reverting r55292. It's causing a bootstraping failure:
...
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc ... src/libiberty/make-temp-file.c -o make-temp-file.o
Assertion failed: (Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && "Wrong topological sorting"), function InitDAGTopologicalSorting, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp, line 508.
../../../../llvm-gcc.src/libiberty/hashtab.c:955: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
make[4]: *** [hashtab.o] Error 1
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [multi-do] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libiberty] Error 2
make: *** [all] Error 2
llvm-svn: 55295
2008-08-24 21:45:30 +00:00
Evan Cheng
a600778748
Move callseq_start above the call address load to allow load to be folded into the call node.
...
llvm-svn: 55292
2008-08-24 19:19:55 +00:00
Cedric Venet
6c99b53fda
Use additionnal include directory instead of ../ in #include.
...
Suggested by aKor.
llvm-svn: 55282
2008-08-24 12:30:46 +00:00
Chris Lattner
fe3155fc62
Switch the asmprinter (.ll) and all the stuff it requires over to
...
use raw_ostream instead of std::ostream. Among other goodness,
this speeds up llvm-dis of kc++ with a release build from 0.85s
to 0.49s (88% faster).
Other interesting changes:
1) This makes Value::print be non-virtual.
2) AP[S]Int and ConstantRange can no longer print to ostream directly,
use raw_ostream instead.
3) This fixes a bug in raw_os_ostream where it didn't flush itself
when destroyed.
4) This adds a new SDNode::print method, instead of only allowing "dump".
A lot of APIs have both std::ostream and raw_ostream versions, it would
be useful to go through and systematically anihilate the std::ostream
versions.
This passes dejagnu, but there may be minor fallout, plz let me know if
so and I'll fix it.
llvm-svn: 55263
2008-08-23 22:23:09 +00:00
Anton Korobeynikov
be3a5a5ce9
Provide a 64 bit variant of mmx.maskmovq intrinsic lowering.
...
Is there way to avoid explicit target check?
llvm-svn: 55238
2008-08-23 15:53:19 +00:00
Dan Gohman
a9d5f9b006
Move the point at which FastISel taps into the SelectionDAGISel
...
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
llvm-svn: 55219
2008-08-23 02:25:05 +00:00
Anton Korobeynikov
8e795209d3
Make option variables static, so they won't cause nameclash
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llvm-svn: 55203
2008-08-22 21:27:49 +00:00
Bill Wendling
60e176391d
Reverting r55190, r55191, and r55192. They broke the build with this error message:
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{standard input}:17:bad register name `%sil'
make[4]: *** [libgcc/./_addvsi3.o] Error 1
make[4]: *** Waiting for unfinished jobs....
{standard input}:23:bad register name `%dil'
{standard input}:28:bad register name `%dil'
make[4]: *** [libgcc/./_addvdi3.o] Error 1
{standard input}:18:bad register name `%sil'
make[4]: *** [libgcc/./_subvsi3.o] Error 1
llvm-svn: 55200
2008-08-22 20:51:05 +00:00