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961f3df27b
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3 Commits

Author SHA1 Message Date
Francis Visoiu Mistrih
961f3df27b [CodeGen] Print register names in lowercase in both MIR and debug output 
As part of the unification of the debug format and the MIR format,
always print registers as lowercase.

* Only debug printing is affected. It now follows MIR.

Differential Revision: https://reviews.llvm.org/D40417

llvm-svn: 319187
 2017-11-28 17:15:09 +00:00
Jonas Paulsson
4b6f06420e [SystemZ] Enable machine scheduler. 
The machine scheduler (before register allocation) is enabled by default for
SystemZ.

The SelectionDAG scheduling preference now becomes source order scheduling
(was regpressure).

Review: Ulrich Weigand
https://reviews.llvm.org/D37977

llvm-svn: 315063
 2017-10-06 13:59:28 +00:00
Nirav Dave
7ec57298c0 [SystemZ] Prevent Merging Bitcast with non-normal loads 
Fixes PR32505.

Reviewers: uweigand, jonpa

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31609

llvm-svn: 299552
 2017-04-05 15:42:48 +00:00