Evan Cheng
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952943f744
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Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
llvm-svn: 134590
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2011-07-07 03:55:05 +00:00 |
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Bruno Cardoso Lopes
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15b9096112
|
Since ARM's prefetch implementation predicted the presence of a instruction
cache prefetch and now that the info from "prefetch" to "ARMPreload" is present,
only add a testcase for PLI.
llvm-svn: 132978
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2011-06-14 05:11:46 +00:00 |
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Bruno Cardoso Lopes
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b6afc5168f
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Add one more argument to the prefetch intrinsic to indicate whether it's a data
or instruction cache access. Update the targets to match it and also teach
autoupgrade.
llvm-svn: 132976
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2011-06-14 04:58:37 +00:00 |
|
Bob Wilson
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56f64ab701
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Add -mcpu=cortex-a9-mp. It's cortex-a9 with MP extension. rdar://8648637.
llvm-svn: 129774
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2011-04-19 18:11:52 +00:00 |
|
Evan Cheng
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165e65f53a
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Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
llvm-svn: 118237
|
2010-11-04 05:19:35 +00:00 |
|
Evan Cheng
|
eab7251695
|
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
llvm-svn: 118160
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2010-11-03 06:34:55 +00:00 |
|
Evan Cheng
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b41703bc2f
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Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
llvm-svn: 118152
|
2010-11-03 05:14:24 +00:00 |
|