Jim Grosbach
9717a9c0d3
ARM push of a single register encodes as pre-indexed STR.
...
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
llvm-svn: 137318
2011-08-11 18:07:11 +00:00
Andrew Trick
eb6a7aad9e
Cleanup. Another thorough review by Nick!
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llvm-svn: 137317
2011-08-11 17:54:58 +00:00
Jim Grosbach
abaaf4513f
ARM pop of a single register encodes as post-indexed LDR.
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Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
llvm-svn: 137316
2011-08-11 17:35:48 +00:00
Justin Holewinski
08425ade9c
PTX: Add basic documentation to CodeGenerator.html
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llvm-svn: 137315
2011-08-11 17:34:16 +00:00
Nadav Rotem
2461d23062
Add a comment, per Bruno's CR.
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llvm-svn: 137313
2011-08-11 17:05:47 +00:00
Nadav Rotem
b738be4555
[AVX] When joining two XMM registers into a YMM register, make sure that the
...
lower XMM register gets in first. This will allow the SUBREG pattern to
elliminate the first vector insertion.
llvm-svn: 137310
2011-08-11 16:49:36 +00:00
Nadav Rotem
de1b485f3f
[AVX] If the data which is going to be saved is already in two XMM registers
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(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.
Before:
vinsertf128 $1, %xmm3, %ymm0, %ymm3
vinsertf128 $0, %xmm1, %ymm3, %ymm1
vmovaps %ymm1, 416(%rsp)
After:
vmovaps %xmm3, 416+16(%rsp)
vmovaps %xmm1, 416(%rsp)
llvm-svn: 137308
2011-08-11 16:41:21 +00:00
Chris Lattner
3ae8704c4f
add missing colon, thanks peter.
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llvm-svn: 137306
2011-08-11 16:15:10 +00:00
Chris Lattner
575057916a
fix PR10605 / rdar://9930964 by adding a pretty scary missed check.
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It's somewhat surprising anything works without this. Before we would
compile the testcase into:
test: # @test
movl $4, 8(%rdi)
movl 8(%rdi), %eax
orl %esi, %eax
cmpl $32, %edx
movl %eax, -4(%rsp) # 4-byte Spill
je .LBB0_2
now we produce:
test: # @test
movl 8(%rdi), %eax
movl $4, 8(%rdi)
orl %esi, %eax
cmpl $32, %edx
movl %eax, -4(%rsp) # 4-byte Spill
je .LBB0_2
llvm-svn: 137303
2011-08-11 06:26:54 +00:00
Bruno Cardoso Lopes
4106caa9af
Cleanup: Remove Int_ CVTSS2SI* forms
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llvm-svn: 137297
2011-08-11 02:52:36 +00:00
Bruno Cardoso Lopes
8674ddf55a
Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causing
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infinite recursive calls in legalize. Fix PR10562
llvm-svn: 137296
2011-08-11 02:49:44 +00:00
Bruno Cardoso Lopes
954ac403c7
Use the splat index to generate the desired shuffle. Otherwise we
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could only get undefs and the vector shuffle becomes an undef,
generating wrong code.
llvm-svn: 137295
2011-08-11 02:49:41 +00:00
Eli Friedman
17bd9e5d7c
Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2).
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Fixes PR9693.
llvm-svn: 137292
2011-08-11 01:48:05 +00:00
Chad Rosier
1ff3ae1c91
Typo.
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llvm-svn: 137286
2011-08-11 00:22:48 +00:00
Devang Patel
504551c7bf
Stay within 80 columns.
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llvm-svn: 137283
2011-08-10 23:58:09 +00:00
Jim Grosbach
5322f1ea74
ARM LDRT assembly parsing and encoding.
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llvm-svn: 137282
2011-08-10 23:43:54 +00:00
Jim Grosbach
9fd458fd63
Tidy up. 80 columns.
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llvm-svn: 137277
2011-08-10 23:23:47 +00:00
Andrew Trick
306e3d0508
Reapplying r136844.
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An algorithm for incrementally updating LoopInfo within a
LoopPassManager. The incremental update should be extremely cheap in
most cases and can be used in places where it's not feasible to
regenerate the entire loop forest.
- "Unloop" is a node in the loop tree whose last backedge has been removed.
- Perform reverse dataflow on the block inside Unloop to propagate the
nearest loop from the block's successors.
- For reducible CFG, each block in unloop is visited exactly
once. This is because unloop no longer has a backedge and blocks
within subloops don't change parents.
- Immediate subloops are summarized by the nearest loop reachable from
their exits or exits within nested subloops.
- At completion the unloop blocks each have a new parent loop, and
each immediate subloop has a new parent.
llvm-svn: 137276
2011-08-10 23:22:57 +00:00
Jim Grosbach
eb96dd6c99
ARM tests for LDRSHT assembly parsing and encoding.
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llvm-svn: 137274
2011-08-10 23:18:30 +00:00
Jim Grosbach
e2cc6866d1
ARM tests for LDRSH assembly parsing and encoding.
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llvm-svn: 137272
2011-08-10 23:12:25 +00:00
Jim Grosbach
f65a625648
ARM tests for LDRSBT assembly parsing and encoding.
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llvm-svn: 137271
2011-08-10 23:08:56 +00:00
Jim Grosbach
e22ad37645
ARM tests for LDRSB assembly parsing and encoding.
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llvm-svn: 137270
2011-08-10 23:06:44 +00:00
Jim Grosbach
f291232aa1
Add FIXME.
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llvm-svn: 137265
2011-08-10 22:56:43 +00:00
Andrew Trick
0a61db0237
Cleanup. Remove an extraneous GraphTraits specialization.
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llvm-svn: 137264
2011-08-10 22:55:39 +00:00
Jim Grosbach
5c5f1c8305
ARM tests for LDRHT assembly parsing and encoding.
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llvm-svn: 137263
2011-08-10 22:55:38 +00:00
NAKAMURA Takumi
5d316f7632
test/CodeGen/X86/opt-shuff-tstore.ll: Add explicit -mtriple=x86_64-linux.
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llvm-svn: 137262
2011-08-10 22:52:48 +00:00
Jim Grosbach
7c1596bf26
ARM tests for LDRH(register) assembly parsing and encoding.
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llvm-svn: 137261
2011-08-10 22:45:42 +00:00
Jim Grosbach
e0ccd6b34e
ARM LDRH(immediate) assembly parsing and encoding support.
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llvm-svn: 137260
2011-08-10 22:42:16 +00:00
Jim Grosbach
e0c10a6d0c
Add FIXME
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llvm-svn: 137258
2011-08-10 22:20:38 +00:00
Jim Grosbach
4ad2dc8bb2
ARM LDRD(register) assembly parsing and encoding.
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Add support for literal encoding of #-0 along the way.
llvm-svn: 137254
2011-08-10 21:56:18 +00:00
Devang Patel
1541972a13
Distinguish between two copies of one inlined variable. Take 2.
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llvm-svn: 137253
2011-08-10 21:50:54 +00:00
Devang Patel
393d6e1fd0
While extending definition range of a debug variable, consult lexical scopes also. There is no point extending debug variable out side its lexical block. This provides 6x compile time speedup in some cases.
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llvm-svn: 137250
2011-08-10 21:25:34 +00:00
Devang Patel
5a1dd582e2
Revert unintentional parts of previous check-in.
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llvm-svn: 137249
2011-08-10 21:16:49 +00:00
Devang Patel
de73daa98c
Start using LexicalScopes utility. No intetional functionality change.
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llvm-svn: 137246
2011-08-10 20:55:27 +00:00
Jim Grosbach
e19952cfbb
Fix typo. Not quite sure how that slipped in there.
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llvm-svn: 137245
2011-08-10 20:49:18 +00:00
Jim Grosbach
bbef0044c8
ARM LDRD(immediate) assembly parsing and encoding support.
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llvm-svn: 137244
2011-08-10 20:29:19 +00:00
Eli Friedman
5c21e417bb
Changes per Jeffrey's comments.
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llvm-svn: 137243
2011-08-10 20:17:43 +00:00
Nadav Rotem
1b3075c0ab
Fix the test. Add cpu target.
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llvm-svn: 137241
2011-08-10 19:49:19 +00:00
Nadav Rotem
4a8d78d24a
When performing a truncating store, it is sometimes possible to rearrange the
...
data in-register prior to saving to memory. When we reorder the data in memory
we prevent the need to save multiple scalars to memory, making a single regular
store.
llvm-svn: 137238
2011-08-10 19:30:14 +00:00
Devang Patel
4459f63998
Provide utility to extract and use lexical scoping information from machine instructions.
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llvm-svn: 137237
2011-08-10 19:04:06 +00:00
Owen Anderson
0fde7a84ee
Add initial support for decoding NEON instructions in Thumb2 mode.
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llvm-svn: 137236
2011-08-10 19:01:10 +00:00
David Greene
2c065bce0c
Make Record Name an Init
...
Use an Init (ultimately a StringInit) to represent the Record name.
This allows the name to be composed by standard TableGen operators.
This will enable us to get rid of the ugly #NAME# hack processing and
naturally replace it with operators. It also increases flexibility
and power of the TableGen language by allowing record identifiers to
be computed dynamically.
llvm-svn: 137232
2011-08-10 18:27:46 +00:00
David Greene
1b84fa8ef7
Add getAsUnquotedString
...
Add a method to return an Init as an unquoted string. This primarily
affects StringInit where we return the value without surrounding it
with quotes.
This is in preparation for removing the ugly #NAME# hack and replacing
it with standard TabelGen operators.
llvm-svn: 137231
2011-08-10 18:27:45 +00:00
Andrew Trick
c1871c7c97
Comments. Thanks for the spell check Nick!
...
Also, my apologies for spoiling the autocomplete on SimplifyInstructions.cpp. I couldn't think of a better filename.
llvm-svn: 137229
2011-08-10 18:07:05 +00:00
Bruno Cardoso Lopes
565ab1542a
The following X86 pattern is incorrect:
...
def : Pat<(X86Movss VR128:$src1,
(bc_v4i32 (v2i64 (load addr:$src2)))),
(MOVLPSrm VR128:$src1, addr:$src2)>;
This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner.
llvm-svn: 137227
2011-08-10 17:45:17 +00:00
Eli Friedman
fa9191bd9f
Whitespace.
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llvm-svn: 137226
2011-08-10 17:39:11 +00:00
Owen Anderson
59d627c17a
Tabs --> spaces.
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llvm-svn: 137225
2011-08-10 17:38:05 +00:00
Owen Anderson
0819cf208f
Cleanups based on Nick Lewycky's feedback.
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llvm-svn: 137224
2011-08-10 17:36:48 +00:00
Owen Anderson
0d68079e26
Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots.
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llvm-svn: 137223
2011-08-10 17:21:20 +00:00
Rafael Espindola
45cd7316b5
Add support for the R and Q constraints.
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llvm-svn: 137217
2011-08-10 16:26:42 +00:00