Chris Lattner
97ee5c7f18
Disable formation of rlwinm instructions from SRA bases. This fixes
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the 177.mesa failure from last night, and fixes the
CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll regression test I added.
If this code cannot be fixed, it should be removed for good, but I'll leave
it to Nate to decide its fate.
llvm-svn: 23670
2005-10-09 05:36:17 +00:00
Nate Begeman
ef7172f7b3
Remove another unused file. Preparing for the great "enable i64 on ppc32"
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merge, and using subtarget info for ptr size.
llvm-svn: 23668
2005-10-08 01:32:34 +00:00
Nate Begeman
77c1ff0239
Remove a file that is no longer used
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llvm-svn: 23666
2005-10-08 01:21:27 +00:00
Chris Lattner
6809d07aa5
When preselecting, favor things that have low depth to select first. This
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is faster and uses less stack space. This reduces our stack requirement
enough to compile sixtrack, and though it's a hack, should be enough until
we switch to iterative isel
llvm-svn: 23664
2005-10-07 22:10:27 +00:00
Chris Lattner
8481412db8
Fix a CQ regression from my patch to split F32/F64 into seperate register
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classes on PPC. We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced. This fixes Regression/CodeGen/PowerPC/fpcopy.ll
llvm-svn: 23654
2005-10-07 05:00:52 +00:00
Chris Lattner
9be9eb2f7f
Fix CodeGen/Generic/bool-to-double.ll
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llvm-svn: 23652
2005-10-07 04:50:48 +00:00
Chris Lattner
f572bec811
Pull out Call, reducing stack frame size from 6032 bytes to 5184 bytes.
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llvm-svn: 23650
2005-10-06 19:07:45 +00:00
Chris Lattner
0e0c65b680
Pull out setcc, this reduces stack frame size from 7520 to 6032 bytes
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llvm-svn: 23649
2005-10-06 19:03:35 +00:00
Chris Lattner
0e97719aa3
Pull two more methods out, reducing stack frame size from 8224 -> 7520 bytes
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llvm-svn: 23648
2005-10-06 18:56:10 +00:00
Chris Lattner
4b1b6161ef
Add a recursive-iterative hybrid stage to attempt to reduce stack space, this
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helps but not enough.
Start pulling cases out of PPC32DAGToDAGISel::Select. With GCC 4, this function
required 8512 bytes of stack space for each invocation (GCC 3 required less
than 700 bytes). Pulling this first function out gets us down to 8224. More
to come :(
llvm-svn: 23647
2005-10-06 18:45:51 +00:00
Andrew Lenharth
c9e3e3ee73
This is suppose to work now
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llvm-svn: 23644
2005-10-06 16:54:29 +00:00
Andrew Lenharth
a3b71accf4
remove VAX compatibility instruction, we will never use this
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llvm-svn: 23643
2005-10-06 16:53:32 +00:00
Chris Lattner
e4feaa3bea
silence some warnings
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llvm-svn: 23637
2005-10-05 17:15:09 +00:00
Chris Lattner
70ebb767b4
Add a forward def
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llvm-svn: 23621
2005-10-04 05:09:20 +00:00
Chris Lattner
26a791ec89
Speed up the asm printer a lot by not printing formatted LLVM asm output
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for globals
llvm-svn: 23608
2005-10-03 07:08:36 +00:00
Chris Lattner
462fe8b2cc
silence some warnings
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llvm-svn: 23594
2005-10-02 16:29:36 +00:00
Chris Lattner
51aeb8156a
silence a warning
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llvm-svn: 23593
2005-10-02 16:27:59 +00:00
Chris Lattner
d4313f30ea
add patterns for float binops and fma ops
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llvm-svn: 23592
2005-10-02 07:46:28 +00:00
Chris Lattner
efd92cf886
Sort the cpu and features table, so that the alpha backend doesn't fail EVERY
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compile with an assertion that the tables are not sorted!
llvm-svn: 23591
2005-10-02 07:13:52 +00:00
Chris Lattner
00a39b4fd5
another solution to the fsel issue. Instead of having 4 variants, just force
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the comparison to be 64-bits. This is fine because extensions from float
to double are free.
llvm-svn: 23589
2005-10-02 07:07:49 +00:00
Chris Lattner
efc0d24037
fsel can take a different FP type for the comparison and for the result. As such
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split the FSEL family into 4 things instead of just two.
llvm-svn: 23588
2005-10-02 06:58:23 +00:00
Chris Lattner
f1c1042780
fix an f32/f64 type mismatch
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llvm-svn: 23587
2005-10-02 06:37:13 +00:00
Chris Lattner
89c435541a
Adjust to change in ctor
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llvm-svn: 23585
2005-10-02 06:23:51 +00:00
Chris Lattner
b66cf00015
Minor tweak to the branch selector. When emitting a two-way branch, and if
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we're in a single-mbb loop, make sure to emit the backwards branch as the
conditional branch instead of the uncond branch. For example, emit this:
LBBl29_z__44:
stw r9, 0(r15)
stw r9, 4(r15)
stw r9, 8(r15)
stw r9, 12(r15)
addi r15, r15, 16
addi r8, r8, 1
cmpw cr0, r8, r28
ble cr0, LBBl29_z__44
b LBBl29_z__48 *** NOT PART OF LOOP
Instead of:
LBBl29_z__44:
stw r9, 0(r15)
stw r9, 4(r15)
stw r9, 8(r15)
stw r9, 12(r15)
addi r15, r15, 16
addi r8, r8, 1
cmpw cr0, r8, r28
bgt cr0, LBBl29_z__48 *** PART OF LOOP!
b LBBl29_z__44
The former sequence has one fewer dispatch group for the loop body.
llvm-svn: 23582
2005-10-01 23:06:26 +00:00
Chris Lattner
f26486ee16
like the comment says, enable this
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llvm-svn: 23581
2005-10-01 23:02:40 +00:00
Chris Lattner
2f63a0f7c6
fix typo
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llvm-svn: 23578
2005-10-01 02:51:36 +00:00
Chris Lattner
50411b1026
Modify the ppc backend to use two register classes for FP: F8RC and F4RC.
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These are used to represent float and double values, and the two regclasses
contain the same physical registers.
llvm-svn: 23577
2005-10-01 01:35:02 +00:00
Jim Laskey
94e6b5c648
Should be using flag and not chain.
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llvm-svn: 23572
2005-09-30 23:43:37 +00:00
Nate Begeman
62fa04cd5b
Remove some now-dead code.
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llvm-svn: 23571
2005-09-30 21:28:27 +00:00
Andrew Lenharth
901ca061fd
subtarget support for CIX and FIX extentions (the only 2 I care about right now)
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llvm-svn: 23569
2005-09-30 20:24:38 +00:00
Chris Lattner
c744d9398f
Rename MRegisterDesc -> TargetRegisterDesc for consistency
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llvm-svn: 23564
2005-09-30 17:49:27 +00:00
Chris Lattner
661384dce6
trim down the target info structs now that we have a preferred spill register class for each callee save register
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Why is V9 maintaining these tables manually? ugh!
llvm-svn: 23561
2005-09-30 17:38:36 +00:00
Chris Lattner
c3c139cc70
constant fold these calls
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llvm-svn: 23558
2005-09-30 17:16:59 +00:00
Chris Lattner
f70bf81bb6
simplify this code using the new regclass info passed in
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llvm-svn: 23557
2005-09-30 17:12:38 +00:00
Chris Lattner
8e4d17179d
stub out a virtual method
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llvm-svn: 23554
2005-09-30 06:55:18 +00:00
Chris Lattner
6a87f90d17
CR registers are not used by this "target"
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llvm-svn: 23552
2005-09-30 06:43:58 +00:00
Chris Lattner
49117a5dcc
these registers don't belong to any register classes, so don't mark them
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as callee save. They can never be generated by the compiler.
llvm-svn: 23551
2005-09-30 06:42:24 +00:00
Chris Lattner
60e0bcc04a
Now that self referential classes are supported, get rid of a work-around.
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llvm-svn: 23544
2005-09-30 04:13:23 +00:00
Chris Lattner
2aaaf81c9e
pass extra args
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llvm-svn: 23539
2005-09-30 01:31:52 +00:00
Chris Lattner
3c59b33016
these methods get extra args
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llvm-svn: 23538
2005-09-30 01:30:55 +00:00
Chris Lattner
a1266f8ed5
Pass extra regclasses into spilling code
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llvm-svn: 23537
2005-09-30 01:29:42 +00:00
Chris Lattner
2b22bc735c
Use the 32-bit version for now
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llvm-svn: 23534
2005-09-30 00:05:05 +00:00
Chris Lattner
06cf72a8e5
Add a bunch of patterns for F64 FP ops, add some more integer ops
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llvm-svn: 23533
2005-09-29 23:34:24 +00:00
Chris Lattner
47999915ad
Remove code for patterns that are autogenerated
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llvm-svn: 23532
2005-09-29 23:33:31 +00:00
Andrew Lenharth
070a2605dd
begining alpha subtarget support
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llvm-svn: 23531
2005-09-29 22:54:56 +00:00
Chris Lattner
e16fc704bd
tblgen autogens this pattern now
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llvm-svn: 23530
2005-09-29 22:37:24 +00:00
Andrew Lenharth
b5d08bba45
copy and paste error
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llvm-svn: 23528
2005-09-29 21:11:57 +00:00
Chris Lattner
7c8efa3b9b
now that tblgen is smarter, this pattern is not needed. Also, tblgen
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now inverts commuted versions of ANDC/ORC with the current .td file.
llvm-svn: 23527
2005-09-29 19:29:15 +00:00
Chris Lattner
cb42f7df68
consistency with other cases, no functionality change
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llvm-svn: 23524
2005-09-29 17:38:52 +00:00
Chris Lattner
cb09b023d3
Make the JIT default to the DAG isel instead of the pattern isel, like LLC.
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The Pattern isel has some strange memory corruption issues going on. :(
This should have been converted over anyway, but it got forgotten somehow
when switching to the dag isel.
llvm-svn: 23523
2005-09-29 17:31:03 +00:00