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9918652e43
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536 Commits

Author SHA1 Message Date
Daniel Sanders
9918652e43 [mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrinsics) 
llvm-svn: 193239
 2013-10-23 10:36:52 +00:00
Matheus Almeida
1760b2c642 [mips][msa] Fix definition of SLD instruction. 
The second parameter of the SLD intrinsic is the number of columns (GPR) to 
slide left the source array.

llvm-svn: 193076
 2013-10-21 11:47:56 +00:00
Daniel Sanders
794132ee1f [mips][msa] Added a regression test that depended on multiple patches to pass. 
llvm-svn: 192961
 2013-10-18 09:52:21 +00:00
Daniel Sanders
f588d8546a [mips][msa] Added lsa instruction 
llvm-svn: 192895
 2013-10-17 13:38:20 +00:00
Daniel Sanders
4adbd7d84f Fix r192888: test/CodeGen/Mips/msa/3r_ld_st.ll should have been deleted 
llvm-svn: 192889
 2013-10-17 12:36:35 +00:00
Daniel Sanders
21c7c7cd9b [mips][msa] Added support for build_vector for v4f32 and v2f64. 
llvm-svn: 192699
 2013-10-15 13:14:41 +00:00
Akira Hatanaka
29e44ea3aa [mips] Transfer kill flag to the newly created operand. 
llvm-svn: 192662
 2013-10-15 01:06:30 +00:00
Reed Kotler
9efb450361 For Mips16, start to consolidate all forms of 32 bit literal loading so that 
they can be better handled and optimized in the Mips16 constant island code.

llvm-svn: 192520
 2013-10-12 02:19:08 +00:00
Matheus Almeida
73759d3a3b [mips][msa] Improves robustness of the test by enhancing pattern matching. 
llvm-svn: 192446
 2013-10-11 13:18:01 +00:00
Daniel Sanders
3649e05b17 [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics) 
llvm-svn: 192438
 2013-10-11 10:50:42 +00:00
Daniel Sanders
9bec7b823b [mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not intrinsics) 
llvm-svn: 192435
 2013-10-11 10:27:32 +00:00
Daniel Sanders
253e018134 [mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not intrinsics) 
llvm-svn: 192430
 2013-10-11 10:14:25 +00:00
Daniel Sanders
4971ec128b [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics) 
llvm-svn: 192429
 2013-10-11 10:00:06 +00:00
Akira Hatanaka
d7e78a8926 [mips] Do not generate INS/EXT nodes if target does not have support for 
ins/ext.

llvm-svn: 192330
 2013-10-09 23:36:17 +00:00
Reed Kotler
0b1b97d48b Add fabsf to the list of inlined functions; otherwise 
Mips16 will try and create a stub for it and this will
result in a link error because that function does not exist in libc.

llvm-svn: 192223
 2013-10-08 19:55:01 +00:00
Reed Kotler
57455fdc7c Let rotr and bswap be handled by expansion for Mips16 since we don't 
have native instructions for this.

llvm-svn: 192207
 2013-10-08 17:32:33 +00:00
Akira Hatanaka
6c2bf15c93 [mips] Test case for r192124. 
llvm-svn: 192135
 2013-10-07 21:32:57 +00:00
Reed Kotler
33301878d0 Add Mips16 patterns for sign extend byte and sign extend halfword. 
llvm-svn: 192130
 2013-10-07 20:46:19 +00:00
Reed Kotler
13ebdc7d9c Support tblockaddr for static compilation in Mips16. 
llvm-svn: 191986
 2013-10-04 22:01:40 +00:00
Akira Hatanaka
e85ca33e98 [mips] Fix a bug in MipsLongBranch::replaceBranch, which was erasing 
instructions in delay slots along with the original branch instructions.

llvm-svn: 191978
 2013-10-04 20:51:40 +00:00
Daniel Sanders
6ffe6fc99c [mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics) 
llvm-svn: 191737
 2013-10-01 10:22:35 +00:00
Manman Ren
799fd39420 TBAA: remove !tbaa from testing cases when they are not needed. 
llvm-svn: 191689
 2013-09-30 18:17:35 +00:00
Akira Hatanaka
e5351a10fe [mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out 
of loops.

Previously, two consecutive calls to function "func" would result in the
following sequence of instructions:

1. load $16, %got(func)($gp) // load address of lazy-binding stub.
2. move $25, $16
3. jalr $25                  // jump to lazy-binding stub.
4. nop
5. move $25, $16
6. jalr $25                  // jump to lazy-binding stub again.

With this patch, the second call directly jumps to func's address, bypassing
the lazy-binding resolution routine:

1. load $25, %got(func)($gp) // load address of lazy-binding stub.
2. jalr $25                  // jump to lazy-binding stub.
3. nop
4. load $25, %got(func)($gp) // load resolved address of func.
5. jalr $25                  // directly jump to func.

llvm-svn: 191591
 2013-09-28 00:12:32 +00:00
Daniel Sanders
0987676281 [mips][msa] Implemented insert.d intrinsic. 
This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is
further lowered into a sequence of insert.w's on MIPS32.

llvm-svn: 191521
 2013-09-27 13:36:54 +00:00
Daniel Sanders
3c43957555 [mips][msa] Implemented fill.d intrinsic. 
This intrinsic is lowered into an equivalent BUILD_VECTOR which is further
lowered into a sequence of insert.w's on MIPS32.

llvm-svn: 191519
 2013-09-27 13:20:41 +00:00
Daniel Sanders
935673af60 [mips][msa] Implemented copy_[us].d intrinsic. 
This intrinsic is lowered into equivalent copy_s.w instructions during
legalization.

llvm-svn: 191518
 2013-09-27 13:04:21 +00:00
Daniel Sanders
8c83ddcdd2 [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64. 
For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is
later expanded to appropriate insve.[wd] insns.

llvm-svn: 191515
 2013-09-27 12:31:32 +00:00
Daniel Sanders
0bb1b5a37f [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 
For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may
be expanded to subregister copies and/or instructions as appropriate.

llvm-svn: 191514
 2013-09-27 12:17:32 +00:00
Daniel Sanders
0f009e6be5 [mips][msa] Added support for MSA registers to copyPhysReg 
llvm-svn: 191512
 2013-09-27 12:03:51 +00:00
Daniel Sanders
8e7e5fd076 [mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics) 
Updated some of the vshf since they (correctly) emit splati's now

llvm-svn: 191511
 2013-09-27 11:48:57 +00:00
Daniel Sanders
d13fea547a [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. 
llvm-svn: 191498
 2013-09-27 10:08:31 +00:00
Daniel Sanders
6a20248b3a [mips][msa] Expand all truncstores and loadexts for MSA as well as DSP 
llvm-svn: 191496
 2013-09-27 09:44:59 +00:00
Daniel Sanders
27836999cd [mips][msa] Added missing check in performSRACombine 
Reviewers: jacksprat, dsanders

Reviewed By: dsanders

Differential Revision: http://llvm-reviews.chandlerc.com/D1755

llvm-svn: 191495
 2013-09-27 09:25:29 +00:00
Reed Kotler
ea8c398b50 Fix a bad typo in the inline assembly code for mips16 pic fp stubs 
and make one cosmetic cleanup to make it look the same as gcc
in this area; adjusting test cases.

llvm-svn: 191400
 2013-09-25 20:58:50 +00:00
Daniel Sanders
d110591231 [mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. not intrinsics) 
llvm-svn: 191306
 2013-09-24 14:53:25 +00:00
Daniel Sanders
48059bf5ef [mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal IR (i.e. not intrinsics) 
llvm-svn: 191304
 2013-09-24 14:36:12 +00:00
Daniel Sanders
db41b542e8 [mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics) 
llvm-svn: 191302
 2013-09-24 14:20:00 +00:00
Daniel Sanders
7c64721346 [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics) 
llvm-svn: 191301
 2013-09-24 14:02:15 +00:00
Daniel Sanders
e154d03143 [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. 
Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover
bitcasted as well as normal vectors. However, it doesn't seem to be possible to
match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of
immediates, it should be possible to use ldi.b to load v2i64) using TableGen so
ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp

This made the majority of the constant splat BUILD_VECTOR lowering redundant.
The only transformation remaining for constant splats is when an (up-to) 32-bit
constant splat is possible but the value does not fit into a 10-bit signed
integer. In this case, the BUILD_VECTOR is transformed into a bitcasted
BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32
register (which is initialized using the usual lui/addui sequence).

There are no additional tests since this is a re-implementation of previous
functionality. The change is intended to make it easier to implement some of
the upcoming instruction selection patches since they can rely on existing
support for BUILD_VECTOR's in the DAGCombiner.

compare_float.ll changed slightly because a BITCAST is no longer
introduced during legalization.

llvm-svn: 191299
 2013-09-24 13:33:07 +00:00
Daniel Sanders
1c08f8b17d [mips][msa] Non-constant BUILD_VECTOR's should be expanded to INSERT_VECTOR_ELT instead of memory operations. 
The resulting code is the same length, but doesnt cause memory traffic or latency.

llvm-svn: 191297
 2013-09-24 13:16:15 +00:00
Daniel Sanders
d201758a30 [mips][msa] Added partial support for matching fmax_a from normal IR (i.e. not intrinsics) 
This covers the case where fmax_a can be used to implement ISD::FABS.

llvm-svn: 191296
 2013-09-24 13:02:08 +00:00
Daniel Sanders
fe71effbbd [mips][msa] Added support for matching andi, ori, nori, and xori from normal IR (i.e. not intrinsics) 
llvm-svn: 191293
 2013-09-24 12:32:47 +00:00
Daniel Sanders
f05ed8bd9a [mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics) 
llvm-svn: 191291
 2013-09-24 12:18:31 +00:00
Daniel Sanders
0167ec55f4 [mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics) 
This required correcting the definition of the bsel and bseli intrinsics.

llvm-svn: 191290
 2013-09-24 12:04:44 +00:00
Daniel Sanders
9a3de1f604 [mips][msa] Added support for matching comparisons from normal IR (i.e. not intrinsics) 
MIPS SelectionDAG changes:
* Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask.

llvm-svn: 191286
 2013-09-24 10:46:19 +00:00
Daniel Sanders
362149b5a7 [mips][msa] Added support for matching slli, srai, and srli from normal IR (i.e. not intrinsics) 
llvm-svn: 191285
 2013-09-24 10:28:18 +00:00
Reed Kotler
ed09a36fb5 Make nomips16 mask not repeat if it ends with a '.'. 
This mask is purely for debugging and testing.

llvm-svn: 191231
 2013-09-23 22:36:11 +00:00
Daniel Sanders
ced4e4005c [mips][msa] Added support for matching addvi, and subvi from normal IR (i.e. not intrinsics) 
llvm-svn: 191203
 2013-09-23 14:29:55 +00:00
Daniel Sanders
34cb8f3e4d [mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) 
Changes to MIPS SelectionDAG:
* Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single
  operation and implemented the DAG combines necessary to fold sign/zero
  extends into the extract.

llvm-svn: 191199
 2013-09-23 14:03:12 +00:00
Daniel Sanders
d1df1263eb [mips][msa] Added support for matching pcnt from normal IR (i.e. not intrinsics) 
llvm-svn: 191198
 2013-09-23 13:40:21 +00:00