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Author SHA1 Message Date
Jim Grosbach
0ba5ba4535 ARM pre-UAL NEG mnemonic for convenience when porting old code. 
llvm-svn: 146511
 2011-12-13 20:23:22 +00:00
Chad Rosier
8af97606a9 [fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular 
load and then move the result from a GPR to a FPR.

llvm-svn: 146502
 2011-12-13 19:22:14 +00:00
Akira Hatanaka
23f439aca1 Add test/MC/Mips/dg.exp. 
llvm-svn: 146472
 2011-12-13 04:12:49 +00:00
Akira Hatanaka
a9290d5ab9 Move direct object emitter test to directory test/MC/Mips. Rename it to 
elf-relsym.ll.

llvm-svn: 146470
 2011-12-13 03:50:34 +00:00
Akira Hatanaka
28140f744a Relocation against a symbol, instead of against section. We had some extreme 
test cases where there were a lot of relocations applied relative to a large
rodata section. Gas would create a symbol for each of these whereas we would
be relative to the beginning of the rodata section. This change mimics what
gas does.

Patch by Jack Carter.

llvm-svn: 146468
 2011-12-13 02:27:40 +00:00
Nick Lewycky
90a4c39a28 Don't rely on a particular version string for llvm. 
llvm-svn: 146456
 2011-12-13 00:34:14 +00:00
Tony Linthicum
da0dd81cf1 Temporarily disable Hexagon tests. They are failing on OS X 
llvm-svn: 146455
 2011-12-13 00:33:45 +00:00
Akira Hatanaka
46dd9e66a6 Test case for r146432 by Jack Carter. 
llvm-svn: 146433
 2011-12-12 22:41:39 +00:00
Bob Wilson
70f6f24d68 Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006> 
These modifiers simply select either the low or high D subregister of a Neon
Q register.  I've also removed the unimplemented 'p' modifier, which turns out
to be a bit different than the comment here suggests and as far as I can tell
was only intended for internal use in Apple's version of gcc.

llvm-svn: 146417
 2011-12-12 21:45:15 +00:00
Tony Linthicum
61adbf8dc5 Hexagon backend support 
llvm-svn: 146412
 2011-12-12 21:14:40 +00:00
Joerg Sonnenberger
5b25b4d437 Only replace fwrite with fputc, if the return value is unused. 
llvm-svn: 146411
 2011-12-12 20:18:31 +00:00
Jan Sjödin
b9e2da0d9a XOP instructions and encoding tests. 
llvm-svn: 146407
 2011-12-12 19:37:49 +00:00
Roman Divacky
a450b8b2c8 Add support for gnu_indirect_function. 
llvm-svn: 146377
 2011-12-12 17:34:04 +00:00
Chandler Carruth
2bedf185c9 Manually upgrade the test suite to specify the flag to cttz and ctlz. 
I followed three heuristics for deciding whether to set 'true' or
'false':

- Everything target independent got 'true' as that is the expected
  common output of the GCC builtins.
- If the target arch only has one way of implementing this operation,
  set the flag in the way that exercises the most of codegen. For most
  architectures this is also the likely path from a GCC builtin, with
  'true' being set. It will (eventually) require lowering away that
  difference, and then lowering to the architecture's operation.
- Otherwise, set the flag differently dependending on which target
  operation should be tested.

Let me know if anyone has any issue with this pattern or would like
specific tests of another form. This should allow the x86 codegen to
just iteratively improve as I teach the backend how to differentiate
between the two forms, and everything else should remain exactly the
same.

llvm-svn: 146370
 2011-12-12 11:59:10 +00:00
Chandler Carruth
36be5dd1e8 Add an explicit test of the auto-upgrade functionality for the new 
intrinsic syntax.

Now that this is explicitly covered, I plan to upgrade the existing test
suite to use an explicit immediate. Note that I plan to specify 'true'
in most places rather than the auto-upgraded value as that is the far
more common value to end up here as that is the value coming from GCC's
builtins. The only place I'm likely to put a 'false' in is when testing
x86 which actually has different instructions for the two variants.

llvm-svn: 146369
 2011-12-12 11:23:11 +00:00
Chandler Carruth
d733f059d0 Teach the verifier to reject all non-constant arguments to the second 
argument of the cttz and ctlz intrinsics.

llvm-svn: 146360
 2011-12-12 04:36:02 +00:00
Stepan Dyatkovskiy
bf1423bdcd Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11. 
llvm-svn: 146341
 2011-12-11 14:35:48 +00:00
Chandler Carruth
afb8199f38 Don't assume things about the exact details of the LLVM version number, 
such as what VCS information is attached.

llvm-svn: 146333
 2011-12-10 21:40:31 +00:00
Chad Rosier
fa74c25947 Revert associate SelectInsertValue test as well. 
llvm-svn: 146332
 2011-12-10 21:34:28 +00:00
Chad Rosier
d8a265c838 Revert r146322 to appease buildbots. Original commit message: 
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.

llvm-svn: 146328
 2011-12-10 19:55:03 +00:00
Stepan Dyatkovskiy
5b2b42e8c9 Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt. 
llvm-svn: 146322
 2011-12-10 08:42:24 +00:00
Hal Finkel
d591c94df7 Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it. 
llvm-svn: 146318
 2011-12-10 04:50:53 +00:00
Rafael Espindola
9b9d35cc05 Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas 
does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.

llvm-svn: 146311
 2011-12-10 02:28:43 +00:00
Eli Friedman
ca06c3a2bd Splats can contain undef's; make sure to handle them correctly. PR11526. 
llvm-svn: 146299
 2011-12-09 23:54:42 +00:00
Jim Grosbach
356ad6d232 ARM assembly aliases for BIC<-->AND (immediate). 
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.

rdar://10550057

llvm-svn: 146283
 2011-12-09 22:02:17 +00:00
Evan Cheng
77f0fb0296 Update test to something more sensible. 
llvm-svn: 146282
 2011-12-09 21:54:10 +00:00
Jim Grosbach
489e81da30 ARM assembly parsing and encoding for VLD2 with writeback. 
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.

llvm-svn: 146278
 2011-12-09 21:28:25 +00:00
Chad Rosier
7e0dc23863 [fast-isel] Add support for selecting insertvalue. 
rdar://10530851

llvm-svn: 146276
 2011-12-09 20:09:54 +00:00
Rafael Espindola
b5c511f7b7 Handle reloc_signed_4byte in here. Not doing so was a regression from my 
previous commit. It is strange that we see it in 32 bits. We already
have a fixme about it.

llvm-svn: 146273
 2011-12-09 19:57:29 +00:00
Kevin Enderby
63cf89d532 The second part of support for generating dwarf for assembly source files. This 
generates the dwarf Compile Unit DIE and a dwarf subprogram DIE for each
non-temporary label.

The next part will be to get the clang driver to enable this when assembling
a .s file.  rdar://9275556

llvm-svn: 146262
 2011-12-09 18:09:40 +00:00
Benjamin Kramer
06cd66b1d7 X86: Add patterns for the various rounding ops for SSE4.1 and AVX. 
llvm-svn: 146257
 2011-12-09 15:44:03 +00:00
Andrew Trick
4f0b3bb42b Add -unroll-runtime for unrolling loops with run-time trip counts. 
Patch by Brendon Cahoon!

This extends the existing LoopUnroll and LoopUnrollPass. Brendon
measured no regressions in the llvm test suite with -unroll-runtime
enabled. This implementation works by using the existing loop
unrolling code to unroll the loop by a power-of-two (default 8). It
generates an if-then-else sequence of code prior to the loop to
execute the extra iterations before entering the unrolled loop.

llvm-svn: 146245
 2011-12-09 06:19:40 +00:00
Evan Cheng
2c8bac6b4c Forgot setting -march. 
llvm-svn: 146244
 2011-12-09 06:15:00 +00:00
Rafael Espindola
82e22767cf Handle the case of the magical _GLOBAL_OFFSET_TABLE_ showing up in a 
symbol difference. This matches gas behavior and fixes PR11513.

We still don't handle _GLOBAL_OFFSET_TABLE_ in data sections.

llvm-svn: 146238
 2011-12-09 03:03:58 +00:00
Akira Hatanaka
ce89ae9f84 jalr should use t9 ($25) for indirect calls regardless of the relocation model 
specified.

llvm-svn: 146229
 2011-12-09 01:45:12 +00:00
Eli Friedman
8f3db3867c Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514. 
llvm-svn: 146219
 2011-12-09 01:16:26 +00:00
Nick Lewycky
d2c1661e9f Fix infinite loop in DSE when deleting a free in a reachable loop that's also 
trivially infinite.

llvm-svn: 146197
 2011-12-08 22:36:35 +00:00
Evan Cheng
ad8debd736 Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417 
llvm-svn: 146196
 2011-12-08 22:30:45 +00:00
Jim Grosbach
62873cae5f ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough. 
llvm-svn: 146194
 2011-12-08 22:19:04 +00:00
Jim Grosbach
a33fa8aa88 ARM VSHR implied destination operand form aliases. 
llvm-svn: 146192
 2011-12-08 22:06:06 +00:00
Evan Cheng
d8a73b8918 Add various missing AVX patterns which was causing crashes. Sadly, the generated 
code looks pretty bad compared to SSE.

rdar://10538793

llvm-svn: 146191
 2011-12-08 22:05:28 +00:00
Jim Grosbach
af9cc198cf Tidy up a bit. 
llvm-svn: 146190
 2011-12-08 22:04:40 +00:00
Jim Grosbach
78020c4642 ARM VSUB implied destination operand form aliases. 
llvm-svn: 146182
 2011-12-08 20:56:26 +00:00
Jim Grosbach
957be45ccf Tidy up a bit. 
llvm-svn: 146181
 2011-12-08 20:53:19 +00:00
Jim Grosbach
a33af36947 ARM VQADD implied destination operand form aliases. 
llvm-svn: 146179
 2011-12-08 20:49:43 +00:00
Jim Grosbach
405e213008 ARM a few more VMUL implied destination operand form aliases. 
llvm-svn: 146177
 2011-12-08 20:42:35 +00:00
Owen Anderson
d003a613e7 Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise. 
llvm-svn: 146171
 2011-12-08 19:32:14 +00:00
Evan Cheng
0e0e920975 Add test for r146163. 
llvm-svn: 146167
 2011-12-08 19:21:39 +00:00
Daniel Dunbar
c192ce505d Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics 
sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.

llvm-svn: 146157
 2011-12-08 17:32:18 +00:00
NAKAMURA Takumi
671c1da473 test/CodeGen/X86/vec_compare-2.ll: Add explicit -mtriple=i686-linux. 
llvm-svn: 146152
 2011-12-08 15:24:09 +00:00
Nadav Rotem
341b30a457 Fix a bug in the integer-promotion of bitcast operations on vector types. 
We must not issue a bitcast operation for integer-promotion of vector types, because the
location of the values in the vector may be different.

llvm-svn: 146150
 2011-12-08 13:10:01 +00:00
Stepan Dyatkovskiy
8fde5b6eb4 Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). 
llvm-svn: 146143
 2011-12-08 07:55:03 +00:00
Jim Grosbach
e1fe053f6e ARM NEON two-operand aliases for VSHL(immediate). 
llvm-svn: 146125
 2011-12-08 01:30:04 +00:00
Jim Grosbach
3e9384b103 ARM NEON two-operand aliases for VSHL(register). 
llvm-svn: 146123
 2011-12-08 01:12:35 +00:00
Jim Grosbach
3b4d5c0510 ARM optional destination operand variants for VEXT instructions. 
llvm-svn: 146114
 2011-12-08 00:43:47 +00:00
Jim Grosbach
0c64182f7c Tidy up. 
llvm-svn: 146113
 2011-12-08 00:41:54 +00:00
Jim Grosbach
c1cf417595 ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm". 
llvm-svn: 146111
 2011-12-08 00:31:07 +00:00
Jim Grosbach
6146f79b7d ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands. 
For 'gas' compatibility.

llvm-svn: 146106
 2011-12-07 23:40:58 +00:00
Akira Hatanaka
7db0038ac0 32 to 64-bit zext pattern. 
llvm-svn: 146096
 2011-12-07 23:14:41 +00:00
Jim Grosbach
dd3788b044 ARM two-operand aliases for VAND/VEOR/VORR instructions. 
llvm-svn: 146095
 2011-12-07 23:08:12 +00:00
Jim Grosbach
da0a3e310a ARM two-operand aliases for VADDW instructions. 
llvm-svn: 146093
 2011-12-07 23:01:10 +00:00
Jim Grosbach
ecf9c2bb21 ARM two-operand aliases for VADD instructions. 
llvm-svn: 146091
 2011-12-07 22:52:54 +00:00
Akira Hatanaka
b8e63b4c07 64-bit WrapperPICPat patterns. 
llvm-svn: 146086
 2011-12-07 22:11:43 +00:00
Akira Hatanaka
2b45547782 Modify LowerFCOPYSIGN to handle Mips64. 
llvm-svn: 146080
 2011-12-07 21:48:50 +00:00
Akira Hatanaka
19d6cd4d0e Fix 64-bit immediate patterns. 
llvm-svn: 146059
 2011-12-07 20:10:24 +00:00
Jim Grosbach
2f57374e32 Darwin assembler improved relocs when w/o subsections_via_symbols. 
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.

llvm-svn: 146054
 2011-12-07 19:46:59 +00:00
Jim Grosbach
1ccae84fa7 Thumb2 alias for long-form pop and friends. 
rdar://10542474

llvm-svn: 146046
 2011-12-07 18:32:28 +00:00
Jim Grosbach
81cb9952c9 ARM support the .arm and .thumb directives for assembly mode switching. 
llvm-svn: 146042
 2011-12-07 18:04:19 +00:00
Jim Grosbach
3352ab97ca ARM NEON VCLT(register) is a pseudo aliasing VCGT(register). 
llvm-svn: 146039
 2011-12-07 17:51:15 +00:00
Jim Grosbach
61d2b8b2f9 Tidy up. Move MachO tests to MachO directory. 
llvm-svn: 146038
 2011-12-07 17:50:28 +00:00
Eli Friedman
9e8d557cd1 Support vector bitcasts in the AsmPrinter. PR11495. 
llvm-svn: 146001
 2011-12-07 00:50:54 +00:00
Eli Friedman
5545db0906 Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves correctly. PR11494. 
llvm-svn: 145996
 2011-12-07 00:11:56 +00:00
Hal Finkel
a76ada827b delaying restore-cr changed assigned registers in some tests 
llvm-svn: 145963
 2011-12-06 20:55:46 +00:00
Hal Finkel
7d78f1a8a4 add a test case that uses RESTORE_CR 
llvm-svn: 145962
 2011-12-06 20:55:41 +00:00
Justin Holewinski
c9457b712c PTX: Continue to fix up the register mess. 
llvm-svn: 145947
 2011-12-06 17:39:48 +00:00
Craig Topper
8b05e7d035 Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those. 
llvm-svn: 145927
 2011-12-06 09:04:59 +00:00
NAKAMURA Takumi
ed2be25205 test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it. 
FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)
llvm-svn: 145925
 2011-12-06 06:48:26 +00:00
Jim Grosbach
5b4f7d74de ARM mode 'mul' operand ordering tweak. 
Same as r145922, just for ARM mode.

llvm-svn: 145923
 2011-12-06 05:28:00 +00:00
Jim Grosbach
dc7d42f559 Thumb2: MUL two-operand form encoding operand order fix. 
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

llvm-svn: 145922
 2011-12-06 05:03:45 +00:00
Craig Topper
72b41227d8 Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted. 
llvm-svn: 145921
 2011-12-06 04:59:07 +00:00
Jim Grosbach
8bdbe92631 Thumb2 encoding choice correction for PLD. 
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

llvm-svn: 145919
 2011-12-06 04:49:29 +00:00
NAKAMURA Takumi
ea8cc0e506 test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM. 
MC/MachO assumes x86.

llvm-svn: 145916
 2011-12-06 03:56:05 +00:00
Andrew Trick
04c98888bc LSR: prune undesirable formulae early. 
It's always good to prune early, but formulae that are unsatisfactory
in their own right need to be removed before running any other pruning
heuristics. We easily avoid generating such formulae, but we need them
as an intermediate basis for forming other good formulae.

llvm-svn: 145906
 2011-12-06 03:13:31 +00:00
Chad Rosier
70dd1f98af [arm-fast-isel] Doublewords only require word-alignment. 
rdar://10528060

llvm-svn: 145891
 2011-12-06 01:44:17 +00:00
Jakob Stoklund Olesen
af85f53dd0 Align ARM constant pool islands via their basic block. 
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter.  Now the same alignment
is set on the basic block.

This is in preparation of supporting ARM constant pool islands with
different alignments.

llvm-svn: 145890
 2011-12-06 01:43:02 +00:00
Jim Grosbach
0fd3f58ea2 Fix ARM handling of tBcc branch relaxation. 
rdar://10069056

llvm-svn: 145885
 2011-12-06 01:08:19 +00:00
Chad Rosier
7096fea51c Probably not a good idea to convert a single vector load into a memcpy. We 
don't do this now, but add a test case to prevent this from happening in the
future.
Additional test for rdar://9892684

llvm-svn: 145879
 2011-12-06 00:19:08 +00:00
Chad Rosier
c50cbc5a65 Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio 
where this would be bad as the backend shouldn't have a problem inlining small
memcpys.
rdar://10510150

llvm-svn: 145865
 2011-12-05 22:37:00 +00:00
Jim Grosbach
74bbb6454e Tweak ADDrr fix. Bad check for explicit .w 
llvm-svn: 145863
 2011-12-05 22:27:04 +00:00
Jim Grosbach
6584358d09 Update tests for r145860. Add a few new ones. 
llvm-svn: 145861
 2011-12-05 22:21:28 +00:00
Akira Hatanaka
bdefd49aa5 Add definitions of 64-bit extract and insert instrucions and make 
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.

llvm-svn: 145853
 2011-12-05 21:26:34 +00:00
Jim Grosbach
655b017748 Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. 
rdar://10529348

llvm-svn: 145851
 2011-12-05 21:06:26 +00:00
Akira Hatanaka
b119dd5891 Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and 
O32 with relocation-model=pic too.

llvm-svn: 145850
 2011-12-05 21:03:03 +00:00
Jim Grosbach
9c017fb254 ARM assembly parsing for the rest of the VMUL data type aliases. 
Finish up rdar://10522016.

llvm-svn: 145846
 2011-12-05 20:29:59 +00:00
Hal Finkel
c8d6ce5e09 Add test case - this input used to crash because of duplicate generation of SPILL_CRs 
llvm-svn: 145820
 2011-12-05 17:55:22 +00:00
Hal Finkel
8b1e460cd9 enable PPC register scavenging by default (update tests and remove some FIXMEs) 
llvm-svn: 145819
 2011-12-05 17:55:17 +00:00
Hal Finkel
68e102ed41 remove wasted space for extra bit copies of CR2 subregs 
llvm-svn: 145817
 2011-12-05 17:55:06 +00:00
NAKAMURA Takumi
c6a187dfdd test/CodeGen/X86/pointer-vector.ll: Add explicit -mtriple=i686-linux. 
llvm-svn: 145805
 2011-12-05 07:54:57 +00:00
Nadav Rotem
1a91e4381d Add support for vectors of pointers. 
llvm-svn: 145801
 2011-12-05 06:29:09 +00:00
Anton Korobeynikov
e2277de6a7 Emit the ctors in the proper order on ARM/EABI. 
Maybe some targets should use this as well.

Patch by Evgeniy Stepanov!

llvm-svn: 145781
 2011-12-03 23:49:37 +00:00