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15260 Commits

Author SHA1 Message Date
Joerg Sonnenberger
8cf8d64d19 Allow inlining of functions with returns_twice calls, if they have the 
attribute themselve.

llvm-svn: 146851
 2011-12-18 20:35:43 +00:00
Chad Rosier
b870a13cd8 Revert 146728 as it's causing failures on some of the external bots as well as 
internal nightly testers.  Original commit message:

By popular demand, link up types by name if they are isomorphic and one is an
autorenamed version of the other.   This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large
app.

llvm-svn: 146838
 2011-12-17 22:19:53 +00:00
Kevin Enderby
42fffe915a Revert r146822 at Pete Cooper's request as it broke clang self hosting. 
Hope I did this correctly :)

llvm-svn: 146834
 2011-12-17 19:48:52 +00:00
Pete Cooper
0ec73f6e98 SimplifyCFG now predicts some conditional branches to true or false depending on previous branch on same comparison operands. 
For example, 

if (a == b) {
    if (a > b) // this is false
    
Fixes some of the issues on <rdar://problem/10554090>

llvm-svn: 146822
 2011-12-17 06:32:38 +00:00
Manuel Klimek
09f4d148b8 Deleting the json-bench-test until I understand why it is flaky. 
llvm-svn: 146821
 2011-12-17 06:29:32 +00:00
Evan Cheng
23574ec02a Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle. 
llvm-svn: 146805
 2011-12-17 01:25:34 +00:00
Rafael Espindola
549d0683b1 Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the 
asm parsing and testcase.

llvm-svn: 146801
 2011-12-17 01:14:52 +00:00
Lang Hames
e32ef23ba8 Make sure that the lower bits on the VSELECT condition are properly set. 
llvm-svn: 146800
 2011-12-17 01:08:46 +00:00
Dan Gohman
9c8c9a8f62 The powers that be have decided that LLVM IR should now support 16-bit 
"half precision" floating-point with a first-class type.

This patch adds basic IR support (but not codegen support).

llvm-svn: 146786
 2011-12-17 00:04:22 +00:00
Eric Christopher
38b0b94ef2 When recursing for the original size of a type, stop if we are at a 
pointer or a reference type - we actually just want the size of the
pointer then for that.

Fixes rdar://10335756

llvm-svn: 146785
 2011-12-16 23:42:45 +00:00
Jakob Stoklund Olesen
445cdbb987 Fix off-by-one error in bucket sort. 
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.

<rdar://problem/10594653>

llvm-svn: 146767
 2011-12-16 23:00:05 +00:00
Benjamin Kramer
04d6a4c456 Hexagon: Fix a nasty order-of-initialization bug. 
Reenable the tests.

llvm-svn: 146750
 2011-12-16 19:08:59 +00:00
Manuel Klimek
2f7cf4e64b Adds a JSON parser and a benchmark (json-bench) to catch performance regressions. 
llvm-svn: 146735
 2011-12-16 13:09:10 +00:00
Chris Lattner
26f06c927f By popular demand, link up types by name if they are isomorphic and one is an 
autorenamed version of the other.   This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large app.

llvm-svn: 146728
 2011-12-16 08:36:07 +00:00
Craig Topper
88e2bfef0a Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes. 
llvm-svn: 146726
 2011-12-16 08:06:31 +00:00
Kostya Serebryany
c78b00cab4 [asan] add a test for instrumenting globals 
llvm-svn: 146718
 2011-12-16 01:28:19 +00:00
Eli Friedman
f626b19bda Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586. 
llvm-svn: 146709
 2011-12-15 23:46:18 +00:00
Jim Grosbach
30f4b285a6 ARM NEON VCLE is an alias for VCGE w/ the source operands reversed. 
llvm-svn: 146699
 2011-12-15 22:56:33 +00:00
Jim Grosbach
b79d2a8f50 ARM NEON VTBL/VTBX assembly parsing and encoding. 
llvm-svn: 146691
 2011-12-15 22:27:11 +00:00
Chad Rosier
62ebee9859 Add missing zmovl AVX patterns which were causing crashes. 
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146689
 2011-12-15 22:11:31 +00:00
Chad Rosier
e74b3b1469 Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX. 
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146684
 2011-12-15 21:34:44 +00:00
Lang Hames
d5cee672a7 Set specific target cpu for testcase. 
llvm-svn: 146678
 2011-12-15 20:22:34 +00:00
Lang Hames
0e361e816d Added test case for r146671. 
llvm-svn: 146675
 2011-12-15 19:56:07 +00:00
Hal Finkel
e8220d9927 Add a test case to make sure that the nop really does follow the bl on ppc64 elf 
llvm-svn: 146666
 2011-12-15 17:59:23 +00:00
Eli Friedman
09abc453ac Fix test. 
llvm-svn: 146642
 2011-12-15 04:52:47 +00:00
Eli Friedman
f6ae3a7caf Make constant folding for GEPs a bit more aggressive. 
llvm-svn: 146639
 2011-12-15 04:33:48 +00:00
Eli Friedman
71c0914b64 Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570. 
llvm-svn: 146630
 2011-12-15 02:07:20 +00:00
Chad Rosier
b93733686c Add support for lowering fneg when AVX is enabled. 
rdar://10566486

llvm-svn: 146625
 2011-12-15 01:02:25 +00:00
Pete Cooper
550b96ab46 Added InstCombine for "select cond, ~cond, x" type patterns 
These can be reduced to "~cond & x" or "~cond | x"

llvm-svn: 146624
 2011-12-15 00:56:45 +00:00
Eli Friedman
5dd57bb40a Make loop preheader insertion in LoopSimplify handle the case where the loop header is a landing pad correctly (by splitting the landingpad out of the loop header). Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads. PR11575. 
llvm-svn: 146621
 2011-12-15 00:50:34 +00:00
Dan Gohman
1add31cc93 Move Instruction::isSafeToSpeculativelyExecute out of VMCore and 
into Analysis as a standalone function, since there's no need for
it to be in VMCore. Also, update it to use isKnownNonZero and
other goodies available in Analysis, making it more precise,
enabling more aggressive optimization.

llvm-svn: 146610
 2011-12-14 23:49:11 +00:00
Jim Grosbach
75db252aee ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. 
llvm-svn: 146605
 2011-12-14 23:25:46 +00:00
Devang Patel
0db1ed1a48 Do not sink instruction, if it is not profitable. 
On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator.

Radar 10266272.

llvm-svn: 146604
 2011-12-14 23:20:38 +00:00
Kevin Enderby
bc6d6388c2 Improve the implementation of .incbin directive by replacing a loop by using 
getStreamer().EmitBytes.  Suggestion by Benjamin Kramer!

llvm-svn: 146599
 2011-12-14 22:34:45 +00:00
Andrew Trick
9c88f32f94 LSR: Fold redundant bitcasts on-the-fly. 
llvm-svn: 146597
 2011-12-14 22:07:19 +00:00
Jim Grosbach
83520a5b70 ARM NEON fix alignment encoding for VST2 w/ writeback. 
Add tests for w/ writeback instruction parsing and encoding.

llvm-svn: 146594
 2011-12-14 21:49:24 +00:00
Kevin Enderby
b0b669eb26 Add the .incbin directive which takes the binary data from a file and emits 
it to the streamer.  rdar://10383898

llvm-svn: 146592
 2011-12-14 21:47:48 +00:00
Jim Grosbach
44829ab9d2 ARM NEON VST2 assembly parsing and encoding. 
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

llvm-svn: 146579
 2011-12-14 19:35:22 +00:00
Stepan Dyatkovskiy
14cb78c6fb Fix for bug #11429: Wrong behaviour for switches. Small improvement for code size heuristics. 
llvm-svn: 146578
 2011-12-14 19:19:17 +00:00
Dan Gohman
e9572aa680 It turns out that clang does use pointer-to-function types to 
point to ARC-managed pointers sometimes. This fixes rdar://10551239.

llvm-svn: 146577
 2011-12-14 19:10:53 +00:00
Akira Hatanaka
3fca32d88e Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object 
emission is not supported yet, but a patch that adds the support should follow
soon.

llvm-svn: 146572
 2011-12-14 18:26:41 +00:00
Jim Grosbach
54372eef76 ARM/Thumb2 'cmp rn, #imm' alias to cmn. 
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.

rdar://10552389

llvm-svn: 146567
 2011-12-14 17:30:24 +00:00
Jim Grosbach
628ae663ef ARM assembler support for the target-specific .req directive. 
rdar://10549683

llvm-svn: 146543
 2011-12-14 02:16:11 +00:00
Evan Cheng
68ba5536f3 - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function 
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
  and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
  prevent IT blocks from being broken apart.

llvm-svn: 146542
 2011-12-14 02:11:42 +00:00
Chad Rosier
33f40b2c25 Add newline at EOF. 
llvm-svn: 146538
 2011-12-14 01:34:39 +00:00
Jim Grosbach
089ad574d8 Thumb2 assembler aliases for "mov(shifted register)" 
rdar://10549767

llvm-svn: 146520
 2011-12-13 22:45:11 +00:00
Jim Grosbach
bd33fc6efd ARM LDM/STM system instruction variants. 
rdar://10550269

llvm-svn: 146519
 2011-12-13 21:48:29 +00:00
Jim Grosbach
7db50010cc Test for 146516 
llvm-svn: 146517
 2011-12-13 21:06:59 +00:00
Jim Grosbach
13d3509445 ARM thumb2 parsing of "rsb rd, rn, #0". 
rdar://10549741

llvm-svn: 146515
 2011-12-13 20:50:38 +00:00
Jim Grosbach
dfec87fe2f ARM NEON two-operand aliases for VQDMULH. 
llvm-svn: 146514
 2011-12-13 20:40:37 +00:00