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Commit Graph

1005 Commits

Author SHA1 Message Date
Andrew Lenharth
8e2beec4d1 fix typo
llvm-svn: 21693
2005-05-04 19:25:37 +00:00
Andrew Lenharth
8b64bd0fd5 Implement count leading zeros (ctlz), count trailing zeros (cttz), and count
population (ctpop).  Generic lowering is implemented, however only promotion
is implemented for SelectionDAG at the moment.

More coming soon.

llvm-svn: 21676
2005-05-03 17:19:30 +00:00
Chris Lattner
15d29b0220 Add support for FSIN/FCOS when unsafe math ops are enabled. Patch contributed by
Morten Ofstad!

llvm-svn: 21632
2005-04-30 04:25:35 +00:00
Chris Lattner
663664d10c Add support for llvm.sqrt and sin/cos if unsafe math optimizations are enabled.
llvm-svn: 21631
2005-04-30 04:12:40 +00:00
Chris Lattner
27a534f181 Add support for FSQRT node, patch contributed by Morten Ofstad
llvm-svn: 21610
2005-04-28 22:07:18 +00:00
Chris Lattner
236cef3563 Add some new X86 instrs, patch contributed by Morten Ofstad
llvm-svn: 21608
2005-04-28 21:50:05 +00:00
Chris Lattner
2f7a83ffbf Codegen fabs/fabsf as FABS. Patch contributed by Morten Ofstad
llvm-svn: 21607
2005-04-28 21:48:42 +00:00
Andrew Lenharth
2a00530fa7 Implement Value* tracking for loads and stores in the selection DAG. This enables one to use alias analysis in the backends.
(TRUNK)Stores and (EXT|ZEXT|SEXT)Loads have an extra SDOperand which is a SrcValueSDNode which contains the Value*.  Note that if the operation is introduced by the backend, it will still have the operand, but the value* will be null.

llvm-svn: 21599
2005-04-27 20:10:01 +00:00
Misha Brukman
bf3f6181fd * Remove trailing whitespace
* Convert tabs to spaces

llvm-svn: 21426
2005-04-21 23:38:14 +00:00
Chris Lattner
8d813a7d51 Handle stores of global address as stores of immediates. Instead of:
test1:
        movl $N, %eax
        movl %eax, G
        ret

emit:

test1:
        movl $N, G
        ret

llvm-svn: 21407
2005-04-21 19:11:03 +00:00
Chris Lattner
706775467b Handle (store &GV -> mem) as a store immediate. This often occurs for
printf format strings and other stuff.  Instead of generating this:

        movl $l1__2E_str_1, %eax
        movl %eax, (%esp)

we now emit:

        movl $l1__2E_str_1, (%esp)

llvm-svn: 21406
2005-04-21 19:03:24 +00:00
Nate Begeman
ecb5b5c028 Make pattern isel default for ppc
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
  0 == off
  1 == on
  2 == target default

llvm-svn: 21309
2005-04-15 22:12:16 +00:00
Chris Lattner
85c6a7bed0 Fix some mysteriously missing {}'s which cause the miscompilation of
Olden/mst, Ptrdist/bc, Obsequi, etc.

llvm-svn: 21274
2005-04-13 03:29:53 +00:00
Chris Lattner
f25fefd9cf Z_E_I is gone
llvm-svn: 21267
2005-04-13 02:39:05 +00:00
Chris Lattner
fd4d6e0847 Use live out sets for return values instead of imp_defs, which is cleaner and faster.
llvm-svn: 21181
2005-04-09 15:23:56 +00:00
Chris Lattner
39f963f968 This target does not support/want ISD::BRCONDTWOWAY
llvm-svn: 21164
2005-04-09 03:22:37 +00:00
Chris Lattner
583dcc66f2 X86 zero extends setcc results
llvm-svn: 21146
2005-04-07 19:41:46 +00:00
Chris Lattner
40ee8a062b Fix SingleSource/Regression/C/2005-05-06-LongLongSignedShift.c, we were not
properly sign extending the top of the result of a 64-bit shift right by
a constant > 32.

llvm-svn: 21120
2005-04-06 20:59:35 +00:00
Chris Lattner
c87ff88efb Add (untested) support for MULHS and MULHU.
llvm-svn: 21107
2005-04-06 04:21:07 +00:00
Chris Lattner
ba7cdbebb1 add signed versions of the extra precision multiplies
llvm-svn: 21106
2005-04-06 04:19:22 +00:00
Chris Lattner
8f30d63c1a add support for FABS and FNEG
llvm-svn: 21015
2005-04-02 05:30:17 +00:00
Chris Lattner
a5d4718875 This target doesn't support fabs/fneg yet.
llvm-svn: 21010
2005-04-02 05:03:24 +00:00
Chris Lattner
71434aa2dd add an fabs instr
llvm-svn: 21006
2005-04-02 04:31:56 +00:00
Chris Lattner
8ee783d9f0 Add support for 64-bit shifts.
llvm-svn: 21005
2005-04-02 04:01:14 +00:00
Chris Lattner
67da3fdb70 Add support for ISD::UNDEF to the X86 be
llvm-svn: 20990
2005-04-01 22:46:45 +00:00
Chris Lattner
46c4246df1 don't depend on the cfg being set up yet
llvm-svn: 20936
2005-03-30 01:10:00 +00:00
Nate Begeman
f821401825 Change interface to LowerCallTo to take a boolean isVarArg argument.
llvm-svn: 20842
2005-03-26 01:29:23 +00:00
Chris Lattner
ad07b1bc54 eliminate dead variables, patch contributed by Gabor Greif!
llvm-svn: 20812
2005-03-24 17:32:20 +00:00
Nate Begeman
175a9f1cc6 Remove comments that are now meaningless from the pattern ISels, at Chris's
request.

llvm-svn: 20804
2005-03-24 04:39:54 +00:00
Chris Lattner
79ba9d58fd Don't emit two comparisons when comparing a FP value against zero!
llvm-svn: 20651
2005-03-17 16:29:26 +00:00
Chris Lattner
c9a3ea81bf Fix the missing symbols problem Bill was hitting. Patch contributed by
Bill Wendling!!

llvm-svn: 20649
2005-03-17 15:38:16 +00:00
Chris Lattner
4b688a1c70 This mega patch converts us from using Function::a{iterator|begin|end} to
using Function::arg_{iterator|begin|end}.  Likewise Module::g* -> Module::global_*.

This patch is contributed by Gabor Greif, thanks!

llvm-svn: 20597
2005-03-15 04:54:21 +00:00
Reid Spencer
b0ca4aa8cd Patch to make assembly output compatible with mingw compilation (identical
to cygwin)

llvm-svn: 20520
2005-03-08 17:02:05 +00:00
Chris Lattner
a024984017 Fix spelling, patch contributed by Gabor Greif!
llvm-svn: 20343
2005-02-27 06:18:25 +00:00
Chris Lattner
9838ab1271 Silence some uninit variable warnings.
llvm-svn: 20284
2005-02-23 05:57:21 +00:00
Chris Lattner
ab92b92bc5 We can fold promoted and non-promoted loads into divs also!
llvm-svn: 19835
2005-01-25 20:35:10 +00:00
Chris Lattner
a9a0369879 Fold promoted loads into binary ops for FP, allowing us to generate m32 forms
of FP ops.

llvm-svn: 19834
2005-01-25 20:03:11 +00:00
Chris Lattner
6ff85c3152 Silence a warning.
llvm-svn: 19798
2005-01-23 23:20:06 +00:00
Chris Lattner
94952e0947 Allow the FP stackifier to completely ignore functions that do not use FP at
all.  This should speed up the X86 backend fairly significantly on integer
codes.  Now if only we didn't have to compute livevar still... ;-)

llvm-svn: 19796
2005-01-23 23:13:59 +00:00
Reid Spencer
5c7b6e83f0 Support Cygwin assembly generation. The cygwin version of Gnu ASsembler
doesn't support certain directives and symbols on cygwin are prefixed with
an underscore. This patch makes the necessary adjustments to the output.

llvm-svn: 19775
2005-01-23 03:52:14 +00:00
Chris Lattner
b4cf4ffb04 Speed up folding operations into loads.
llvm-svn: 19733
2005-01-21 21:43:02 +00:00
Chris Lattner
fd4d7f71ae The ever-important vanity pass name :)
llvm-svn: 19731
2005-01-21 21:35:14 +00:00
Chris Lattner
5f2fbeaa69 Fix a FIXME: realize that argument stores are all independent (don't alias)
llvm-svn: 19728
2005-01-21 19:46:38 +00:00
Chris Lattner
febeb380ae Implement ADD_PARTS/SUB_PARTS so that 64-bit integer add/sub work. This
fixes most of the remaining llc-beta failures.

llvm-svn: 19716
2005-01-20 18:53:00 +00:00
Chris Lattner
8b0a2a3251 Fix a crash compiling 134.perl.
llvm-svn: 19711
2005-01-20 16:50:16 +00:00
Chris Lattner
6534e1ede3 Fix a problem where were were literally selecting for INCREASED register
pressure, not decreases register pressure.  Fix problem where we accidentally
swapped the operands of SHLD, which caused fourinarow to fail.  This fixes
fourinarow.

llvm-svn: 19697
2005-01-19 17:24:34 +00:00
Chris Lattner
b75589131d When commuting these instructions, make sure to actually swap the operands too.
llvm-svn: 19694
2005-01-19 16:55:52 +00:00
Chris Lattner
fde1a5688b Implement Regression/CodeGen/X86/rotate.ll: emit rotate instructions (which
typically cost 1 cycle) instead of shld/shrd instruction (which are typically
6 or more cycles).  This also saves code space.

For example, instead of emitting:

rotr:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %CL, BYTE PTR [%ESP + 8]
        shrd %EAX, %EAX, %CL
        ret
rotli:
        mov %EAX, DWORD PTR [%ESP + 4]
        shrd %EAX, %EAX, 27
        ret

Emit:

rotr32:
        mov %CL, BYTE PTR [%ESP + 8]
        mov %EAX, DWORD PTR [%ESP + 4]
        ror %EAX, %CL
        ret
rotli32:
        mov %EAX, DWORD PTR [%ESP + 4]
        ror %EAX, 27
        ret

We also emit byte rotate instructions which do not have a sh[lr]d counterpart
at all.

llvm-svn: 19692
2005-01-19 08:07:05 +00:00
Chris Lattner
34757ff939 Add rotate instructions.
llvm-svn: 19690
2005-01-19 07:50:03 +00:00
Chris Lattner
e539ce8223 Match 16-bit shld/shrd instructions as well, implementing shift-double.llx:test5
llvm-svn: 19689
2005-01-19 07:37:26 +00:00