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1005 Commits

Author SHA1 Message Date
Chris Lattner
9258948b08 Codegen signed divides by 2 and -2 more efficiently. In particular 
instead of:

s:   ;; X / 2
        movl 4(%esp), %eax
        movl %eax, %ecx
        shrl $31, %ecx
        movl %eax, %edx
        addl %ecx, %edx
        sarl $1, %eax
        ret

t:   ;; X / -2
        movl 4(%esp), %eax
        movl %eax, %ecx
        shrl $31, %ecx
        movl %eax, %edx
        addl %ecx, %edx
        sarl $1, %eax
        negl %eax
        ret

Emit:

s:
        movl 4(%esp), %eax
        cmpl $-2147483648, %eax
        sbbl $-1, %eax
        sarl $1, %eax
        ret

t:
        movl 4(%esp), %eax
        cmpl $-2147483648, %eax
        sbbl $-1, %eax
        sarl $1, %eax
        negl %eax
        ret

llvm-svn: 16760
 2004-10-06 04:02:39 +00:00
Chris Lattner
acd213fba3 Add some new instructions. Fix the asm string for sbb32rr 
llvm-svn: 16759
 2004-10-06 04:01:02 +00:00
Chris Lattner
0228f228df * Prune #includes 
* Update comments
* Rearrange code a bit
* Finally ELIMINATE the GAS workaround emitter for Intel mode.  woot!

llvm-svn: 16647
 2004-10-04 07:31:08 +00:00
Chris Lattner
581948c8f6 Add support for emitting AT&T style .s files, and make it the default. Users 
may now choose their output format with the -x86-asm-syntax={intel|att} flag.

llvm-svn: 16646
 2004-10-04 07:24:48 +00:00
Chris Lattner
5959f4a108 Convert some missed patterns to support AT&T style 
llvm-svn: 16645
 2004-10-04 07:23:07 +00:00
Chris Lattner
a05d9f53bb Apparently the GNU assembler has a HUGE hack to be compatible with really 
old and broken AT&T syntax assemblers.  The problem with this hack is that
*SOME* forms of the fdiv and fsub instructions have the 'r' bit inverted.
This was a real pain to figure out, but is trivially easy to support: thus
we are now bug compatible with gas and gcc.

llvm-svn: 16644
 2004-10-04 07:08:46 +00:00
Chris Lattner
08098895db Fix incorrect suffix 
llvm-svn: 16642
 2004-10-04 05:20:16 +00:00
Chris Lattner
c2fc9597bd Fix some more missed suffixes and swapped operands 
llvm-svn: 16641
 2004-10-04 01:38:10 +00:00
Chris Lattner
7b15a84728 Add missing suffixes to FP instructions for AT&T mode 
llvm-svn: 16640
 2004-10-04 00:43:31 +00:00
Chris Lattner
8d44dcca97 Add support for the -x86-asm-syntax flag, which can be used to choose between 
Intel and AT&T style assembly language.  The ultimate goal of this is to
eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission
is not fully operational.

llvm-svn: 16639
 2004-10-03 20:36:57 +00:00
Chris Lattner
94780713a8 Add support to the instruction patterns for AT&T style output, which will 
hopefully lead to the death of the 'GasBugWorkaroundEmitter'.  This also
includes changes to wrap the whole file to 80 columns! Woot! :)

Note that the AT&T style output has not been tested at all.

llvm-svn: 16638
 2004-10-03 20:35:00 +00:00
Alkis Evlogimenos
3f8f30bcb8 The real x87 floating point registers should not be allocatable. They 
are only used by the stackifier when transforming FPn register
allocations to the real stack file x87 registers.

llvm-svn: 16472
 2004-09-21 21:22:11 +00:00
Misha Brukman
e877aacbaa s/ISel/X86ISel/ to have unique class names for debugging via gdb because the C++ 
front-end in gcc does not mangle classes in anonymous namespaces correctly.

llvm-svn: 16469
 2004-09-21 18:21:21 +00:00
Reid Spencer
c6a8d70cff Convert code to compile with vc7.1. 
Patch contributed by Paolo Invernizzi. Thanks Paolo!

llvm-svn: 16368
 2004-09-15 17:06:42 +00:00
Misha Brukman
9e5af08ef9 Fit long lines into 80 cols via creative space elimination 
llvm-svn: 16353
 2004-09-15 01:40:18 +00:00
Chris Lattner
aee36bb527 Revamp the Register class, and allow the use of the RegisterGroup class to 
specify aliases directly in register definitions.

Patch contributed by Jason Eckhardt!

llvm-svn: 16330
 2004-09-14 04:17:02 +00:00
Misha Brukman
ec87a61944 Fix filename: Printer.cpp has become X86AsmPrinter.cpp 
llvm-svn: 16299
 2004-09-12 21:26:04 +00:00
Alkis Evlogimenos
4d2b0a2b5b Use a shorter form to express implicit use/defs in FpGETRESULT and 
FpSETRESULT.

llvm-svn: 16247
 2004-09-08 18:29:31 +00:00
Alkis Evlogimenos
3540de9ea6 A call instruction should implicitely define ST0 since the return 
value is returned in that register. The pseudo instructions
FpGETRESULT and FpSETRESULT shold also have an implicity use and def
of ST0 repsecitvely.

llvm-svn: 16246
 2004-09-08 16:54:54 +00:00
Reid Spencer
c4abcbefb1 Changes For Bug 352 
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.

llvm-svn: 16137
 2004-09-01 22:55:40 +00:00
Reid Spencer
59cb27bcdc Reduce the number of arguments in the instruction builder and make some 
improvements on instruction selection that account for register and frame
index bases.

Patch contributed by Jeff Cohen. Thanks Jeff!

llvm-svn: 16110
 2004-08-30 00:13:26 +00:00
Chris Lattner
6781bb48eb Add -sse[,2,3] arguments to LLC 
llvm-svn: 16018
 2004-08-24 08:18:44 +00:00
Chris Lattner
28c7ae5697 Nuke commented out stuff 
llvm-svn: 16017
 2004-08-24 08:18:27 +00:00
Chris Lattner
64d3bc5e85 Switch from bytes to bits for alignment for consistency 
llvm-svn: 15974
 2004-08-21 20:14:13 +00:00
Chris Lattner
4427fd9a3c Reduce uses of getRegClass 
llvm-svn: 15973
 2004-08-21 20:13:52 +00:00
Chris Lattner
8c5096d223 Rename var 
llvm-svn: 15897
 2004-08-18 02:22:55 +00:00
Chris Lattner
d3d5c1d2a2 Start using alignment output routines from AsmPrinter. 
Changes to make this more similar to the ppc asmprinter

llvm-svn: 15890
 2004-08-17 19:25:42 +00:00
Chris Lattner
052cebe33c Use the AsmPrinter emitGlobalConstant. 
llvm-svn: 15872
 2004-08-17 06:48:55 +00:00
Chris Lattner
bf5dba50c5 Start using the AsmPrinter to emit our first class constants. This also 
drops our half-assed support for cygwin, which noone uses and doesn't work
anyway.

llvm-svn: 15839
 2004-08-16 23:16:06 +00:00
Chris Lattner
3383506bcc Disable the pattern isel 
llvm-svn: 15787
 2004-08-15 23:02:17 +00:00
Chris Lattner
555a585fd8 Code insertion methods now return void instead of an int. 
llvm-svn: 15780
 2004-08-15 22:15:11 +00:00
Chris Lattner
e58190f5f6 These methods no longer take a TargetRegisterClass* operand. 
llvm-svn: 15774
 2004-08-15 21:56:44 +00:00
Nate Begeman
fabece673b Eliminate MachineFunction& argument from eliminateFrameIndex in x86 Target. Get MachineFunction from MachineInstruction's parent's parent 
llvm-svn: 15739
 2004-08-14 22:05:10 +00:00
Chris Lattner
5e7e9b6c26 Remove a bunch of ad-hoc target-specific flags that were only used by the 
old asmprinter.

llvm-svn: 15660
 2004-08-11 07:12:04 +00:00
Chris Lattner
b09bc9d4e3 Remove a dead method 
llvm-svn: 15659
 2004-08-11 07:07:14 +00:00
Chris Lattner
3fc9d4490c Finally, the entire instruction asmprinter is now generated from tblgen, woo! 
llvm-svn: 15658
 2004-08-11 07:02:04 +00:00
Chris Lattner
3cef2f82ff Add asmprintergen support for the last X86 instruction that needs it: pcrelative calls. 
llvm-svn: 15657
 2004-08-11 06:59:12 +00:00
Chris Lattner
309873fed0 This file is long dead 
llvm-svn: 15656
 2004-08-11 06:55:12 +00:00
Chris Lattner
9c171be048 Scrunch memoperands, add a few more for floating point memops 
Eliminate the FPI*m classes, converting them to use FPI instead.

llvm-svn: 15655
 2004-08-11 06:50:10 +00:00
Chris Lattner
f34003128d Move hacks up 
llvm-svn: 15654
 2004-08-11 06:09:55 +00:00
Chris Lattner
b287047c3f Make FPI take asm string and operand list 
llvm-svn: 15653
 2004-08-11 05:54:16 +00:00
Chris Lattner
c304bf7e03 Nuke the Im*i* patterns, by asmprintergenifying all users. 
llvm-svn: 15652
 2004-08-11 05:31:07 +00:00
Chris Lattner
65ab459759 X86 instructions that read-modify-write memory are not LLVM two-address instructions. 
llvm-svn: 15651
 2004-08-11 05:07:25 +00:00
Chris Lattner
384711a69c Get rid of the Im8, Im16, Im32 classes, converting more instructions over to 
asmprintergeneration

llvm-svn: 15650
 2004-08-11 04:31:00 +00:00
Chris Lattner
24279a8ac8 Remove dead method 
llvm-svn: 15647
 2004-08-11 02:26:39 +00:00
Chris Lattner
b66b9cd4a9 Convert asmprinter to new style of instruction printer 
Start asmprintergen'ifying machine instrs with memory operands.

llvm-svn: 15646
 2004-08-11 02:25:00 +00:00
Chris Lattner
5cf0a20d4f This is purely a formatting patch that gets us closer to the mecca of fitting 
X86InstrInfo.td into 80 columns

llvm-svn: 15629
 2004-08-10 21:21:30 +00:00
Chris Lattner
f6c4de46e0 Drop the first argument of FPI, and asmprinterify fxch 
llvm-svn: 15628
 2004-08-10 21:02:13 +00:00
Chris Lattner
97abe28059 This purely mechanical patch gives the "I" tblgen class operand list and asm 
string operands, and adjusts all users to pass them in instead of using II.

llvm-svn: 15624
 2004-08-10 20:17:41 +00:00
Chris Lattner
332fa9be1c Convert Ii32 instructions over to use the asmprinter generator 
llvm-svn: 15621
 2004-08-10 19:06:36 +00:00
Chris Lattner
068209661a Convert the Ii16 instructions over 
llvm-svn: 15606
 2004-08-10 16:22:02 +00:00
Chris Lattner
315782f0ac Convert all Ii8 instructions over to the autogenerated asmprinter. 
llvm-svn: 15605
 2004-08-10 16:09:54 +00:00
Alkis Evlogimenos
f853362a44 Stop using getValues(). 
llvm-svn: 15487
 2004-08-04 08:44:43 +00:00
Chris Lattner
2677b71f64 Fix a warning 
llvm-svn: 15409
 2004-08-01 19:31:30 +00:00
Chris Lattner
df7c9d0339 Convert all I<> instructions to asmformat. 
Delete the 'name' field of all instructions that have asmformats.

llvm-svn: 15403
 2004-08-01 09:52:59 +00:00
Chris Lattner
90a4b737dd Eliminate 3 of the X86 printImplicit* flags. 
llvm-svn: 15398
 2004-08-01 08:23:17 +00:00
Chris Lattner
de4844f84d Get rid of 3 of the 4 'printimplicit' flags. Implicit operands are now 
explicitly listed in the asm string.

llvm-svn: 15397
 2004-08-01 08:22:29 +00:00
Chris Lattner
0c5ab21dcd Convert more instructions over to the asmprinter 
llvm-svn: 15396
 2004-08-01 08:13:11 +00:00
Chris Lattner
0a6fedb451 Handle registers a bit more efficiently 
llvm-svn: 15395
 2004-08-01 08:12:41 +00:00
Chris Lattner
c40aa40525 give FP stack registers names 
llvm-svn: 15394
 2004-08-01 08:12:13 +00:00
Chris Lattner
6c596faddb Switch more instructions over to using the asmprinter. Fix bugs in the emission 
of in/out instructions (missing %'s on registers).

llvm-svn: 15393
 2004-08-01 07:44:35 +00:00
Chris Lattner
3a928f8119 The tblgen'erated asmparser wants a way to print operands. 
llvm-svn: 15392
 2004-08-01 07:43:46 +00:00
Chris Lattner
e4c868ffa0 Rename the Printer class -> X86AsmPrinter. 
Include the tablegenerated assembly writer.

llvm-svn: 15389
 2004-08-01 06:02:08 +00:00
Chris Lattner
a02166d28b Factor a bunch of the rules and add support for generating the asmwriter. 
llvm-svn: 15388
 2004-08-01 06:01:32 +00:00
Chris Lattner
9a7b050ebb Specify an asm string and operands lists for a bunch of instructions. 
This only really covers no-operand instructions so far.

llvm-svn: 15387
 2004-08-01 06:01:00 +00:00
Chris Lattner
101dccd430 Completely disable the pattern isel until it is more substantial. 
llvm-svn: 15380
 2004-08-01 03:28:02 +00:00
Chris Lattner
9bce44c8cc Entirely eliminate all patterns and expanders from this file. We shall go 
with an incremental approach rather than a revolutionary approach.

llvm-svn: 15379
 2004-08-01 03:25:01 +00:00
Chris Lattner
0717ef353d Remove obsolete file 
llvm-svn: 15377
 2004-08-01 03:19:28 +00:00
Alkis Evlogimenos
cdcb1c62e5 Align breaks. 
llvm-svn: 15371
 2004-07-31 10:05:44 +00:00
Chris Lattner
0d66480e9e Add breaks 
llvm-svn: 15365
 2004-07-31 09:53:31 +00:00
Alkis Evlogimenos
1eb8a5dc09 Simplify code a bit. 
llvm-svn: 15364
 2004-07-31 09:44:32 +00:00
Alkis Evlogimenos
de150fb74b Correctly spell 'unconditional'. 
llvm-svn: 15363
 2004-07-31 09:41:44 +00:00
Alkis Evlogimenos
bc3d550391 Implement insertGoto and reverseBranchCondition for the X86. 
llvm-svn: 15362
 2004-07-31 09:38:47 +00:00
Chris Lattner
9a23ab1e63 Mark barrier instructions. Execution does not fall through uncond branches 
or return intructions.

llvm-svn: 15356
 2004-07-31 02:10:53 +00:00
Misha Brukman
3e7a88e9db Fix indentation: should be 2 spaces. 
llvm-svn: 15240
 2004-07-26 18:48:58 +00:00
Misha Brukman
61ff8a374f Fix file header as it has been renamed. 
llvm-svn: 15239
 2004-07-26 18:45:48 +00:00
Misha Brukman
ccd1114518 Renamed files to have the `X86' prefix for uniqueness purposes. 
All CVS history was renamed, the *,v were copied over.  No worries.

llvm-svn: 15238
 2004-07-26 18:43:11 +00:00
Chris Lattner
093d84c480 Remove some (LARGE) abandoned code for the release. If this is ever needed 
again in the future, it can be resurrected out of CVS

llvm-svn: 15112
 2004-07-22 21:30:35 +00:00
Chris Lattner
e3d3cd3e71 Fix cases where we generated horrible code like this: 
mov %EDI, 12
        add %EDI, %ECX
        mov %ECX, 12
        add %ECX, %EDX
        mov %EDX, 12
        add %EDX, %ESI

instead (really!) generate this:

        add %ECX, 12
        add %EDX, 12
        add %ESI, 12

llvm-svn: 15090
 2004-07-21 21:28:26 +00:00
Chris Lattner
e8b9b58454 While I'm at it, don't break codegen of mul by 3,5,9. 
llvm-svn: 15013
 2004-07-19 23:50:57 +00:00
Chris Lattner
f668465840 Generate better code for multiplies by negative constants like -4, -1, -9, etc. 
llvm-svn: 15012
 2004-07-19 23:47:21 +00:00
Reid Spencer
14243817ec bug 122: 
- Replace ConstantPointerRef usage with GlobalValue usage
- Minimize redundant isa<GlobalValue> usage
- Correct isa<Constant> for GlobalValue subclass

llvm-svn: 14950
 2004-07-18 00:38:32 +00:00
Chris Lattner
9bcf258cc3 Make sure to emit the immediate byte for instructions like: 
shrd [mem], reg, imm

This fixes the jit-ls failure on 186.crafty.

llvm-svn: 14914
 2004-07-17 20:26:14 +00:00
Chris Lattner
d7905d828b Reserve the correct amt of space. 
llvm-svn: 14913
 2004-07-17 20:24:05 +00:00
Chris Lattner
c4888ccda7 Patches towards fixing PR341 
llvm-svn: 14841
 2004-07-15 02:14:30 +00:00
Chris Lattner
210ffe4b77 Improve codegen for the LLVM offsetof/sizeof "operator". Before we compiled 
this LLVM function:

int %foo() {
        ret int cast (int** getelementptr (int** null, int 1) to int)
}

into:

foo:
        mov %EAX, 0
        lea %EAX, DWORD PTR [%EAX + 4]
        ret

now we compile it into:

foo:
        mov %EAX, 4
        ret

This sequence is frequently generated by the MSIL front-end, and soon the malloc lowering pass and
Java front-ends as well..

-Chris

llvm-svn: 14834
 2004-07-15 00:58:53 +00:00
Chris Lattner
6331eb6bbe Delete the allocate*TargetMachine function, which is now dead . 
The shared command line options are now in a header that makes sense.

llvm-svn: 14756
 2004-07-11 04:17:10 +00:00
Chris Lattner
b67e3b01bc Make these format a bit nicer 
llvm-svn: 14747
 2004-07-11 03:27:42 +00:00
Chris Lattner
2ada866a78 Auto-registrate target 
llvm-svn: 14745
 2004-07-11 02:48:49 +00:00
Reid Spencer
50ec3f9325 Add #include <iostream> since Value.h does not #include it any more. 
llvm-svn: 14622
 2004-07-04 12:19:56 +00:00
Chris Lattner
6da0499f4b Remove dead blocks 
llvm-svn: 14564
 2004-07-02 05:46:41 +00:00
Misha Brukman
9e015dddb8 Fix associativity of parameters to assert(): now it actually makes sense. 
llvm-svn: 14483
 2004-06-29 19:43:20 +00:00
Misha Brukman
b3e4179f42 Convert tabs to spaces. 
llvm-svn: 14482
 2004-06-29 19:28:53 +00:00
Chris Lattner
2abf0134d0 I believe that the code generator now properly handles dead basic blocks. If not, 
this is a bug, and should be fixed.

llvm-svn: 14476
 2004-06-29 07:17:12 +00:00
Chris Lattner
cd1a39bbec Fix a regression from r1.224. In particular, codegen a cast from double -> 
float as a truncation by going through memory.  This truncation was being
skipped, which caused 175.vpr to fail after aggressive register promotion.

llvm-svn: 14473
 2004-06-29 00:14:38 +00:00
Tanya Lattner
da38dc5180 Made a fix so that you can print out MachineInstrs that belong to a MachineBasicBlock that is not yet attached to a MachineFunction. This change includes changing the third operand (TargetMachine) to a pointer for the MachineInstr::print function. 
llvm-svn: 14389
 2004-06-25 00:13:11 +00:00
Misha Brukman
e38f7ed2cc Spell out `NoFramePointerElim' for readability. 
llvm-svn: 14299
 2004-06-21 21:17:44 +00:00
Misha Brukman
a2ac4e4345 Use the common `NoFPElim' setting instead of our own. 
llvm-svn: 14298
 2004-06-21 21:10:24 +00:00
Chris Lattner
cc465361d9 Move the IntrinsicLowering header into the CodeGen directory, as per PR346 
llvm-svn: 14266
 2004-06-20 07:49:54 +00:00
Chris Lattner
9e1bbe86ba Codegen sub C, X a little bit better for register pressure. Instead of 
mov REG, C
sub REG, X

generate:

neg X
add X, C

which uses one less reg

llvm-svn: 14213
 2004-06-18 00:50:37 +00:00
Chris Lattner
a5750b975a Fold setcc instructions into select and branches that are not in the same BB as 
the setcc.

llvm-svn: 14212
 2004-06-18 00:29:22 +00:00
Chris Lattner
f815117481 Do not fold loads into instructions if it is used more than once. In particular 
we do not want to fold the load in cases like this:

  X = load
    = add A, X
    = add B, X

llvm-svn: 14204
 2004-06-17 22:15:25 +00:00
Chris Lattner
0cd29ae2cd Rename Type::PrimitiveID to TypeId and ::getPrimitiveID() to ::getTypeID() 
llvm-svn: 14201
 2004-06-17 18:19:28 +00:00
Chris Lattner
9bb0083d16 Remove support for llvm.isnan. Alkis wins :) 
llvm-svn: 14189
 2004-06-15 21:48:07 +00:00
Chris Lattner
d11493d8c4 Add basic support for the isunordered intrinsic. The isnan stuff still needs to go 
llvm-svn: 14185
 2004-06-15 21:36:44 +00:00
Chris Lattner
3a8e675c03 By far, one of the most common uses of isnan is to make 'isunordered' 
comparisons.  In an 'isunordered' predicate, which looks like this at
the LLVM level:

        %a = call bool %llvm.isnan(double %X)
        %b = call bool %llvm.isnan(double %Y)
        %COM = or bool %a, %b

We used to generate this code:

        fxch %ST(1)
        fucomip %ST(0), %ST(0)
        setp %AL
        fucomip %ST(0), %ST(0)
        setp %AH
        or %AL, %AH

With this patch, we generate this code:

        fucomip %ST(0), %ST(1)
        fstp %ST(0)
        setp %AL

Which should make alkis happy.  Tested as X86/compare_folding.llx:test1

llvm-svn: 14148
 2004-06-11 05:33:49 +00:00
Chris Lattner
f78e3e7f63 Fix bug in previous checkin 
llvm-svn: 14146
 2004-06-11 05:22:44 +00:00
Chris Lattner
7d8093efb1 No really, these are dead now 
llvm-svn: 14145
 2004-06-11 04:50:14 +00:00
Chris Lattner
a8e603b719 Now that compare instructions aren't lumped in with the other twoargfp instructions, 
we can get rid of the FpUCOM/FpUCOMi pseudo instructions, which makes stuff simpler
and faster.

llvm-svn: 14144
 2004-06-11 04:49:02 +00:00
Chris Lattner
b050f778ca Introduce a new FP instruction type to separate the compare cases from the 
twoarg cases.

llvm-svn: 14143
 2004-06-11 04:41:24 +00:00
Chris Lattner
edb06042b9 Add direct support for the isnan intrinsic, implementing test/Regression/CodeGen/X86/isnan.llx 
testcase

llvm-svn: 14141
 2004-06-11 04:31:10 +00:00
Chris Lattner
4c8b57ea31 Add support for the setp instructions 
llvm-svn: 14140
 2004-06-11 04:30:06 +00:00
Chris Lattner
c66e996765 Split compare instruction handling OUT of handleTwoArgFP into handleCompareFP. 
This makes the code much simpler, and the two cases really do belong apart.
Once we do it, it's pretty obvious how flawed the logic was for A != A case,
so I fixed it (fixing PR369).

This also uses freeStackSlotAfter instead of inserting an fxchg then
popStackAfter'ing in the case where there is a dead result (unlikely, but
possible), producing better code.

llvm-svn: 14139
 2004-06-11 04:25:06 +00:00
Chris Lattner
1f0e0d55c4 Fix the fixed stack offset, patch contributed by Vladimir Prus 
llvm-svn: 14110
 2004-06-10 06:19:25 +00:00
John Criswell
287e3fc88b Fix for PR#366. We use getClassB() so that we can handle cast instructions 
that cast to bool.

llvm-svn: 14096
 2004-06-09 15:18:51 +00:00
Chris Lattner
c51b272047 This file is obsolete 
llvm-svn: 14005
 2004-06-04 00:15:21 +00:00
Chris Lattner
5ad9eaab1a Convert to the new TargetMachine interface. 
llvm-svn: 13952
 2004-06-02 05:55:25 +00:00
Chris Lattner
1e22b42cb6 Add support for accurate garbage collection to the LLVM code generators 
llvm-svn: 13696
 2004-05-23 21:23:35 +00:00
Chris Lattner
85f19c7b3f Add some notes to myself, no functional changes 
llvm-svn: 13695
 2004-05-23 21:23:12 +00:00
Chris Lattner
5862899c44 minor wording change 
llvm-svn: 13694
 2004-05-23 21:22:55 +00:00
Brian Gaeke
e5736bf986 Don't keep track of references to LLVM BasicBlocks while emitting; use 
MachineBasicBlocks instead.

llvm-svn: 13568
 2004-05-14 06:54:58 +00:00
Brian Gaeke
a25a10e73b Support MachineBasicBlock operands on RawFrm instructions. 
Get rid of separate numbering for LLVM BasicBlocks; use the automatically
generated MachineBasicBlock numbering.

llvm-svn: 13567
 2004-05-14 06:54:57 +00:00
Brian Gaeke
a17301ca8b Generate branch machine instructions with MachineBasicBlock operands instead of 
LLVM BasicBlock operands.

llvm-svn: 13566
 2004-05-14 06:54:56 +00:00
Chris Lattner
269da7901a Two more improvements for null pointer handling: storing a null pointer 
and passing a null pointer into a function.

For this testcase:

void %test(int** %X) {
  store int* null, int** %X
  call void %test(int** null)
  ret void
}

we now generate this:

test:
        sub %ESP, 12
        mov %EAX, DWORD PTR [%ESP + 16]
        mov DWORD PTR [%EAX], 0
        mov DWORD PTR [%ESP], 0
        call test
        add %ESP, 12
        ret

instead of this:

test:
        sub %ESP, 12
        mov %EAX, DWORD PTR [%ESP + 16]
        mov %ECX, 0
        mov DWORD PTR [%EAX], %ECX
        mov %EAX, 0
        mov DWORD PTR [%ESP], %EAX
        call test
        add %ESP, 12
        ret

llvm-svn: 13558
 2004-05-13 15:26:48 +00:00
Chris Lattner
dc8e8484e5 Second half of my fixed-sized-alloca patch. This folds the LEA to compute 
the alloca address into common operations like loads/stores.

In a simple testcase like this (which is just designed to excersize the
alloca A, nothing more):

int %test(int %X, bool %C) {
        %A = alloca int
        store int %X, int* %A
        store int* %A, int** %G
        br bool %C, label %T, label %F
T:
        call int %test(int 1, bool false)
        %V = load int* %A
        ret int %V
F:
        call int %test(int 123, bool true)
        %V2 = load int* %A
        ret int %V2
}

We now generate:

test:
        sub %ESP, 12
        mov %EAX, DWORD PTR [%ESP + 16]
        mov %CL, BYTE PTR [%ESP + 20]
***     mov DWORD PTR [%ESP + 8], %EAX
        mov %EAX, OFFSET G
        lea %EDX, DWORD PTR [%ESP + 8]
        mov DWORD PTR [%EAX], %EDX
        test %CL, %CL
        je .LBB2 # PC rel: F
.LBB1:  # T
        mov DWORD PTR [%ESP], 1
        mov DWORD PTR [%ESP + 4], 0
        call test
***     mov %EAX, DWORD PTR [%ESP + 8]
        add %ESP, 12
        ret
.LBB2:  # F
        mov DWORD PTR [%ESP], 123
        mov DWORD PTR [%ESP + 4], 1
        call test
***     mov %EAX, DWORD PTR [%ESP + 8]
        add %ESP, 12
        ret

Instead of:

test:
        sub %ESP, 20
        mov %EAX, DWORD PTR [%ESP + 24]
        mov %CL, BYTE PTR [%ESP + 28]
***     lea %EDX, DWORD PTR [%ESP + 16]
***     mov DWORD PTR [%EDX], %EAX
        mov %EAX, OFFSET G
        mov DWORD PTR [%EAX], %EDX
        test %CL, %CL
***     mov DWORD PTR [%ESP + 12], %EDX
        je .LBB2 # PC rel: F
.LBB1:  # T
        mov DWORD PTR [%ESP], 1
        mov %EAX, 0
        mov DWORD PTR [%ESP + 4], %EAX
        call test
***     mov %EAX, DWORD PTR [%ESP + 12]
***     mov %EAX, DWORD PTR [%EAX]
        add %ESP, 20
        ret
.LBB2:  # F
        mov DWORD PTR [%ESP], 123
        mov %EAX, 1
        mov DWORD PTR [%ESP + 4], %EAX
        call test
***     mov %EAX, DWORD PTR [%ESP + 12]
***     mov %EAX, DWORD PTR [%EAX]
        add %ESP, 20
        ret

llvm-svn: 13557
 2004-05-13 15:12:43 +00:00
Chris Lattner
94de563118 Substantially improve code generation for address exposed locals (aka fixed 
sized allocas in the entry block).  Instead of generating code like this:

entry:
  reg1024 = ESP+1234
... (much later)
  *reg1024 = 17


Generate code that looks like this:
entry:
  (no code generated)
... (much later)
  t = ESP+1234
  *t = 17

The advantage being that we DRAMATICALLY reduce the register pressure for these
silly temporaries (they were all being spilled to the stack, resulting in very
silly code).  This is actually a manual implementation of rematerialization :)

I have a patch to fold the alloca address computation into loads & stores, which
will make this much better still, but just getting this right took way too much time
and I'm sleepy.

llvm-svn: 13554
 2004-05-13 07:40:27 +00:00
Chris Lattner
a19bb14155 Pass boolean constants into function calls more efficiently, generating: 
mov DWORD PTR [%ESP + 4], 1

instead of:

        mov %EAX, 1
        mov DWORD PTR [%ESP + 4], %EAX

llvm-svn: 13494
 2004-05-12 16:35:04 +00:00
Chris Lattner
a407338e12 Fix a fairly serious pessimizaion that was preventing us from efficiently 
compiling things like 'add long %X, 1'.  The problem is that we were switching
the order of the operands for longs even though we can't fold them yet.

llvm-svn: 13451
 2004-05-10 15:15:55 +00:00
Chris Lattner
0962db8f10 Fix some comments, avoid sign extending booleans when zero extend works fine 
llvm-svn: 13440
 2004-05-09 23:16:33 +00:00
Chris Lattner
d18c637a37 Generate more efficient code for casting booleans to integers (no sign extension required) 
llvm-svn: 13439
 2004-05-09 22:28:45 +00:00
Chris Lattner
67c21e74ec Codegen floating point stores of constants into integer instructions. This 
allows us to compile:

store float 10.0, float* %P

into:
        mov DWORD PTR [%EAX], 1092616192

instead of:

.CPItest_0:                                     # float 0x4024000000000000
.long   1092616192      # float 10
...
        fld DWORD PTR [.CPItest_0]
        fstp DWORD PTR [%EAX]

llvm-svn: 13409
 2004-05-07 21:18:15 +00:00
Chris Lattner
2021030378 Make comparisons against the null pointer as efficient as integer comparisons 
against zero.  In particular, don't emit:

        mov %ESI, 0
        cmp %ECX, %ESI

instead, emit:

       test %ECX, %ECX

llvm-svn: 13407
 2004-05-07 19:55:55 +00:00
Chris Lattner
42e602b94f Remove unneeded check 
llvm-svn: 13355
 2004-05-04 19:35:11 +00:00
Chris Lattner
dac54ebbee Improve signed division by power of 2 *dramatically* from this: 
div:
        mov %EDX, DWORD PTR [%ESP + 4]
        mov %ECX, 64
        mov %EAX, %EDX
        sar %EDX, 31
        idiv %ECX
        ret

to this:

div:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, %EAX
        sar %ECX, 5
        shr %ECX, 26
        mov %EDX, %EAX
        add %EDX, %ECX
        sar %EAX, 6
        ret

Note that the intel compiler is currently making this:

div:
        movl      4(%esp), %edx                                 #3.5
        movl      %edx, %eax                                    #4.14
        sarl      $5, %eax                                      #4.14
        shrl      $26, %eax                                     #4.14
        addl      %edx, %eax                                    #4.14
        sarl      $6, %eax                                      #4.14
        ret                                                     #4.14

Which has one less register->register copy.  (hint hint alkis :)

llvm-svn: 13354
 2004-05-04 19:33:58 +00:00
Chris Lattner
cb9a614ea4 Improve code generated for integer multiplications by 2,3,5,9 
llvm-svn: 13342
 2004-05-04 15:47:14 +00:00
Chris Lattner
4b5d4eb5b1 Remove unused #include 
llvm-svn: 13304
 2004-05-01 21:29:16 +00:00
Chris Lattner
ffbf667718 Iterate over the Machine CFG that Brian added instead of the LLVM CFG. 
Look at all of the pretty minuses. :)

llvm-svn: 13303
 2004-05-01 21:27:53 +00:00
Brian Gaeke
bfb4fe5109 Make RequiresFPRegKill() take a MachineBasicBlock arg. 
In InsertFPRegKills(), just check the MachineBasicBlock for successors
instead of its corresponding BasicBlock.

llvm-svn: 13213
 2004-04-28 04:45:55 +00:00
Brian Gaeke
74ed24c9de In InsertFPRegKills(), use the machine-CFG itself rather than the 
LLVM CFG when trying to find the successors of BB.

llvm-svn: 13212
 2004-04-28 04:34:16 +00:00
Brian Gaeke
6c03805717 Update the machine-CFG edges whenever we see a branch. 
llvm-svn: 13211
 2004-04-28 04:19:37 +00:00
Brian Gaeke
0db103b4b3 Use emitWordAt() to emit forward-branch fixups. 
llvm-svn: 13120
 2004-04-23 17:11:16 +00:00
John Criswell
8a4525ae64 Remove code to adjust the iterator for llvm.readio and llvm.writeio. 
The iterator is pointing at the next instruction which should not disappear
when doing the load/store replacement.

llvm-svn: 12954
 2004-04-14 21:27:56 +00:00
Chris Lattner
64431dbce7 This is the real fix for Codegen/X86/2004-04-13-FPCMOV-Crash.llx which works 
even when the "optimization" I added before is turned off.  It generates this
extremely pointless code:

test:
        fld QWORD PTR [%ESP + 4]
        mov %AL, 0
        test %AL, %AL
        fcmove %ST(0), %ST(0)
        ret

Good thing the optimizer will have removed this before code generation
anyway.  :)

llvm-svn: 12939
 2004-04-14 02:42:32 +00:00
John Criswell
94de925685 Added support for the llvm.readio and llvm.writeio intrinsics. 
On x86, memory operations occur in-order, so these are just lowered into
volatile loads and stores.

llvm-svn: 12936
 2004-04-13 22:13:14 +00:00
Chris Lattner
2ba048528f Implement a small optimization, which papers over the problem in 
X86/2004-04-13-FPCMOV-Crash.llx

A more robust fix is to follow.

llvm-svn: 12935
 2004-04-13 21:56:09 +00:00
Chris Lattner
8b6bc380e3 Emit the immediate form of in/out when possible. 
Fix several bugs in the intrinsics:
  1. Make sure to copy the input registers before the instructions that use them
  2. Make sure to copy the value returned by 'in' out of EAX into the register
     it is supposed to be in.

This fixes assertions when using in/out and linear scan.

llvm-svn: 12896
 2004-04-13 17:20:37 +00:00
Chris Lattner
15ac62827e Add immediate forms of in/out. Use let to shorten lines 
llvm-svn: 12895
 2004-04-13 17:19:31 +00:00
Chris Lattner
ecbade26d5 Add support for new instruction type 
llvm-svn: 12894
 2004-04-13 17:18:51 +00:00
Chris Lattner
e8e60bf45f Add support for the printImplicitDefsBefore flag 
llvm-svn: 12893
 2004-04-13 17:18:39 +00:00
Chris Lattner
43f754339a Fix issues that the local allocator has dealing with instructions that implicitly use ST(0) 
llvm-svn: 12855
 2004-04-12 03:02:48 +00:00
Chris Lattner
9cdc472518 No really, fix printing for LLC. I gotta get a way for CVS to whine at me if 
I have unsaved emacs buffers, geeze...

llvm-svn: 12854
 2004-04-12 01:52:04 +00:00
Chris Lattner
f1d59be0e8 Correct printing for LLC and the encoding for the JIT 
llvm-svn: 12853
 2004-04-12 01:50:04 +00:00
Chris Lattner
682a6361c7 Use the fucomi[p] instructions to perform floating point comparisons instead 
of the fucom[p][p] instructions.  This allows us to code generate this function

bool %test(double %X, double %Y) {
        %C = setlt double %Y, %X
        ret bool %C
}

... into:

test:
        fld QWORD PTR [%ESP + 4]
        fld QWORD PTR [%ESP + 12]
        fucomip %ST(1)
        fstp %ST(0)
        setb %AL
        movsx %EAX, %AL
        ret

where before we generated:

test:
        fld QWORD PTR [%ESP + 4]
        fld QWORD PTR [%ESP + 12]
        fucompp
**      fnstsw
**      sahf
        setb %AL
        movsx %EAX, %AL
        ret

The two marked instructions (which are the ones eliminated) are very bad,
because they serialize execution of the processor.  These instructions are
available on the PPRO and later, but since we already use cmov's we aren't
losing any portability.

I retained the old code for the day when we decide we want to support back
to the 386.

llvm-svn: 12852
 2004-04-12 01:43:36 +00:00
Chris Lattner
c85d92e0b7 Add support for the FUCOMIr instruction 
llvm-svn: 12851
 2004-04-12 01:39:15 +00:00
Chris Lattner
cfb7144bf1 Add two new instructions 
llvm-svn: 12850
 2004-04-12 01:38:55 +00:00
Chris Lattner
de47ad3d6f Fix a bug in my load/cast folding patch. 
llvm-svn: 12849
 2004-04-12 00:23:04 +00:00
Chris Lattner
b3a10e244a Adjust some comments, fix a bug in my previous patch 
llvm-svn: 12848
 2004-04-12 00:12:04 +00:00
Chris Lattner
24f8b11206 On X86, casting an integer to floating point requires going through memory. 
If the source of the cast is a load, we can just use the source memory location,
without having to create a temporary stack slot entry.

Before we code generated this:

double %int(int* %P) {
        %V = load int* %P
        %V2 = cast int %V to double
        ret double %V2
}

into:

int:
        sub %ESP, 4
        mov %EAX, DWORD PTR [%ESP + 8]
        mov %EAX, DWORD PTR [%EAX]
        mov DWORD PTR [%ESP], %EAX
        fild DWORD PTR [%ESP]
        add %ESP, 4
        ret

Now we produce this:

int:
        mov %EAX, DWORD PTR [%ESP + 4]
        fild DWORD PTR [%EAX]
        ret

... which is nicer.

llvm-svn: 12846
 2004-04-11 23:21:26 +00:00
Chris Lattner
95cf3f8765 Implement folding of loads into floating point operations. This implements: 
test/Regression/CodeGen/X86/fp_load_fold.llx

llvm-svn: 12844
 2004-04-11 22:05:45 +00:00
Chris Lattner
b611f10e74 Unify all of the code for floating point +,-,*,/ into one function 
llvm-svn: 12842
 2004-04-11 21:23:56 +00:00
Chris Lattner
3378d71a55 This implements folding of constant operands into floating point operations 
for mul and div.

Instead of generating this:

test_divr:
        fld QWORD PTR [%ESP + 4]
        fld QWORD PTR [.CPItest_divr_0]
        fdivrp %ST(1)
        ret

We now generate this:

test_divr:
        fld QWORD PTR [%ESP + 4]
        fdivr QWORD PTR [.CPItest_divr_0]
        ret

This code desperately needs refactoring, which will come in the next
patch.

llvm-svn: 12841
 2004-04-11 21:09:14 +00:00
Chris Lattner
833d84f48a Restructure the mul/div/rem handling code to follow the pattern the other 
instructions use.  This doesn't change any functionality except that long
constant expressions of these operations will now magically start working.

llvm-svn: 12840
 2004-04-11 20:56:28 +00:00
Chris Lattner
69304a897c Codegen FP adds and subtracts with a constant more efficiently, generating: 
fld QWORD PTR [%ESP + 4]
        fadd QWORD PTR [.CPItest_add_0]

instead of:

        fld QWORD PTR [%ESP + 4]
        fld QWORD PTR [.CPItest_add_0]
        faddp %ST(1)

I also intend to do this for mul & div, but it appears that I have to
refactor a bit of code before I can do so.

This is tested by: test/Regression/CodeGen/X86/fp_constant_op.llx

llvm-svn: 12839
 2004-04-11 20:26:20 +00:00
Chris Lattner
dda382531e Add some new instructions 
llvm-svn: 12838
 2004-04-11 20:24:15 +00:00
Chris Lattner
a0681183b6 Relax assertion to make this function work with a broader class of instructions 
llvm-svn: 12836
 2004-04-11 20:21:06 +00:00
Chris Lattner
d22a1894a0 Two changes: 
1. If an incoming argument is dead, don't load it from the stack
  2. Do not code gen noop copies at all (ie, cast int -> uint), not even to
     a move.  This should reduce register pressure for allocators that are
     unable to coallesce away these copies in some cases.

llvm-svn: 12835
 2004-04-11 19:21:59 +00:00
Chris Lattner
8b1122d4dc Silence a spurious warning 
llvm-svn: 12815
 2004-04-10 18:32:01 +00:00
John Criswell
c9c191c41b Reversed the order of the llvm.writeport() operands so that the value 
is listed first and the address is listed second.

llvm-svn: 12795
 2004-04-09 19:09:14 +00:00
John Criswell
a52a2291d8 Changed assertions to error messages. 
llvm-svn: 12787
 2004-04-09 15:10:15 +00:00
John Criswell
8740c3767d Changes recommended by Chris: 
InstSelectSimple.cpp:
  Change the checks for proper I/O port address size into an exit() instead
  of an assertion.  Assertions aren't used in Release builds, and handling
  this error should be graceful (not that this counts as graceful, but it's
  more graceful).

  Modified the generation of the IN/OUT instructions to have 0 arguments.
X86InstrInfo.td:
  Added the OpSize attribute to the 16 bit IN and OUT instructions.

llvm-svn: 12786
 2004-04-08 22:39:13 +00:00
John Criswell
f6b16ea70b Added the llvm.readport and llvm.writeport intrinsics for x86. These do 
I/O port instructions on x86.  The specific code sequence is tailored to
the parameters and return value of the intrinsic call.
Added the ability for implicit defintions to be printed in the Instruction
Printer.
Added the ability for RawFrm instruction to print implict uses and
defintions with correct comma output.  This required adjustment to some
methods so that a leading comma would or would not be printed.

llvm-svn: 12782
 2004-04-08 20:31:47 +00:00
Jakub Staszak
fc0d9bb7e9 file based off InstSelectSimple.cpp, slowly being replaced by generated code from the really simple X86 instruction selector tablegen backend 
llvm-svn: 12715
 2004-04-06 19:35:17 +00:00
Jakub Staszak
06dc0add14 Tablgen files for really simple instruction selector 
llvm-svn: 12714
 2004-04-06 19:34:00 +00:00
Chris Lattner
3808778190 Fix PR313: [x86] JIT miscompiles unsigned short to floating point 
llvm-svn: 12711
 2004-04-06 19:29:36 +00:00
Chris Lattner
993d6106c7 Fix incorrect encoding of some ADC and SBB instuctions 
llvm-svn: 12710
 2004-04-06 19:20:32 +00:00
Chris Lattner
54e93df11a Fix a minor bug in previous checking 
Enable folding of long seteq/setne comparisons into branches and select instructions
Implement unfolded long relational comparisons against a constants a bit more efficiently

Folding comparisons changes code that looks like this:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %ECX, %EAX
        or %ECX, %EDX
        sete %CL
        test %CL, %CL
        je .LBB2 # PC rel: F

into code that looks like this:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %ECX, %EAX
        or %ECX, %EDX
        jne .LBB2 # PC rel: F

This speeds up 186.crafty by 6% with llc-ls.

llvm-svn: 12702
 2004-04-06 17:34:50 +00:00
Chris Lattner
2d9b28ac0b Improve codegen of long == and != comparisons against constants. Before, 
comparing a long against zero got us this:

        sub %ESP, 8
        mov DWORD PTR [%ESP + 4], %ESI
        mov DWORD PTR [%ESP], %EDI
        mov %EAX, DWORD PTR [%ESP + 12]
        mov %EDX, DWORD PTR [%ESP + 16]
        mov %ECX, 0
        mov %ESI, 0
        mov %EDI, %EAX
        xor %EDI, %ECX
        mov %ECX, %EDX
        xor %ECX, %ESI
        or %EDI, %ECX
        sete %CL
        test %CL, %CL
        je .LBB2 # PC rel: F

Now it gets us this:

        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %ECX, %EAX
        or %ECX, %EDX
        sete %CL
        test %CL, %CL
        je .LBB2 # PC rel: F

llvm-svn: 12696
 2004-04-06 16:02:27 +00:00
Chris Lattner
fd7b570dff Handle various other important cases of multiplying a long constant immediate. For 
example, multiplying X*(1 + (1LL << 32)) now produces:

test:
        mov %ECX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %EAX, %ECX
        add %EDX, %ECX
        ret

[[[Note to Alkis: why isn't linear scan generating this code??  This might be a
 problem with your intervals being too conservative:

test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        add %EDX, %EAX
        ret

end note]]]

Whereas GCC produces this:

T:
        sub     %esp, 12
        mov     %edx, DWORD PTR [%esp+16]
        mov     DWORD PTR [%esp+8], %edi
        mov     %ecx, DWORD PTR [%esp+20]
        xor     %edi, %edi
        mov     DWORD PTR [%esp], %ebx
        mov     %ebx, %edi
        mov     %eax, %edx
        mov     DWORD PTR [%esp+4], %esi
        add     %ebx, %edx
        mov     %edi, DWORD PTR [%esp+8]
        lea     %edx, [%ecx+%ebx]
        mov     %esi, DWORD PTR [%esp+4]
        mov     %ebx, DWORD PTR [%esp]
        add     %esp, 12
        ret

I'm not sure example what GCC is smoking here, but it looks like it has just
confused itself with a bunch of stack slots or something.  The intel compiler
is better, but still not good:

T:
        movl      4(%esp), %edx                                 #2.11
        movl      8(%esp), %eax                                 #2.11
        lea       (%eax,%edx), %ecx                             #3.12
        movl      $1, %eax                                      #3.12
        mull      %edx                                          #3.12
        addl      %ecx, %edx                                    #3.12
        ret                                                     #3.12

llvm-svn: 12693
 2004-04-06 04:55:43 +00:00
Chris Lattner
6038e5a4a1 Efficiently handle a long multiplication by a constant. For this testcase: 
long %test(long %X) {
        %Y = mul long %X, 123
        ret long %Y
}

we used to generate:

test:
        sub %ESP, 12
        mov DWORD PTR [%ESP + 8], %ESI
        mov DWORD PTR [%ESP + 4], %EDI
        mov DWORD PTR [%ESP], %EBX
        mov %ECX, DWORD PTR [%ESP + 16]
        mov %ESI, DWORD PTR [%ESP + 20]
        mov %EDI, 123
        mov %EBX, 0
        mov %EAX, %ECX
        mul %EDI
        imul %ESI, %EDI
        add %ESI, %EDX
        imul %ECX, %EBX
        add %ESI, %ECX
        mov %EDX, %ESI
        mov %EBX, DWORD PTR [%ESP]
        mov %EDI, DWORD PTR [%ESP + 4]
        mov %ESI, DWORD PTR [%ESP + 8]
        add %ESP, 12
        ret

Now we emit:
test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %EDX, 123
        mul %EDX
        imul %ECX, %ECX, 123
        add %ECX, %EDX
        mov %EDX, %ECX
        ret

Which, incidently, is substantially nicer than what GCC manages:
T:
        sub     %esp, 8
        mov     %eax, 123
        mov     DWORD PTR [%esp], %ebx
        mov     %ebx, DWORD PTR [%esp+16]
        mov     DWORD PTR [%esp+4], %esi
        mov     %esi, DWORD PTR [%esp+12]
        imul    %ecx, %ebx, 123
        mov     %ebx, DWORD PTR [%esp]
        mul     %esi
        mov     %esi, DWORD PTR [%esp+4]
        add     %esp, 8
        lea     %edx, [%ecx+%edx]
        ret

llvm-svn: 12692
 2004-04-06 04:29:36 +00:00
Chris Lattner
dd0d31ca2a Improve code generation of long shifts by 32. 
On this testcase:

long %test(long %X) {
        %Y = shr long %X, ubyte 32
        ret long %Y
}

instead of:
t:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EAX, DWORD PTR [%ESP + 8]
        sar %EAX, 0
        mov %EDX, 0
        ret


we now emit:
test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EAX, DWORD PTR [%ESP + 8]
        mov %EDX, 0
        ret

llvm-svn: 12688
 2004-04-06 03:42:38 +00:00
Chris Lattner
7eb61104dc Bugfixes: inc/dec don't set the carry flag! 
llvm-svn: 12687
 2004-04-06 03:36:57 +00:00
Chris Lattner
8cdbb1fe84 Improve code for passing constant longs as arguments to function calls. 
For example, on this instruction:

        call void %test(long 1234)

Instead of this:
        mov %EAX, 1234
        mov %ECX, 0
        mov DWORD PTR [%ESP], %EAX
        mov DWORD PTR [%ESP + 4], %ECX
        call test

We now emit this:
        mov DWORD PTR [%ESP], 1234
        mov DWORD PTR [%ESP + 4], 0
        call test

llvm-svn: 12686
 2004-04-06 03:23:00 +00:00
Chris Lattner
2738d6d4a4 Emit more efficient 64-bit operations when the RHS is a constant, and one 
of the words of the constant is zeros.  For example:
  Y = and long X, 1234

now generates:
  Yl = and Xl, 1234
  Yh = 0

instead of:
  Yl = and Xl, 1234
  Yh = and Xh, 0

llvm-svn: 12685
 2004-04-06 03:15:53 +00:00
Chris Lattner
bdbedf9523 Fix typeo 
llvm-svn: 12684
 2004-04-06 02:13:25 +00:00
Chris Lattner
606639ed1a Add support for simple immediate handling to long instruction selection. 
This allows us to handle code like 'add long %X, 123456789012' more efficiently.

llvm-svn: 12683
 2004-04-06 02:11:49 +00:00
Chris Lattner
e84f12a165 The sbb instructions really ARE sbb's, not adc's 
llvm-svn: 12682
 2004-04-06 02:02:11 +00:00
Chris Lattner
0808f5daa5 Implement negation of longs efficiently. For this testcase: 
long %test(long %X) {
        %Y = sub long 0, %X
        ret long %Y
}

We used to generate:

test:
        sub %ESP, 4
        mov DWORD PTR [%ESP], %ESI
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %ESI, DWORD PTR [%ESP + 12]
        mov %EAX, 0
        mov %EDX, 0
        sub %EAX, %ECX
        sbb %EDX, %ESI
        mov %ESI, DWORD PTR [%ESP]
        add %ESP, 4
        ret

Now we generate:

test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        neg %EAX
        adc %EDX, 0
        neg %EDX
        ret

llvm-svn: 12681
 2004-04-06 01:48:06 +00:00
Chris Lattner
56dcdcf638 Minor tweak to avoid an extra reg-reg copy that the register allocator has to eliminate 
llvm-svn: 12680
 2004-04-06 01:25:33 +00:00
Chris Lattner
42cf317fca Two changes: 
* In promote32, if we can just promote a constant value, do so instead of
    promoting a constant dynamically.
  * In visitReturn inst, actually USE the promote32 argument that takes a
    Value*

The end result of this is that we now generate this:

test:
        mov %EAX, 0
        ret

instead of...

test:
        mov %AX, 0
        movzx %EAX, %AX
        ret

for:

ushort %test() {
        ret ushort 0
}

llvm-svn: 12679
 2004-04-06 01:21:00 +00:00
Chris Lattner
9236135e8f Support getelementptr instructions which use uint's to index into structure 
types and can have arbitrary 32- and 64-bit integer types indexing into
sequential types.

llvm-svn: 12653
 2004-04-05 01:30:19 +00:00
Alkis Evlogimenos
27ed33c309 Clean up code a bit. 
llvm-svn: 12615
 2004-04-02 18:11:32 +00:00
Alkis Evlogimenos
85e007a6dc Fix type in comments 
llvm-svn: 12611
 2004-04-02 16:02:50 +00:00
Alkis Evlogimenos
84ee10f9e1 Fix type in instruction builder instantiation 
llvm-svn: 12610
 2004-04-02 15:51:03 +00:00
Alkis Evlogimenos
20b074682c Add more ADC and SBB variants 
llvm-svn: 12607
 2004-04-02 07:11:10 +00:00
Chris Lattner
b6e4e5a95e Simplify code by using the more powerful BuildMI forms. 
Implement a small optimization.  In test/Regression/CodeGen/X86/select.ll,
we now generate this for foldSel3:

foldSel3:
        mov %AL, BYTE PTR [%ESP + 4]
        fld DWORD PTR [%ESP + 8]
        fld DWORD PTR [%ESP + 12]
        mov %EAX, DWORD PTR [%ESP + 16]
        mov %ECX, DWORD PTR [%ESP + 20]
        cmp %EAX, %ECX
        fxch %ST(1)
        fcmovae %ST(0), %ST(1)
***     fstp %ST(1)
        ret

Instead of:

foldSel3:
        mov %AL, BYTE PTR [%ESP + 4]
        fld DWORD PTR [%ESP + 8]
        fld DWORD PTR [%ESP + 12]
        mov %EAX, DWORD PTR [%ESP + 16]
        mov %ECX, DWORD PTR [%ESP + 20]
        cmp %EAX, %ECX
        fxch %ST(1)
        fcmovae %ST(0), %ST(1)
***     fxch %ST(1)
***     fstp %ST(0)
        ret

In practice, this only effects code size: performance should be basically
unaffected.

llvm-svn: 12588
 2004-04-01 04:06:09 +00:00
Chris Lattner
78027ca4ff Wrap at 80 cols 
llvm-svn: 12587
 2004-04-01 04:03:27 +00:00
Chris Lattner
2e0755a058 Generate slightly smaller code, "test R, R" instead of "cmp R, 0" 
llvm-svn: 12579
 2004-03-31 22:22:36 +00:00
Chris Lattner
97e8b80649 The X86 backend no longer needs the select lowering pass. 
llvm-svn: 12578
 2004-03-31 22:03:46 +00:00
Chris Lattner
e5d60adc20 Codegen FP select instructions into X86 conditional moves. Annoyingly enough 
the X86 does not support a full set of fp cmove instructions, so we can't always
fold the condition into the select.  :(  Yuck.

llvm-svn: 12577
 2004-03-31 22:03:35 +00:00
Chris Lattner
d50df93168 Add support for floating point conditional move instructions 
llvm-svn: 12576
 2004-03-31 22:02:36 +00:00
Chris Lattner
4d543b4201 Add support for FP cmoves 
llvm-svn: 12575
 2004-03-31 22:02:21 +00:00
Chris Lattner
e4fa3010db Add FP conditional move instructions, which annoyingly have special properties 
that require the asmwriter to be extended (printing implicit uses before the
explicit operands)

llvm-svn: 12574
 2004-03-31 22:02:13 +00:00
Chris Lattner
f477746a61 Fold comparisons into select instructions, making much better code and 
using our broad selection of movcc instructions.  :)

llvm-svn: 12560
 2004-03-30 22:39:09 +00:00
Chris Lattner
6c1dd729d3 Implement spill code folding for all of the conditional move instructions 
llvm-svn: 12554
 2004-03-30 21:29:47 +00:00
Chris Lattner
ff016bd6fe Add direct support for integer select instructions, though we still don't support 
folding compares into the select yet.

llvm-svn: 12553
 2004-03-30 21:22:00 +00:00
Chris Lattner
57968a98df Fix some serious bugs in the cmov descriptions, which didn't cause a problem because 
we never generated them

Make indentation a bit more consistent

llvm-svn: 12549
 2004-03-30 20:18:02 +00:00
Chris Lattner
95942c021a Fix a fairly major performance problem. If a PHI node had a constant as 
an incoming value from a block, the selector would evaluate the constant
at the TOP of the block instead of at the end of the block.  This made the
live range for the constant span the entire block, increasing register
pressure needlessly.

llvm-svn: 12542
 2004-03-30 19:10:12 +00:00
Chris Lattner
87479998f2 Add the select lowering pass to get initial support for select instructions 
llvm-svn: 12541
 2004-03-30 18:41:59 +00:00
Chris Lattner
b8f179cb9b Malloc doesn't kill a load. This patch need not go into 1.2 though. 
llvm-svn: 12500
 2004-03-18 17:01:26 +00:00
Chris Lattner
ef7c1e9f7f Fix a really nasty bug that was breaking ijpeg in LLC mode. We were incorrectly 
folding load instructions into other instructions across free instruction
boundaries.  Perhaps this will also fix the other strange failures?

llvm-svn: 12494
 2004-03-18 06:29:54 +00:00
Alkis Evlogimenos
6ac147a7fb Add LAHF instruction 
llvm-svn: 12424
 2004-03-15 17:20:14 +00:00
Alkis Evlogimenos
2b94b048a9 Another API change to MRegisterInfo::foldMemoryOperand. Instead of a 
MachineBasicBlock::iterator take a MachineInstr*.

llvm-svn: 12392
 2004-03-14 20:14:27 +00:00
Alkis Evlogimenos
ff9482b664 Change MRegisterInfo::foldMemoryOperand to return the folded 
instruction to make the API more flexible.

llvm-svn: 12386
 2004-03-14 07:19:51 +00:00
Chris Lattner
b45245327e It helps if I save the file. :) 
llvm-svn: 12357
 2004-03-13 00:24:52 +00:00
Chris Lattner
f7bc6fd913 Rename the intrinsic enum values for llvm.va_* from Intrinsic::va_* to 
Intrinsic::va*.  This avoid conflicting with macros in the stdlib.h file.

llvm-svn: 12356
 2004-03-13 00:24:00 +00:00
Alkis Evlogimenos
da990ad8a4 Add support for a wider range of CMOV instructions. 
llvm-svn: 12336
 2004-03-12 17:59:56 +00:00
Misha Brukman
992e44e3c5 Fix compilation on Sparc: assert(0) => abort() 
llvm-svn: 12289
 2004-03-11 19:08:24 +00:00
Alkis Evlogimenos
a13672fd71 Check if printing of implicit uses is required for all types of shift 
instructions.

llvm-svn: 12258
 2004-03-09 06:10:15 +00:00
Alkis Evlogimenos
7c0224327e Differentiate between extended precision floats (80-bit) and double precision floats (64-bit) 
llvm-svn: 12254
 2004-03-09 03:37:54 +00:00
Alkis Evlogimenos
f86d2df13d Use newly added API to emit bytes for instructions that gas misassembles 
llvm-svn: 12253
 2004-03-09 03:35:34 +00:00
Alkis Evlogimenos
085957be0b Add emitInstruction() API so that we can get the bytes of a simple instruction 
llvm-svn: 12252
 2004-03-09 03:34:53 +00:00
Alkis Evlogimenos
813daf05c3 Constify things a bit 
llvm-svn: 12251
 2004-03-09 03:30:12 +00:00
Chris Lattner
a55628694a Implement folding explicit load instructions into binary operations. For a 
testcase like this:

int %test(int* %P, int %A) {
        %Pv = load int* %P
        %B = add int %A, %Pv
        ret int %B
}

We now generate:
test:
        mov %ECX, DWORD PTR [%ESP + 4]
        mov %EAX, DWORD PTR [%ESP + 8]
        add %EAX, DWORD PTR [%ECX]
        ret

Instead of:
test:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %EAX, DWORD PTR [%EAX]
        add %EAX, %ECX
        ret

... saving one instruction, and often a register.  Note that there are a lot
of other instructions that could use this, but they aren't handled.  I'm not
really interested in adding them, but mul/div and all of the FP instructions
could be supported as well if someone wanted to add them.

llvm-svn: 12204
 2004-03-08 01:58:35 +00:00
Chris Lattner
9a9b1c4822 Rearrange and refactor some code. No functionality changes. 
llvm-svn: 12203
 2004-03-08 01:18:36 +00:00
Alkis Evlogimenos
65649a50e9 Add memory operand version of conditional move. 
llvm-svn: 12190
 2004-03-07 03:19:11 +00:00
Brian Gaeke
0b913593ae make -print-machineinstrs work for both SparcV9 and X86 
llvm-svn: 12122
 2004-03-04 19:16:23 +00:00
Alkis Evlogimenos
e8ebdcc780 Add assertion for scale verification. 
llvm-svn: 12120
 2004-03-04 18:05:02 +00:00
Misha Brukman
491ff34abf Doxygenify some comments. 
llvm-svn: 12064
 2004-03-01 23:53:11 +00:00
Brian Gaeke
b78f8498f0 TargetCacheInfo has been removed; its only uses were to propagate a constant 
(16) into certain areas of the SPARC V9 back-end. I'm fairly sure the US IIIi's
dcache has 32-byte lines, so I'm not sure where the 16 came from. However, in
the interest of not breaking things any more than they already are, I'm going
to leave the constant alone.

llvm-svn: 12043
 2004-03-01 06:43:29 +00:00
Chris Lattner
8c1d67b55f Handle passing constant integers to functions much more efficiently. Instead 
of generating this code:

        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        call Y

we now generate:
        mov DWORD PTR [%ESP], 4
        mov DWORD PTR [%ESP + 4], 123
        call Y

Which hurts the eyes less.  :)

Considering that register pressure around call sites is already high (with all
of the callee clobber registers n stuff), this may help a lot.

llvm-svn: 12028
 2004-03-01 02:42:43 +00:00
Chris Lattner
c686a9ab37 Fix a minor code-quality issue. When passing 8 and 16-bit integer constants 
to function calls, we would emit dead code, like this:

int Y(int, short, double);
int X() {
  Y(4, 123, 4);
}

--- Old
X:
        sub %ESP, 20
        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
***     mov %AX, 123
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        fld QWORD PTR [.CPIX_0]
        fstp QWORD PTR [%ESP + 8]
        call Y
        mov %EAX, 0
        # IMPLICIT_USE %EAX %ESP
        add %ESP, 20
        ret

Now we emit:
X:
        sub %ESP, 20
        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        fld QWORD PTR [.CPIX_0]
        fstp QWORD PTR [%ESP + 8]
        call Y
        mov %EAX, 0
        # IMPLICIT_USE %EAX %ESP
        add %ESP, 20
        ret

Next up, eliminate the mov AX and movsx entirely!

llvm-svn: 12026
 2004-03-01 02:34:08 +00:00
Alkis Evlogimenos
e186d8eb2f Add instruction name description. 
llvm-svn: 11998
 2004-02-29 18:44:03 +00:00
Alkis Evlogimenos
8d8f872b3d Use correct template for SHLD and SHRD instructions so that the memory 
operand size is correctly specified.

llvm-svn: 11997
 2004-02-29 09:19:40 +00:00
Alkis Evlogimenos
10f4523e9a Improve allocation order: 
1) For 8-bit registers try to use first the ones that are parts of the
   same register (AL then AH). This way we only alias 2 16/32-bit
   registers after allocating 4 8-bit variables.

2) Move EBX as the last register to allocate. This will cause less
   spills to happen since we will have 8-bit registers available up to
   register excaustion (assuming we use the allocation order). It
   would be nice if we could push all of the 8-bit aliased registers
   towards the end but we much prefer to keep callee saved register to
   the end to avoid saving them on entry and exit of the function.

For example this gives a slight reduction of spills with linear scan
on 164.gzip.

Before:

11221 asm-printer           - Number of machine instrs printed
  975 spiller               - Number of loads added
  675 spiller               - Number of stores added
  398 spiller               - Number of register spills

After:

11182 asm-printer           - Number of machine instrs printed
  952 spiller               - Number of loads added
  652 spiller               - Number of stores added
  386 spiller               - Number of register spills

llvm-svn: 11996
 2004-02-29 09:17:01 +00:00
Alkis Evlogimenos
7ecfe0a839 A big X86 instruction rename. The instructions are renamed to make 
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:

ADD8rr -> add, 8-bit register, 8-bit register

IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate

IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate

MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory

llvm-svn: 11995
 2004-02-29 08:50:03 +00:00
Chris Lattner
a7db4ff17a Eliminate the X86-specific BMI functions, using BuildMI instead. 
Replace uses of addZImm with addImm.

llvm-svn: 11992
 2004-02-29 07:22:16 +00:00
Chris Lattner
e8e0bafbba Fix a miscompilation of 197.parser that occurs when you have single basic 
block loops.

llvm-svn: 11990
 2004-02-29 07:10:16 +00:00
Chris Lattner
c2977ac665 Adjust to change in TII ctor arguments 
llvm-svn: 11987
 2004-02-29 06:31:44 +00:00
Chris Lattner
cfc8f02250 These two virtual methods are never called. 
llvm-svn: 11984
 2004-02-29 05:59:33 +00:00
Alkis Evlogimenos
0f96b44e0e Use correct template for ADC instruction with memory operands. 
llvm-svn: 11974
 2004-02-29 02:18:17 +00:00
Alkis Evlogimenos
6815402082 SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename them 
to denote this fact.

llvm-svn: 11972
 2004-02-28 23:46:44 +00:00
Alkis Evlogimenos
e8dac99a43 Floating point loads/stores act on memory operands. Rename them to 
denote this fact.

llvm-svn: 11971
 2004-02-28 23:42:35 +00:00
Alkis Evlogimenos
1d71a15be9 Rename instruction templates to be easier to the human eye to 
parse. The name is now I (operand size)*. For example:

Im32 -> instruction with 32-bit memory operands.

Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate
          operands.

llvm-svn: 11970
 2004-02-28 23:09:03 +00:00
Alkis Evlogimenos
6038a89025 Uncomment instructions that take both an immediate and a memory 
operand but their sizes differ.

llvm-svn: 11969
 2004-02-28 22:06:59 +00:00
Alkis Evlogimenos
f208a0fd81 Each instruction now has both an ImmType and a MemType. This describes 
the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).

llvm-svn: 11967
 2004-02-28 22:02:05 +00:00
Alkis Evlogimenos
977dbaadf7 Do not generate instructions with mismatched memory/immediate sized 
operands. The X86 backend doesn't handle them properly right now.

llvm-svn: 11944
 2004-02-28 06:01:43 +00:00
Alkis Evlogimenos
84f00e93f7 Further comment updates. 
llvm-svn: 11933
 2004-02-28 03:20:31 +00:00
Alkis Evlogimenos
edbe362160 Update comments. 
llvm-svn: 11932
 2004-02-28 03:12:31 +00:00
Alkis Evlogimenos
0f91ce52a0 My previous commit broke the jit. The shift instructions always take 
an 8-bit immediate. So mark the shifts that take immediates as taking
an 8-bit argument. The rest with the implicit use of CL are marked
appropriately.

A bug still exists:

def SHLDmri32  : I2A8 <"shld", 0xA4, MRMDestMem>, TB;           // [mem32] <<= [mem32],R32 imm8

The immediate in the above instruction is 8-bit but the memory
reference is 32-bit. The printer prints this as an 8-bit reference
which confuses the assembler. Same with SHRDmri32.

llvm-svn: 11931
 2004-02-28 02:56:26 +00:00
Alkis Evlogimenos
ace6d81654 Fix argument size for SHL, SHR, SAR, SHLD and SHRD families of 
instructions.

llvm-svn: 11923
 2004-02-27 19:46:30 +00:00