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Commit Graph

4315 Commits

Author SHA1 Message Date
Rafael Espindola
12643c4bec Remove anonymous namespace.
Looks like the gcc in http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32/ doesn't like "not external linkage":

/Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h: In instantiation of 'const bool llvm::yaml::has_SequenceMethodTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::value':
/Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h:281:   instantiated from 'llvm::yaml::has_SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >'
/Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/utils/yaml2obj/yaml2obj.cpp:627:   instantiated from here
/Volumes/Macintosh_HD2/buildbots/clang-x86_64-darwin11-self-mingw32/llvm.src/include/llvm/Support/YAMLTraits.h:243: error: 'llvm::yaml::SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::size' is not a valid template argument for type 'size_t (*)(llvm::yaml::IO&, std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> >&)' because function 'static size_t llvm::yaml::SequenceTraits<std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> > >::size(llvm::yaml::IO&, std::vector<<unnamed>::COFFYAML::Relocation, std::allocator<<unnamed>::COFFYAML::Relocation> >&)' has not external linkage

llvm-svn: 178600
2013-04-03 01:07:53 +00:00
Rafael Espindola
44e98eeac2 Use yaml::IO in yaml2obj.cpp.
The generic structs and specializations will be refactored when obj2yaml is
changed to use yaml::IO.

llvm-svn: 178593
2013-04-02 23:56:40 +00:00
Andrew Trick
4e1ed3a6dc Fix TableGen subtarget-emitter to handle A9/Swift.
A9 uses itinerary classes, Swift uses RW lists. This tripped some
verification when we're expanding variants. I had to refine the
verification a bit.

llvm-svn: 178357
2013-03-29 19:08:31 +00:00
Dan Gohman
333b99112b Revert r178166. According to Howard, this code is actually ok.
llvm-svn: 178319
2013-03-29 00:13:08 +00:00
Dan Gohman
9f0372854d Avoid undefined behavior from passing a std::vector's own contents
in as an argument to push_back.

llvm-svn: 178166
2013-03-27 18:44:56 +00:00
Andrew Trick
19f83ecc6b TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.
Allow variants to be defined only for some processors on a target.

llvm-svn: 178074
2013-03-26 21:36:39 +00:00
Dave Zarzycki
2949721b7d x86 -- add the XTEST instruction
llvm-svn: 177888
2013-03-25 18:59:43 +00:00
Jakob Stoklund Olesen
b8c553e610 Allow types to be omitted in output patterns.
This syntax is now preferred:

  def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;

There is no reason to repeat the types in the output pattern.

llvm-svn: 177844
2013-03-24 19:37:00 +00:00
Jakob Stoklund Olesen
2b502e642b Allow direct value types to be used in instruction 'set' patterns.
This makes it possible to define instruction patterns like this:

def LDri : F3_2<3, 0b000000,
                (outs IntRegs:$dst), (ins MEMri:$addr),
                "ld [$addr], $dst",
                [(set i32:$dst, (load ADDRri:$addr))]>;
                      ~~~

llvm-svn: 177834
2013-03-24 00:56:16 +00:00
Jakob Stoklund Olesen
332c7f8ecf Allow direct value types in pattern definitions.
Just like register classes, value types can be used in two ways in
patterns:

  (sext_inreg i32:$src, i16)

In a named leaf node like i32:$src, the value type simply provides the
type of the node directly. This simplifies type inference a lot compared
to the current practice of specifiying types indirectly with register
classes.

As an unnamed leaf node, like i16 above, the value type represents
itself as an MVT::Other immediate.

llvm-svn: 177828
2013-03-23 20:35:01 +00:00
Jakob Stoklund Olesen
a8e8e879c0 Make all unnamed RegisterClass TreePatternNodes typed MVT::i32.
A register class can appear as a leaf TreePatternNode with and without a
name:

  (COPY_TO_REGCLASS GPR:$src, F8RC)

In a named leaf node like GPR:$src, the register class provides type
information for the named variable represented by the node. The TypeSet
for such a node is the set of value types that the register class can
represent.

In an unnamed leaf node like F8RC above, the register class represents
itself as a kind of immediate. Such a node has the type MVT::i32,
we'll never create a virtual register representing it.

This change makes it possible to remove the special handling of
COPY_TO_REGCLASS in CodeGenDAGPatterns.cpp.

llvm-svn: 177825
2013-03-23 18:08:44 +00:00
Benjamin Kramer
2d6ca3aea4 Plug a memory leak in FileCheck when the input file is empty.
llvm-svn: 177822
2013-03-23 13:56:23 +00:00
Sean Silva
b2ca5c4ca4 Add TableGen ctags(1) emitter and helper script.
To use this in conjunction with exuberant ctags to generate a single
combined tags file, run tblgen first and then
  $ ctags --append [...]

Since some identifiers have corresponding definitions in C++ code,
it can be useful (if using vim) to also use cscope, and
  :set cscopetagorder=1
so that
  :tag X
will preferentially select the tablegen symbol, while
  :cscope find g X
will always find the C++ symbol.

Patch by Kevin Schoedel!

(a couple small formatting changes courtesy of clang-format)

llvm-svn: 177682
2013-03-21 23:40:38 +00:00
Reid Kleckner
804b51ca54 [lit] Avoid CRLFs in bash scripts on Windows
Native Windows Python will do line ending translation by default, which
we don't want in bash scripts.  If we're not native Windows Python, then
'b' is ignored.

llvm-svn: 177602
2013-03-20 23:32:14 +00:00
Ulrich Weigand
6cee29625a Extend TableGen instruction selection matcher to improve handling
of complex instruction operands (e.g. address modes).

Currently, if a Pat pattern creates an instruction that has a complex
operand (i.e. one that consists of multiple sub-operands at the MI
level), this operand must match a ComplexPattern DAG pattern with the
correct number of output operands.

This commit extends TableGen to alternatively allow match a complex
operands against multiple separate operands at the DAG level.

This allows using Pat patterns to match pre-increment nodes like
pre_store (which must have separate operands at the DAG level) onto
an instruction pattern that uses a multi-operand memory operand,
like the following example on PowerPC (will be committed as a
follow-on patch):

  def STWU  : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst),
                    "stwu $rS, $dst", LdStStoreUpd, []>,
                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;

  def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff),
            (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>;

Here, the pair of "ptroff" and "ptrreg" operands is matched onto the
complex operand "dst" of class "memri" in the "STWU" instruction.

Approved by Jakob Stoklund Olesen.

llvm-svn: 177428
2013-03-19 19:51:09 +00:00
Andrew Trick
ee650f250f TableGen fix for the new machine model.
Properly handle cases where a group of instructions have different
SchedRW lists with the same itinerary class.
This was supposed to work, but I left in an early break.

llvm-svn: 177317
2013-03-18 20:42:25 +00:00
Jakob Stoklund Olesen
9bba6f749a Extract a method.
This computes the type of an instruction operand or result based on the
records in the instruction's ins and outs lists.

llvm-svn: 177244
2013-03-18 04:08:07 +00:00
Jakob Stoklund Olesen
b984ca6d18 Use ArrayRef<MVT::SimpleValueType> when possible.
Not passing vector references around makes it possible to use
SmallVector in most places.

llvm-svn: 177235
2013-03-17 17:26:09 +00:00
Andrew Trick
d9ea1ed5c1 Machine model. Allow mixed itinerary classes and SchedRW lists.
We always supported a mixture of the old itinerary model and new
per-operand model, but it required a level of indirection to map
itinerary classes to SchedRW lists. This was done for ARM A9.

Now we want to define x86 SchedRW lists, with the goal of removing its
itinerary classes, but still support the itineraries in the mean
time. When I original developed the model, Atom did not have
itineraries, so there was no reason to expect this requirement.

llvm-svn: 177226
2013-03-16 18:58:55 +00:00
Jakob Stoklund Olesen
46174e4527 Add SchedRW as an Instruction field.
Don't require instructions to inherit Sched<...>. Sometimes it is more
convenient to say:

  let SchedRW = ... in {
    ...
  }

Which is now possible.

llvm-svn: 177199
2013-03-15 22:51:13 +00:00
Andrew Trick
aab9978611 Fix r177112: Add ProcResGroup.
This is the other half of r177122 that I meant to commit at the same time.

llvm-svn: 177123
2013-03-14 22:47:01 +00:00
Andrew Trick
d133b52150 MachineModel: Add a ProcResGroup class.
This allows abitrary groups of processor resources. Using something in
a subset automatically counts againts the superset. Currently, this
only works if the superset is also a ProcResGroup as opposed to a
SuperUnit.

This allows SandyBridge to be expressed naturally, which will be
checked in shortly.

def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>;
def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
def SBPort23  : ProcResGroup<[SBPort2, SBPort3]>;
def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;

llvm-svn: 177112
2013-03-14 21:21:50 +00:00
NAKAMURA Takumi
7822c4abc1 lit.TestFormats.GoogleTest: Honor LitConfig.noExecute, or --no-execute were ignored.
llvm-svn: 176930
2013-03-13 06:16:33 +00:00
Kevin Enderby
319d315d55 Fixes disassembler crashes on 2013 Haswell RTM instructions.
rdar://13318048

llvm-svn: 176828
2013-03-11 21:17:13 +00:00
Andrew Trick
ab2046b460 MIsched machine model: tablegen subtarget emitter improvement.
Fix the way resources are counted. I'm taking some time to cleanup the
way MachineScheduler handles in-order machine resources. Eventually
we'll need more PPC/Atom test cases in tree.

llvm-svn: 176390
2013-03-01 23:31:26 +00:00
Bill Wendling
b16f9837ef Enable syntax highlighting for reStructuredText files.
Patch by Journeyer J. Joh!

llvm-svn: 176235
2013-02-28 06:43:24 +00:00
Michael J. Spencer
1f361eb77c [TableGen] Fix ICE on MSVC 2012 Release builds.
llvm-svn: 176125
2013-02-26 21:29:47 +00:00
Kostya Serebryany
f560b78692 Unify clang/llvm attributes for asan/tsan/msan (LLVM part)
These are two related changes (one in llvm, one in clang).
LLVM: 
- rename address_safety => sanitize_address (the enum value is the same, so we preserve binary compatibility with old bitcode)
- rename thread_safety => sanitize_thread
- rename no_uninitialized_checks -> sanitize_memory

CLANG: 
- add __attribute__((no_sanitize_address)) as a synonym for __attribute__((no_address_safety_analysis))
- add __attribute__((no_sanitize_thread))
- add __attribute__((no_sanitize_memory))

for S in address thread memory
If -fsanitize=S is present and __attribute__((no_sanitize_S)) is not
set llvm attribute sanitize_S

llvm-svn: 176075
2013-02-26 06:58:09 +00:00
Matt Beaumont-Gay
c6ce965ace 'Hexadecimal' has two 'a's and only one 'i'.
llvm-svn: 176031
2013-02-25 18:11:18 +00:00
Jyotsna Verma
37dad03d5b Fix for bug 15246 -- out-of-bound error in the TableGen backend, CodeGenMapTable.cpp.
llvm-svn: 175185
2013-02-14 17:58:13 +00:00
David Peixotto
0a3102166e PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA
Fixed bug in tablegen conversion when source pseudo instruction has
a different number of arguments than the destination instruction.

llvm-svn: 175066
2013-02-13 19:21:47 +00:00
Guy Benyei
92dac48079 Add static cast to unsigned char whenever a character classification function is called with a signed char argument, in order to avoid assertions in Windows Debug configuration.
llvm-svn: 175006
2013-02-12 21:21:59 +00:00
Kay Tiong Khoo
d299c572f3 Added 0x0D to 2-byte opcode extension table for prefetch* variants
Fixed decode of existing 3dNow prefetchw instruction
Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs

llvm-svn: 174920
2013-02-12 00:19:12 +00:00
Kostya Serebryany
8e2f1fbfb7 [tsan/msan] adding thread_safety and uninitialized_checks attributes
llvm-svn: 174864
2013-02-11 08:13:54 +00:00
Daniel Dunbar
87a628ad87 [lit] Add a display function for lit.Test.TestResult.
llvm-svn: 174667
2013-02-07 21:34:34 +00:00
Guy Benyei
e5a7b5054c Canonicalize line endings to Linux style also when the --strict-whitespace flag is in use. This flag is supposed to affect horizontal whitespaces only.
llvm-svn: 174541
2013-02-06 20:40:38 +00:00
Jim Grosbach
6f7278da17 Allow targets to add custom asm operand matching logic.
For example, ARM has several instructions with a literal '#0' immediate in the syntax
that's not represented as an actual operand. The asm matcher is expected a token
operand, but the parser will have created an immediate operand. This is currently
handled by dedicated per-instruction C++ munging of the ParsedAsmOperand list, but
will be better handled by this hook.

llvm-svn: 174487
2013-02-06 06:00:06 +00:00
Bob Wilson
0c5819e04c Preprocess Apple llvmCore headers to reflect NDEBUG setting. <rdar://12568983>
If an Apple llvmCore build is done without assertions, and a client uses
the llvmCore headers with assertions enabled, or vice versa, then things will
break because some of the structure sizes in the API are different.  Use the
unifdef tool to make the headers unconditionally match the way the llvmCore
libraries were built.

llvm-svn: 174460
2013-02-05 22:59:42 +00:00
Bob Wilson
388e081f6a Set the deployment target for Apple llvmCore builds. <rdar://problem/12712431>
llvm-svn: 174397
2013-02-05 17:29:03 +00:00
Eli Bendersky
89664e61b6 Fix comments
llvm-svn: 174390
2013-02-05 16:53:11 +00:00
Jack Carter
3dfa61ae2c This patch that sets the EmitAlias flag in td files
and enables the instruction printer to print aliased 
instructions. 

Due to usage of RegisterOperands a change in common 
code (utils/TableGen/AsmWriterEmitter.cpp) is required 
to get the correct register value if it is a RegisterOperand.

Contributer: Vladimir Medic
 
llvm-svn: 174358
2013-02-05 08:32:10 +00:00
Andrew Trick
2969f0d0aa MachineModel: Inconsequential TableGen SubtargetEmitter fix.
Drive by fix. I noticed some missing logic that might bite future
users. This shouldn't affect the final output on currently modeled
targets.

llvm-svn: 174142
2013-02-01 03:19:54 +00:00
Daniel Dunbar
c1a371e4ba [lit] Add a test for internal shell execution behaviors.
llvm-svn: 174102
2013-01-31 22:15:20 +00:00
Daniel Dunbar
bc2e9247e5 [lit] Change to raise InternalShellError for all command execution issues.
llvm-svn: 174101
2013-01-31 22:15:15 +00:00
Daniel Dunbar
f0b8d0bee5 [lit] Fix bug where InternalShellError messages were discarded.
- Also, change the exit code to match 'sh'.

llvm-svn: 174089
2013-01-31 20:58:16 +00:00
Daniel Dunbar
9974bc4dd7 [lit] Fix a shell parsing bug with ';' not separated by whitespace.
- Testing finds bugs, who knew.

llvm-svn: 174087
2013-01-31 20:51:17 +00:00
Daniel Dunbar
b1cf0346bf [lit] Add a test for the various ShTest format features.
llvm-svn: 174072
2013-01-31 18:05:01 +00:00
Daniel Dunbar
6da49ae5e5 [lit] TestRunner: Eliminate failDueToStderr argument, which is now unused.
llvm-svn: 174071
2013-01-31 18:04:45 +00:00
Daniel Dunbar
68b35e0a6d [lit] Delete the now-unused SyntaxCheckTest format.
- Also, kill the pointless LitFormats module.

llvm-svn: 174070
2013-01-31 18:04:38 +00:00
Jakob Stoklund Olesen
71dc1e3b47 Clarify intent.
llvm-svn: 174068
2013-01-31 17:56:23 +00:00