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Commit Graph

82362 Commits

Author SHA1 Message Date
Evan Cheng
9a33fc17be Avoid creating a cycle when folding load / op with flag / store. PR11451474. rdar://11451474
llvm-svn: 156896
2012-05-16 01:54:27 +00:00
John Criswell
f5812a8109 Fixed grammar for the llvm.trap intrinsic description.
llvm-svn: 156881
2012-05-16 00:26:51 +00:00
Jakob Stoklund Olesen
1da786c936 Enable sub-sub-register copy coalescing.
It is now possible to coalesce weird skewed sub-register copies by
picking a super-register class larger than both original registers. The
included test case produces code like this:

  vld2.32 {d16, d17, d18, d19}, [r0]!
  vst2.32 {d18, d19, d20, d21}, [r0]

We still perform interference checking as if it were a normal full copy
join, so this is still quite conservative. In particular, the f1 and f2
functions in the included test case still have remaining copies because
of false interference.

llvm-svn: 156878
2012-05-15 23:31:35 +00:00
Jakob Stoklund Olesen
d9e5addfc0 Teach RegisterCoalescer to handle symmetric sub-register copies.
It is possible to coalesce two overlapping registers to a common
super-register that it larger than both of the original registers.

The important difference is that it may be necessary to rewrite DstReg
operands as well as SrcReg operands because the sub-register index has
changed.

This behavior is still disabled by CoalescerPair.

llvm-svn: 156869
2012-05-15 22:26:28 +00:00
Jakob Stoklund Olesen
0e3b11196f Handle NewReg==OldReg in renameRegister().
This can happen when widening a virtual register to a super-register
class.

llvm-svn: 156867
2012-05-15 22:20:27 +00:00
Jakob Stoklund Olesen
109ee15f5d We never call adjustCopiesBackFrom() for partial copies.
There is no need to look at an always null SrcIdx.

llvm-svn: 156866
2012-05-15 22:18:49 +00:00
Daniel Dunbar
e481053e50 llvm-config: Use sys::fs::equivalent instead of string comparison.
- Hopefully fixes PR11600 (untested).

llvm-svn: 156865
2012-05-15 22:07:18 +00:00
Daniel Dunbar
35f13a8fee [Support] Add a version of sys::fs::equivalent() that treats errors as false.
llvm-svn: 156864
2012-05-15 22:07:14 +00:00
Daniel Dunbar
9eca628bf1 [docs] Remove unsupported references to ExtraSource variable.
llvm-svn: 156857
2012-05-15 21:32:27 +00:00
Bill Wendling
43288a8cba Add blurb for Crack.
llvm-svn: 156852
2012-05-15 20:47:23 +00:00
Kevin Enderby
8feefef6ff Add a test case for r156840, a fix to llvm-objdump when disassembling using
-macho to disassemble the last symbol to the end of the section.

llvm-svn: 156850
2012-05-15 20:20:50 +00:00
Nuno Lopes
40c48e0924 reuse the result of some expensive computations in getSignExtendExpr() and getZeroExtendExpr()
this gives a speedup of > 80 in a debug build in the test case of PR12825 (php_sha512_crypt_r)

llvm-svn: 156849
2012-05-15 20:20:14 +00:00
Jakob Stoklund Olesen
032842545f Extend the CoalescerPair interface to handle symmetric sub-register copies.
Now both SrcReg and DstReg can be sub-registers of the final coalesced
register.

CoalescerPair::setRegisters still rejects such copies because
RegisterCoalescer doesn't yet handle them.

llvm-svn: 156848
2012-05-15 20:09:43 +00:00
Akira Hatanaka
2938a5c491 Update MIPS' section in the release notes. Patch by Simon Atanasyan.
llvm-svn: 156847
2012-05-15 20:06:41 +00:00
Andrew Trick
2bc63e3ee1 Add -enable-aa-sched-mi, off by default, for AliasAnalysis inside MachineScheduler.
This feature avoids creating edges in the scheduler's dependence graph
for non-aliasing memory operations according to whichever alias
analysis is available. It has been fully tested in Hexagon. Before
making this default, it needs to be extended to handle multiple
MachineMemOperands, compile time needs more evaluation, and
benchmarking on X86 and ARM is needed.

Patch by Sergei Larin!

llvm-svn: 156842
2012-05-15 18:59:41 +00:00
Kevin Enderby
a1272a1de8 Fixed a bug in llvm-objdump when disassembling using -macho option for a binary
that has more than one symbol.  The last symbol was not being disassembled to
the end of the section.

llvm-svn: 156840
2012-05-15 18:57:14 +00:00
Daniel Dunbar
64c706d674 llvm-build: Add support for non-installed libraries (e.g., gtest).
- These libraries are only reported by llvm-config when run from a development
   tree.

llvm-svn: 156838
2012-05-15 18:44:17 +00:00
Daniel Dunbar
9fa09aa92b llvm-build: Don't emit library information for disabled targets.
llvm-svn: 156837
2012-05-15 18:44:12 +00:00
Daniel Dunbar
551d4ff482 [utils] Fix Get{RepositoryPath,SourceVersion} to have a more robust is-git-svn
check.

llvm-svn: 156836
2012-05-15 18:44:09 +00:00
Jim Grosbach
8f241263d7 TableGen'erate mapping physical registers to encoding values.
Many targets always use the same bitwise encoding value for physical
registers in all (or most) instructions. Add this mapping to the
.td files and TableGen'erate the information and expose an accessor
in MCRegisterInfo.

patch by Tom Stellard.

llvm-svn: 156829
2012-05-15 17:35:57 +00:00
Jim Grosbach
2e62e2f664 Allow MCCodeEmitter access to the target MCRegisterInfo.
Add the MCRegisterInfo to the factories and constructors.

Patch by Tom Stellard <Tom.Stellard@amd.com>.

llvm-svn: 156828
2012-05-15 17:35:52 +00:00
Sirish Pande
7081e43d5c Enable all Hexagon tests.
llvm-svn: 156824
2012-05-15 16:13:12 +00:00
Nuno Lopes
9cdc8c5146 minor simplification to code: Ty is already a SCEV type; don't need to run getEffectiveSCEVType() twice
llvm-svn: 156823
2012-05-15 15:44:38 +00:00
David Chisnall
be2ca80057 Add some release notes about compiler-rt and libc++
llvm-svn: 156819
2012-05-15 13:06:46 +00:00
David Majnemer
ea3e1ea334 Teach SimplifyLibCalls about stpcpy.
llvm-svn: 156815
2012-05-15 11:46:21 +00:00
Bill Wendling
18c55548e9 Remove warning about testing unsigned int with int.
llvm-svn: 156812
2012-05-15 09:59:13 +00:00
Stepan Dyatkovskiy
6d83dd3cf8 Fixed one small stupid, but critical bug.
llvm-svn: 156810
2012-05-15 09:21:39 +00:00
Stepan Dyatkovskiy
f0f42687c6 Rejected r156804 due to buildbots failures.
llvm-svn: 156808
2012-05-15 06:50:18 +00:00
Stepan Dyatkovskiy
8f3e310361 SelectionDAGBuilder::Clusterify : main functinality was replaced with CRSBuilder::optimize, so big part of Clusterify's code was reduced.
llvm-svn: 156804
2012-05-15 05:09:41 +00:00
Akira Hatanaka
01faea9193 Temporarily disable anti-dependence breaking for Mips until bug 12829 is
resolved.

llvm-svn: 156801
2012-05-15 03:14:52 +00:00
Jakob Stoklund Olesen
c52390cafe Create a struct representing register units in TableGen.
Besides the weight, we also want to store up to two root registers per
unit. Most units will have a single root, the leaf register they
represent. Units created for ad hoc aliasing get two roots: The two
aliasing registers.

The root registers can be used to compute the set of overlapping
registers.

llvm-svn: 156792
2012-05-15 00:50:23 +00:00
Bill Wendling
36335d9da3 Remove extraneous ';'.
llvm-svn: 156791
2012-05-15 00:41:56 +00:00
Akira Hatanaka
6652e4ae4b Add a command line option to skip the delay slot filler pass entirely for Mips.
The purpose of this option is to silence error messages issued by machine
verifier passes and enable them to run to the end. If this option is not
provided, -verify-machineinstrs complains when it discovers there is a
non-terminator instruction (an instruction that is in a delay slot) after the
first terminator in a basic block.

llvm-svn: 156790
2012-05-14 23:59:17 +00:00
Michael J. Spencer
d6a42acd4e [Support/YAMLParser] Use rtrim on plain scalars.
llvm-svn: 156787
2012-05-14 22:43:34 +00:00
Michael J. Spencer
5a53bd3002 [Support/COFF] Make the order of members in symbol match the standard.
llvm-svn: 156785
2012-05-14 22:43:21 +00:00
David Blaikie
434a602438 Fix use of uninitialized variable.
Found by GCC's maybe-uninitialized.

llvm-svn: 156780
2012-05-14 21:48:19 +00:00
Jakob Stoklund Olesen
a78f184a30 Don't access MO reference after invalidating operand list.
This should unbreak llvm-x86_64-linux.

llvm-svn: 156778
2012-05-14 21:30:58 +00:00
Jakob Stoklund Olesen
a3e3afc746 Fix PR12821.
RAFast must add an <imp-def> operand when it is rewriting a sub-register
def that isn't a read-modify-write.

llvm-svn: 156777
2012-05-14 21:10:25 +00:00
Chad Rosier
c3a90c47b9 Move the capture analysis from MemoryDependencyAnalysis to a more general place
so that it can be reused in MemCpyOptimizer.  This analysis is needed to remove
an unnecessary memcpy when returning a struct into a local variable.
rdar://11341081
PR12686

llvm-svn: 156776
2012-05-14 20:35:04 +00:00
Brendon Cahoon
8b14ad918f Revert 156634 upon request until code improvement changes are made.
llvm-svn: 156775
2012-05-14 19:35:42 +00:00
Dan Gohman
cc1f60a86c Rename @llvm.debugger to @llvm.debugtrap.
llvm-svn: 156774
2012-05-14 18:58:10 +00:00
Akira Hatanaka
6c31f7a19a Release notes for MIPS backend.
llvm-svn: 156772
2012-05-14 18:40:07 +00:00
Andrew Trick
c0a8fc3638 Remove a stale forward declaration.
llvm-svn: 156770
2012-05-14 18:03:19 +00:00
Jakob Stoklund Olesen
184e921187 Remove the expensive BitVector::operator~().
Returning a temporary BitVector is very expensive. If you must, create
the temporary explicitly: Use BitVector(A).flip() instead of ~A.

llvm-svn: 156768
2012-05-14 15:46:27 +00:00
Jakob Stoklund Olesen
f8648a8b0d Remove BitVector binops.
These operators were crazy slow, calling malloc to return a temporary
result. At the same time, they look very innocent when used in code.

If you need temporary BitVectors to compute your thing, create them
explicitly, and use the inplace logical operators. This makes the high
cost explicit in the code.

llvm-svn: 156767
2012-05-14 15:37:25 +00:00
Jakob Stoklund Olesen
6d4ef2b65f Consider ad hoc aliasing when building RegUnits.
Register units can be used to compute if two registers overlap:

  A overlaps B iff units(A) intersects units(B).

With this change, the above holds true even on targets that use ad hoc
aliasing (currently only ARM). This means that register units can be
used to implement regsOverlap() more efficiently, and the register
allocator can use the concept to model interference.

When there is no ad hoc aliasing, the register units correspond to the
maximal cliques in the register overlap graph. This is optimal, no other
register unit assignment can have fewer units.

With ad hoc aliasing, weird things are possible, and we don't try too
hard to compute the maximal cliques. The current approach is always
correct, and it works very well (probably optimally) as long as the ad
hoc aliasing doesn't have cliques larger than pairs. It seems unlikely
that any target would need more.

llvm-svn: 156763
2012-05-14 15:20:39 +00:00
Jakob Stoklund Olesen
a87c0f6c9d Record the ad hoc aliasing graph in CodeGenRegister.
The ad hoc aliasing specified in the 'Aliases' list in .td files is
currently only used by computeOverlaps(). It will soon be needed to
build accurate register units as well, so build the undirected graph in
CodeGenRegister::buildObjectGraph() instead.

Aliasing is a symmetric relationship with only one direction specified
in the .td files. Make sure both directions are represented in
getExplicitAliases().

llvm-svn: 156762
2012-05-14 15:12:37 +00:00
Jakob Stoklund Olesen
ce6916a00b Compute topological signatures of registers.
TableGen creates new register classes and sub-register indices based on
the sub-register structure present in the register bank. So far, it has
been doing that on a per-register basis, but that is not very efficient.

This patch teaches TableGen to compute topological signatures for
registers, and use that to reduce the amount of redundant computation.
Registers get the same TopoSig if they have identical sub-register
structure.

TopoSigs are not currently exposed outside TableGen.

llvm-svn: 156761
2012-05-14 15:10:07 +00:00
Jakob Stoklund Olesen
8783cdf045 Add BitVector::anyCommon().
The existing operation (A & B).any() is very slow.

llvm-svn: 156760
2012-05-14 15:01:19 +00:00
Stepan Dyatkovskiy
f050e5bcbf SwitchInst cosmetics: renamed "Hash" method to "hash"
llvm-svn: 156757
2012-05-14 08:26:31 +00:00