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326 Commits

Author SHA1 Message Date
Chris Lattner
2e64872117 Remove some ugly now-redundant casts. 
llvm-svn: 28864
 2006-06-20 00:25:29 +00:00
Chris Lattner
fbea064e90 Fix some mismatched type constraints 
llvm-svn: 28862
 2006-06-20 00:12:37 +00:00
Evan Cheng
98d508af83 Minor clean up. 
llvm-svn: 28860
 2006-06-19 19:25:30 +00:00
Evan Cheng
bc79e5f0e4 Type of vector extract / insert index operand should be iPTR. 
llvm-svn: 28796
 2006-06-15 08:14:54 +00:00
Evan Cheng
889544823a Rename instructions for consistency sake. 
llvm-svn: 28594
 2006-05-31 19:00:07 +00:00
Evan Cheng
abbbe57ba2 Select vector_shuffle v1, undef <2, 3, ?, ?> to MOVHLPS. 
llvm-svn: 28582
 2006-05-31 00:51:37 +00:00
Evan Cheng
c024ad7f32 MAXP{D|S} and MINP{D|S} are commutable. 
llvm-svn: 28578
 2006-05-30 23:47:30 +00:00
Evan Cheng
e2397256c1 Commute shufps / shufpd. 
llvm-svn: 28577
 2006-05-30 23:34:30 +00:00
Evan Cheng
03ca651244 Allow shufps x, x, mask to be converted to pshufd x, mask to save a move. 
llvm-svn: 28565
 2006-05-30 20:26:50 +00:00
Evan Cheng
dc9b5f5fc0 X86 integer register classes naming changes. Make them consistent with FP, vector classes. 
llvm-svn: 28324
 2006-05-16 07:21:53 +00:00
Chris Lattner
a03676690b Teach the code generator to use cvtss2sd as extload f32 -> f64 
llvm-svn: 28131
 2006-05-05 21:35:18 +00:00
Evan Cheng
ef2fbe7460 Use movsd to shuffle in the lowest two elements of a v4f32 / v4i32 vector when 
movlps cannot be used (e.g. when load from m64 has multiple uses).

llvm-svn: 28089
 2006-05-03 20:32:03 +00:00
Evan Cheng
abc391a5a6 Fix a typo. 
llvm-svn: 27968
 2006-04-25 17:48:41 +00:00
Evan Cheng
7f0e30d1a2 Explicitly specify result type for def : Pat<> patterns (if it produces a vector 
result). Otherwise tblgen will pick the default (v16i8 for 128-bit vector).

llvm-svn: 27965
 2006-04-25 00:50:01 +00:00
Evan Cheng
e521de4e60 Added X86 SSE2 intrinsics which can be represented as vector_shuffles. This is 
a temporary workaround for the 2-wide vector_shuffle problem (i.e. its mask
would have type v2i32 which is not legal).

llvm-svn: 27964
 2006-04-24 23:34:56 +00:00
Evan Cheng
3306427d87 Some missing movlps, movhps, movlpd, and movhpd patterns. 
llvm-svn: 27960
 2006-04-24 21:58:20 +00:00
Evan Cheng
e0289de5ab Now generating perfect (I think) code for "vector set" with a single non-zero 
scalar value.

e.g.
        _mm_set_epi32(0, a, 0, 0);
==>
	movd 4(%esp), %xmm0
	pshufd $69, %xmm0, %xmm0

        _mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
	movzbw 4(%esp), %ax
	movzwl %ax, %eax
	pxor %xmm0, %xmm0
	pinsrw $5, %eax, %xmm0

llvm-svn: 27923
 2006-04-21 01:05:10 +00:00
Evan Cheng
7bbfc1d41a Prefer {p}unpack* and mov*dup over {p}shuf* as well. 
llvm-svn: 27844
 2006-04-19 21:15:24 +00:00
Evan Cheng
a52eb1d7d5 - Renamed AddedCost to AddedComplexity. 
- Added more movhlps and movlhps patterns.

llvm-svn: 27842
 2006-04-19 20:37:34 +00:00
Evan Cheng
56e205e534 More mov{h|l}p{d|s} patterns. 
llvm-svn: 27836
 2006-04-19 18:20:17 +00:00
Evan Cheng
b42424177c - More mov{h|l}ps patterns. 
- Increase cost (complexity) of patterns which match mov{h|l}ps ops. These
  are preferred over shufps in most cases.

llvm-svn: 27835
 2006-04-19 18:11:52 +00:00
Evan Cheng
7364ee1c92 - PEXTRW cannot take a memory location as its first source operand. 
- PINSRWrmi encoding bug.

llvm-svn: 27818
 2006-04-18 21:59:43 +00:00
Evan Cheng
f16e4bf29d Name change for clarity sake 
llvm-svn: 27816
 2006-04-18 21:55:35 +00:00
Evan Cheng
8e87e9b0db Name change for clarity sake 
llvm-svn: 27814
 2006-04-18 21:29:50 +00:00
Evan Cheng
838f053b09 Left a pattern out 
llvm-svn: 27813
 2006-04-18 21:29:08 +00:00
Evan Cheng
2cd4e2d240 Fixed an encoding bug: movd from XMM to R32. 
llvm-svn: 27807
 2006-04-18 18:19:00 +00:00
Evan Cheng
98b1ca65dd Use movss to insert_vector_elt(v, s, 0). 
llvm-svn: 27782
 2006-04-17 22:45:49 +00:00
Evan Cheng
833ce43152 Encoding bug 
llvm-svn: 27773
 2006-04-17 21:33:57 +00:00
Evan Cheng
3d26db8148 Errors in patterns preventing load folding 
llvm-svn: 27762
 2006-04-17 18:05:01 +00:00
Evan Cheng
68b2e5b4b0 movduprm, movshduprm bugs 
llvm-svn: 27734
 2006-04-16 18:11:28 +00:00
Evan Cheng
26d917789c Encoding bugs 
llvm-svn: 27733
 2006-04-16 07:02:22 +00:00
Evan Cheng
9f33b2abc5 More encoding bugs 
llvm-svn: 27722
 2006-04-15 06:10:09 +00:00
Evan Cheng
87e0cd1569 pslldrm, psrawrm, etc. encoding bug 
llvm-svn: 27721
 2006-04-15 05:59:08 +00:00
Evan Cheng
4487cf8125 hsubp{s|d} encoding bug 
llvm-svn: 27720
 2006-04-15 05:52:42 +00:00
Evan Cheng
32e5d4f6bc Silly bug 
llvm-svn: 27719
 2006-04-15 05:37:34 +00:00
Evan Cheng
c626c9bb00 Some clean up 
llvm-svn: 27715
 2006-04-14 23:32:40 +00:00
Evan Cheng
32c4470374 Last few SSE3 intrinsics. 
llvm-svn: 27711
 2006-04-14 21:59:03 +00:00
Evan Cheng
184264997e Misc. SSE2 intrinsics: clflush, lfench, mfence 
llvm-svn: 27699
 2006-04-14 07:43:12 +00:00
Evan Cheng
360a73046f pcmpeq* and pcmpgt* intrinsics. 
llvm-svn: 27685
 2006-04-14 01:39:53 +00:00
Evan Cheng
18a1a0e199 psll*, psrl*, and psra* intrinsics. 
llvm-svn: 27684
 2006-04-14 00:14:05 +00:00
Evan Cheng
f7645b0c49 Doh. PANDrm, etc. are not commutable. 
llvm-svn: 27668
 2006-04-13 18:11:28 +00:00
Evan Cheng
2de048bc69 psad, pmax, pmin intrinsics. 
llvm-svn: 27647
 2006-04-13 06:11:45 +00:00
Evan Cheng
93dcea2b5a Various SSE2 packed integer intrinsics: pmulhuw, pavgw, etc. 
llvm-svn: 27645
 2006-04-13 05:24:54 +00:00
Evan Cheng
2f634fac6d padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics. 
llvm-svn: 27639
 2006-04-13 00:43:35 +00:00
Evan Cheng
537bdb370c Naming inconsistency. 
llvm-svn: 27638
 2006-04-13 00:00:23 +00:00
Evan Cheng
8768f25c80 SSE / SSE2 conversion intrinsics. 
llvm-svn: 27637
 2006-04-12 23:42:44 +00:00
Evan Cheng
2c2d734efd All "integer" logical ops (pand, por, pxor) are now promoted to v2i64. 
Clean up and fix various logical ops issues.

llvm-svn: 27633
 2006-04-12 21:21:57 +00:00
Evan Cheng
66fb7beed7 Promote v4i32, v8i16, v16i8 load to v2i64 load. 
llvm-svn: 27612
 2006-04-12 17:12:36 +00:00
Evan Cheng
fbdf6ece4a Various SSE2 conversion intrinsics 
llvm-svn: 27603
 2006-04-12 05:20:24 +00:00
Evan Cheng
68b885f50c Added __builtin_ia32_storelv4si, __builtin_ia32_movqv4si, 
__builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu.

llvm-svn: 27599
 2006-04-11 22:28:25 +00:00
Evan Cheng
c0848b1eaf gcc lower SSE prefetch into generic prefetch intrinsic. Need to add support 
later.

llvm-svn: 27591
 2006-04-11 18:04:57 +00:00
Evan Cheng
7a9fca11b5 Misc. intrinsics. 
llvm-svn: 27590
 2006-04-11 17:35:57 +00:00
Evan Cheng
798acd4094 movnt* and maskmovdqu intrinsics 
llvm-svn: 27587
 2006-04-11 06:57:30 +00:00
Evan Cheng
da283be867 Added support for _mm_move_ss and _mm_move_sd. 
llvm-svn: 27575
 2006-04-11 00:19:04 +00:00
Evan Cheng
b7ccf3b282 Remove some bogus patterns; clean up. 
llvm-svn: 27569
 2006-04-10 22:35:16 +00:00
Evan Cheng
983d251e3d Added some missing shuffle patterns. 
llvm-svn: 27564
 2006-04-10 21:42:19 +00:00
Evan Cheng
352e751a9e movups / movupd 
llvm-svn: 27562
 2006-04-10 21:11:06 +00:00
Evan Cheng
2b6c899eb2 Conditional move of vector types. 
llvm-svn: 27556
 2006-04-10 07:23:14 +00:00
Evan Cheng
0916c33201 ldmxcsr and stmxcsr. 
llvm-svn: 27506
 2006-04-08 00:47:44 +00:00
Evan Cheng
12da231c27 Added patterns for MOVHPSmr and MOVLPSmr. 
llvm-svn: 27497
 2006-04-07 21:20:58 +00:00
Evan Cheng
aaa0d70b65 A MOVPS2SSmr, i.e. _mm_store_ss, encoding bug. 
Also MOVPDI2DIrr.

llvm-svn: 27476
 2006-04-06 23:53:29 +00:00
Evan Cheng
9f27046dc9 - movlp{s|d} and movhp{s|d} support. 
- Normalize shuffle nodes so result vector lower half elements come from the
  first vector, the rest come from the second vector. (Except for the
  exceptions :-).
- Other minor fixes.

llvm-svn: 27474
 2006-04-06 23:23:56 +00:00
Evan Cheng
d2d7aff6ba POR encoded as PAND, yikes. 
llvm-svn: 27446
 2006-04-06 01:49:20 +00:00
Evan Cheng
6d470008c8 Support for comi / ucomi intrinsics. 
llvm-svn: 27444
 2006-04-05 23:38:46 +00:00
Evan Cheng
056e0af55a Handle canonical form of e.g. 
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>

This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.

It would match a {p}unpckl on x86.

llvm-svn: 27437
 2006-04-05 07:20:06 +00:00
Evan Cheng
f745d450c5 Added pslldq and psrldq. 
llvm-svn: 27412
 2006-04-04 21:49:39 +00:00
Evan Cheng
22dd2900e6 Minor fixes + naming changes. 
llvm-svn: 27410
 2006-04-04 19:12:30 +00:00
Evan Cheng
3f7a10bee8 PSHUF* encoding bugs. 
llvm-svn: 27405
 2006-04-04 18:40:36 +00:00
Evan Cheng
f07104b717 cmpps / cmppd encoding bug 
llvm-svn: 27393
 2006-04-04 03:04:07 +00:00
Evan Cheng
2be8582ddb Compact some intrinsic definitions. 
llvm-svn: 27388
 2006-04-04 00:10:53 +00:00
Evan Cheng
bbe72d932c Some SSE1 intrinsics: min, max, sqrt, etc. 
llvm-svn: 27384
 2006-04-03 23:49:17 +00:00
Evan Cheng
7ff32cd571 Use movlpd to: store lower f64 extracted from v2f64. 
Use movhpd to: store upper f64 extracted from v2f64.

llvm-svn: 27382
 2006-04-03 22:30:54 +00:00
Evan Cheng
169240beb7 - More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc. 
- Some bug fixes and naming inconsistency fixes.

llvm-svn: 27377
 2006-04-03 20:53:28 +00:00
Evan Cheng
4623ebd3d0 Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed 
INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.

llvm-svn: 27314
 2006-03-31 21:55:24 +00:00
Evan Cheng
fb980688f1 Added support for SSE3 horizontal ops: haddp{s|d} and hsub{s|d}. 
llvm-svn: 27310
 2006-03-31 21:29:33 +00:00
Evan Cheng
7b9a0c6d7a Add support to use pextrw and pinsrw to extract and insert a word element 
from a 128-bit vector.

llvm-svn: 27304
 2006-03-31 19:22:53 +00:00
Evan Cheng
d3c692650f Make sure all possible shuffles are matched. 
Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.

llvm-svn: 27259
 2006-03-30 19:54:57 +00:00
Evan Cheng
4150ec59a3 More logical ops patterns 
llvm-svn: 27257
 2006-03-30 07:33:32 +00:00
Evan Cheng
57d481a78a Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics 
llvm-svn: 27256
 2006-03-30 06:21:22 +00:00
Evan Cheng
82d2a6910f Add 128-bit pmovmskb intrinsic support. 
llvm-svn: 27255
 2006-03-30 00:33:26 +00:00
Evan Cheng
9ebe75e915 Change SSE pack operation definitions to fit what the intrinsics expected. 
For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.

llvm-svn: 27254
 2006-03-29 23:53:14 +00:00
Evan Cheng
7bc3bc8246 - Added some SSE2 128-bit packed integer ops. 
- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.

llvm-svn: 27252
 2006-03-29 23:07:14 +00:00
Evan Cheng
d0d3eade59 Need to special case splat after all. Make the second operand of splat 
vector_shuffle undef.

llvm-svn: 27250
 2006-03-29 19:02:40 +00:00
Evan Cheng
e7701928bb Floating point logical operation patterns should match bit_convert. Or else 
integer vector logical operations would match andp{s|d} instead of pand.

llvm-svn: 27248
 2006-03-29 18:47:40 +00:00
Evan Cheng
02b5de9b3e - More shuffle related bug fixes. 
- Whenever possible use ops of the right packed types for vector shuffles /
  splats.

llvm-svn: 27246
 2006-03-29 03:04:49 +00:00
Evan Cheng
5194a37602 - Only use pshufd for v4i32 vector shuffles. 
- Other shuffle related fixes.

llvm-svn: 27244
 2006-03-29 01:30:51 +00:00
Evan Cheng
e7a50a5851 Added aliases to scalar SSE instructions, e.g. addss, to match x86 intrinsics. 
The source operands type are v4sf with upper bits passes through.
Added matching code for these.

llvm-svn: 27240
 2006-03-28 23:51:43 +00:00
Evan Cheng
7b7954f53f movlps and movlpd should be modeled as two address code. 
llvm-svn: 27221
 2006-03-28 07:01:28 +00:00
Evan Cheng
9f0e244187 Typo 
llvm-svn: 27219
 2006-03-28 06:53:49 +00:00
Evan Cheng
fb4b2bfc7d * Prefer using operation of matching types. e.g unpcklpd rather than movlhps. 
* Bug fixes.

llvm-svn: 27218
 2006-03-28 06:50:32 +00:00
Evan Cheng
4d554dae17 - Clean up / consoladate various shuffle masks. 
- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.

llvm-svn: 27210
 2006-03-28 02:43:26 +00:00
Evan Cheng
d8d7ec47bd Model unpack lower and interleave as vector_shuffle so we can lower the 
intrinsics as such.

llvm-svn: 27200
 2006-03-28 00:39:58 +00:00
Chris Lattner
b64eb6593a unbreak the build 
llvm-svn: 27174
 2006-03-27 16:52:45 +00:00
Evan Cheng
0865274fa5 Use pcmpeq to generate vector of all ones. 
llvm-svn: 27167
 2006-03-27 07:00:16 +00:00
Evan Cheng
1dfbede1d1 Remove X86:isZeroVector, use ISD::isBuildVectorAllZeros instead; some fixes / cleanups 
llvm-svn: 27150
 2006-03-26 09:53:12 +00:00
Evan Cheng
e5807f6b47 Build arbitrary vector with more than 2 distinct scalar elements with a 
series of unpack and interleave ops.

llvm-svn: 27119
 2006-03-25 09:37:23 +00:00
Evan Cheng
8601147e68 Added SSE cachebility ops 
llvm-svn: 27103
 2006-03-25 06:03:26 +00:00
Evan Cheng
234090b386 Added 128-bit packed integer subtraction. 
llvm-svn: 27096
 2006-03-25 01:33:37 +00:00
Evan Cheng
041c9c534b Added CVTSS2SI. 
llvm-svn: 27094
 2006-03-25 01:00:18 +00:00
Evan Cheng
bdb85b387f Support for scalar to vector with zero extension. 
llvm-svn: 27091
 2006-03-24 23:15:12 +00:00
Evan Cheng
33dad39b46 Added LDMXCSR 
llvm-svn: 27087
 2006-03-24 22:28:37 +00:00
Chris Lattner
2d08e8aee1 plug the intrinsics into the patterns for movmsk* 
llvm-svn: 27083
 2006-03-24 21:49:18 +00:00
Evan Cheng
d58d54cf3e Handle BUILD_VECTOR with all zero elements. 
llvm-svn: 27056
 2006-03-24 07:29:27 +00:00
Evan Cheng
3028b04057 More efficient v2f64 shuffle using movlhps, movhlps, unpckhpd, and unpcklpd. 
llvm-svn: 27040
 2006-03-24 02:58:06 +00:00
Evan Cheng
68410804f0 Handle more shuffle cases with SHUFP* instructions. 
llvm-svn: 27024
 2006-03-24 01:18:28 +00:00
Evan Cheng
a6dc6e535d Following icc's lead: use movdqa to load / store 128-bit integer vectors 
llvm-svn: 26980
 2006-03-23 07:44:07 +00:00
Evan Cheng
c1fe87ea8b Add v4i32 <-> v4f32 bitconvert patterns. 
llvm-svn: 26969
 2006-03-23 02:36:37 +00:00
Evan Cheng
5f7cf963db Add 128-bit integer vector load and add (for testing). 
llvm-svn: 26967
 2006-03-23 01:57:24 +00:00
Evan Cheng
56b67b2c4f SHUFP* are two address code. 
llvm-svn: 26959
 2006-03-22 20:08:18 +00:00
Evan Cheng
ae6a39ea92 - Supposely movlhps is faster / better than unpcklpd. 
- Don't forget pshufd is only available with sse2.

llvm-svn: 26956
 2006-03-22 19:16:21 +00:00
Evan Cheng
cff38e19c3 - Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support 
splat and PSHUFD cases.
- Clean up shuffle / splat matching code.

llvm-svn: 26954
 2006-03-22 18:59:22 +00:00
Evan Cheng
f6dc0a7f5e - VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches 
PSHUFD. We can make permutes entries which point to the undef pointing
  anything we want.
- Change some names to appease Chris.

llvm-svn: 26951
 2006-03-22 08:01:21 +00:00
Evan Cheng
25440d19b1 Fix PSHUF* and SHUF* jit code emission problems 
llvm-svn: 26949
 2006-03-22 07:10:28 +00:00
Evan Cheng
7aac4350c7 Some splat and shuffle support. 
llvm-svn: 26940
 2006-03-22 02:53:00 +00:00
Evan Cheng
47dd756c72 - Use movaps to store 128-bit vector integers. 
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.

llvm-svn: 26932
 2006-03-21 23:01:21 +00:00
Evan Cheng
6ec225863c - Remove scalar to vector pseudo ops. They are just wrong. 
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.

llvm-svn: 26919
 2006-03-21 07:09:35 +00:00
Evan Cheng
a4db61ddc1 x86 ISD::SCALAR_TO_VECTOR support. 
llvm-svn: 26911
 2006-03-21 00:33:35 +00:00
Evan Cheng
c63d434203 Move a few things around. 
llvm-svn: 26893
 2006-03-20 06:04:52 +00:00
Evan Cheng
cc1e38c242 Vector undef's 
llvm-svn: 26870
 2006-03-19 09:38:54 +00:00
Evan Cheng
8dd794ea70 Use the generic vector register classes VR64 / VR128 rather than V4F32, 
V8I16, etc.

llvm-svn: 26838
 2006-03-18 01:23:20 +00:00
Evan Cheng
ee1a44d5d8 Move some pattern fragments to the right files. 
llvm-svn: 26831
 2006-03-17 19:55:52 +00:00
Evan Cheng
005de9e2bb Added MMX, SSE1, and SSE2 vector instructions and some simple patterns. 
Fixed some existing bugs (wrong predicates, prefixes) at the same time.

llvm-svn: 26310
 2006-02-22 02:26:30 +00:00
Evan Cheng
8ab6294f94 One more round of reorg so sabre doesn't freak out. :-) 
llvm-svn: 26303
 2006-02-21 20:00:20 +00:00
Evan Cheng
f7296d8fa5 A big more cleaning up. 
llvm-svn: 26302
 2006-02-21 19:30:30 +00:00
Evan Cheng
223d3a073a Moving things to their proper places. 
llvm-svn: 26301
 2006-02-21 19:26:52 +00:00
Evan Cheng
fee17dfff8 Split instruction info into multiple files, one for each of x87, MMX, and SSE. 
llvm-svn: 26300
 2006-02-21 19:13:53 +00:00