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3808 Commits

Author SHA1 Message Date
Daniel Dunbar
3e99464701 llvm-build: Don't generate duplicate dependencies when LLVMBuild files define 
multiple components.

llvm-svn: 145989
 2011-12-06 23:13:42 +00:00
Evan Cheng
5061553f9d First chunk of MachineInstr bundle support. 
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975
 2011-12-06 22:12:01 +00:00
Jim Grosbach
f972c503d8 Tidy up. Fix naming convention stuff for some internal functions. 
llvm-svn: 145974
 2011-12-06 22:07:02 +00:00
Sebastian Pop
182ae6a6fa use space star instead of star space 
llvm-svn: 145944
 2011-12-06 17:34:16 +00:00
Sebastian Pop
cb55bb22ab add missing point at the end of sentences 
llvm-svn: 145943
 2011-12-06 17:34:11 +00:00
Jim Grosbach
fb734dff3c ARM NEON VEXT aliases for data type suffices. 
llvm-svn: 145726
 2011-12-02 23:34:39 +00:00
Dylan Noblesmith
afe4ff5324 TableGen: fix CMake build s'more 
Oops, missed another missing file from r145629.

llvm-svn: 145636
 2011-12-01 21:53:39 +00:00
Anshuman Dasgupta
f754c8bf8e Add a deterministic finite automaton based packetizer for VLIW architectures 
llvm-svn: 145629
 2011-12-01 21:10:21 +00:00
Jim Grosbach
5c613a4c40 Replace an assert() with an actual diagnostic. 
llvm-svn: 145535
 2011-11-30 23:16:25 +00:00
Jim Grosbach
fa9f6ccd62 ARM parsing for VLD1 two register all lanes, no writeback. 
llvm-svn: 145504
 2011-11-30 18:21:25 +00:00
Jim Grosbach
d97df5c06a llvm_unreachable() is not for user diagnostics.... 
llvm-svn: 145465
 2011-11-30 01:15:55 +00:00
Jim Grosbach
693ce8291c ARM parsing aliases for VLD1 single register all lanes. 
llvm-svn: 145464
 2011-11-30 01:09:44 +00:00
Daniel Dunbar
4e00f5f8fd build/CMake: Finish removal of add_llvm_library_dependencies. 
llvm-svn: 145420
 2011-11-29 19:25:30 +00:00
NAKAMURA Takumi
9e88060bdd lit/TestRunner.py: Try to catch ERROR_FILE_NOT_FOUND, too. 
Thanks to Francois, to let me know.

llvm-svn: 145381
 2011-11-29 06:40:50 +00:00
Bob Wilson
d6042faeb9 Install llvmCore to /usr/local. <rdar://problem/10390708> 
llvm-svn: 145378
 2011-11-29 06:11:56 +00:00
Daniel Dunbar
36e9b032cd llvmbuild/CMake: Update CMake output fragment to include explicit library 
dependency information.

llvm-svn: 145328
 2011-11-29 00:06:50 +00:00
Bill Wendling
d576ee9a81 Support a 'final' release candidate tag. 
llvm-svn: 145243
 2011-11-28 11:45:10 +00:00
NAKAMURA Takumi
e33c002bee lit/TestRunner.py: Use RemoveForce(). 
llvm-svn: 145223
 2011-11-28 01:55:08 +00:00
NAKAMURA Takumi
6393cd009c lit/TestRunner.py: [Win32] Introduce WinWaitReleased(f), to wait for file handles to be released by children. 
When wait() has finished, opened handles (especially writing stdout to file) might not be released immediately.
To wait for released, poll to attempt renaming.

llvm-svn: 145222
 2011-11-28 01:55:01 +00:00
Craig Topper
cfb4ed9cd4 Remove some unnecessary filtering checks from X86 disassembler table build. 
llvm-svn: 144986
 2011-11-19 05:48:20 +00:00
Daniel Dunbar
50227df250 llvm-build: Attempt to work around a CMake Makefile generator bug that doesn't 
properly quote strings when writing the CMakeFiles/Makefile.cmake output file
(which lists the dependencies). This shows up when using CMake + MSYS Makefile
generator.

llvm-svn: 144873
 2011-11-17 01:19:53 +00:00
Owen Anderson
48a129b50e Rename MVT::untyped to MVT::Untyped to match similar nomenclature. 
llvm-svn: 144747
 2011-11-16 01:02:57 +00:00
Evan Cheng
47d8f8af84 Add vmov.f32 to materialize f32 immediate splats which cannot be handled by 
integer variants. rdar://10437054

llvm-svn: 144608
 2011-11-15 02:12:34 +00:00
Jim Grosbach
2ac98a24aa ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions. 
rdar://10435076

llvm-svn: 144606
 2011-11-15 01:46:57 +00:00
Jim Grosbach
97cb1f6146 Tidy up. Formatting. 
llvm-svn: 144598
 2011-11-15 01:05:12 +00:00
Daniel Dunbar
9763106c94 LLVMBuild: Add info for gtest. 
llvm-svn: 144445
 2011-11-12 02:11:04 +00:00
Daniel Dunbar
d6784c1269 LLVMBuild: Alphabetize required_libraries lists. 
llvm-svn: 144416
 2011-11-11 22:59:23 +00:00
Daniel Dunbar
fe59bd30be llvm-build: Add --configure-target-def-file option. 
- Can be used to generate the substitution values we currently use for the various target related .def files.

llvm-svn: 144345
 2011-11-11 00:24:00 +00:00
Daniel Dunbar
846fb32afc LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler. 
llvm-svn: 144344
 2011-11-11 00:23:56 +00:00
Daniel Dunbar
138437ad27 build/Make & CMake: Pass the appropriate --native-target and --enable-targets 
options to llvm-build, so the all-targets etc. components are defined properly.

llvm-svn: 144255
 2011-11-10 01:16:48 +00:00
Daniel Dunbar
f0c4aed0ab llvm-build: Add --native-target and --enable-targets options, and add logic to 
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
 - We still require these components to be in the project (currently in
   lib/Target) so that we have a place to document them and hopefully make it
   more obvious that they are "magic".

llvm-svn: 144253
 2011-11-10 00:50:07 +00:00
Daniel Dunbar
cd4a25f864 llvm-build: Split out the validation logic. 
llvm-svn: 144252
 2011-11-10 00:49:58 +00:00
Daniel Dunbar
c09b47db8f llvm-build: Add an explicit component type to represent targets. 
- Gives us a place to hang target specific metadata (like whether the target has a JIT).

llvm-svn: 144250
 2011-11-10 00:49:51 +00:00
Daniel Dunbar
44d7c5fbba llvm-build: Tidy up options. 
llvm-svn: 144249
 2011-11-10 00:49:42 +00:00
Owen Anderson
ce22d2b033 Remove this from the CMake build since I erased the file. 
llvm-svn: 144245
 2011-11-10 00:07:22 +00:00
Owen Anderson
507b8b1b34 Remove the old-style ARM disassembler, which is no longer used. 
llvm-svn: 144243
 2011-11-09 23:56:06 +00:00
Craig Topper
01b852b95a More AVX2 instructions and their intrinsics. 
llvm-svn: 143895
 2011-11-06 23:04:08 +00:00
Daniel Dunbar
ba1bf9cd90 utils/llvm-build: Ensure output directory exists for tools which write various fragments. 
llvm-svn: 143782
 2011-11-05 04:07:49 +00:00
Daniel Dunbar
eea4a6ec84 utils/llvm-build: Add trivial quoting of slashes for CMake fragment. 
llvm-svn: 143781
 2011-11-05 04:07:43 +00:00
Daniel Dunbar
f1bb0dd894 llvm-build: Quote colons in target names, in an attempt to make msys happy. 
llvm-svn: 143745
 2011-11-04 23:40:11 +00:00
Daniel Dunbar
ef2350c738 llvm-build: Add initial --write-cmake-fragment option. 
llvm-svn: 143744
 2011-11-04 23:10:37 +00:00
Bob Wilson
6269524bb5 Build llvmCore with RTTI enabled. <rdar://problem/10395761> 
llvm-svn: 143714
 2011-11-04 17:57:13 +00:00
Daniel Dunbar
36f864d5ad utils: Rename the "llvmbuild" script to llvm-compilers-check. 
llvm-svn: 143673
 2011-11-04 01:09:02 +00:00
Daniel Dunbar
1acfa4de23 llvm-build: Add initial code for --write-make-fragment. 
llvm-svn: 143661
 2011-11-03 22:46:19 +00:00
Daniel Dunbar
86aba0bafd utils: Remove (way) old nightly test scripts, I don't think anyone uses them and LNT has way better tools than this. 
llvm-svn: 143655
 2011-11-03 21:03:53 +00:00
Daniel Dunbar
1ab272adac llvm-build: Avoid followlinks keyword argument to os.walk. 
- llvm-build should now be Python2.4 compatible as best I know.

llvm-svn: 143641
 2011-11-03 19:45:52 +00:00
Daniel Dunbar
3760ebeebb build: Add initial cut at LLVMBuild.txt files. 
llvm-svn: 143634
 2011-11-03 18:53:17 +00:00
Daniel Dunbar
33ec90d5a9 llvm-build: Update --write-llvmbuild to write out a standard LLVM style file 
header.

llvm-svn: 143629
 2011-11-03 17:56:31 +00:00
Daniel Dunbar
59c32a015d llvm-build: Add "--write-library-table" option for generating the C++ library 
dependency table used by llvm-config.

llvm-svn: 143628
 2011-11-03 17:56:28 +00:00
Daniel Dunbar
c29c610bd2 llvm-build: Add --write-llvmbuild option, which writes out the component tree. 
- Useful for migrating or auto-upgrading the format schema.

llvm-svn: 143626
 2011-11-03 17:56:21 +00:00
Daniel Dunbar
7bd392c820 llvm-build: Add --print-tree command line option. 
llvm-svn: 143625
 2011-11-03 17:56:18 +00:00
Daniel Dunbar
53a6995401 llvm-build: Fill in some details w.r.t. component's parents. 
llvm-svn: 143624
 2011-11-03 17:56:16 +00:00
Daniel Dunbar
a21266263d llvm-build: Validate information on the loaded components and form the topological ordering among them (as well as validating that there are no cycles). 
- Currently we require that all references between components (except the parent relation) fit into a DAG -- this could be relaxed later if it ever proves to be useful.

llvm-svn: 143623
 2011-11-03 17:56:12 +00:00
Daniel Dunbar
297cc17040 llvm-build: Fill in more of component parsing to be more strict and 
differentiate between strings and lists.

llvm-svn: 143622
 2011-11-03 17:56:10 +00:00
Daniel Dunbar
a695c7c611 llvm-build: Sketch code to load LLVMBuild.txt files. 
llvm-svn: 143621
 2011-11-03 17:56:06 +00:00
Daniel Dunbar
d50bc8ff9d build: Stub out llvm-build utility tool. 
llvm-svn: 143620
 2011-11-03 17:56:03 +00:00
Chandler Carruth
50523ec780 The TableGen parts of the CMake build are seriously broken. This fixes 
one aspect of them by having them use the (annoying, if not broken)
proper library dependency model for adding the LLVMTableGen library as
a dependency. This could manifest as a link order issue in the presence
of separate LLVM / Clang source builds with CMake and a linker that
really cares about such things.

Also, add the Support dependency to llvm-tblgen itself so that it
doesn't rely on TableGen's transitive Support dependency. A parallel
change for clang-tblgen will be forthcoming.

llvm-svn: 143531
 2011-11-02 05:03:06 +00:00
Chad Rosier
9031eff807 Rename show-diagnostics to something less ambiguous. 
llvm-svn: 143525
 2011-11-02 00:44:16 +00:00
Bill Wendling
c5c8918efc Do a relative path ln command instead of an absolute path one. Some people strangely enough have different directory layouts... 
llvm-svn: 143302
 2011-10-29 23:49:52 +00:00
Jim Grosbach
3d628952f6 Allow InstAlias's to use immediate matcher patterns that xform the value. 
For example,

On ARM, "mov r3, #-3" is an alias for "mvn r3, #2", so we want to use a
matcher pattern that handles the bitwise negation when mapping to t2MVNi.

llvm-svn: 143233
 2011-10-28 22:32:53 +00:00
Jim Grosbach
188121af2e Allow register classes to match a containing class in InstAliases. 
If the register class in the source alias is a subclass of the register class
of the actual instruction, the alias can still match OK since the constraints
are strictly a subset of what the instruction can actually handle.

llvm-svn: 143200
 2011-10-28 16:43:40 +00:00
Dan Gohman
892b86e74c Remove the Alpha backend. 
llvm-svn: 143164
 2011-10-27 22:56:32 +00:00
Jim Grosbach
ef4767e393 Delete dead code. Nothing ever instantiates this. 
llvm-svn: 143153
 2011-10-27 21:59:17 +00:00
Daniel Dunbar
b1e6d3a421 lit: Drop some unneeded code from example tests. 
- Also, cleanup site.exp files in example tests.

llvm-svn: 143141
 2011-10-27 20:59:19 +00:00
Dan Gohman
77125e4240 Remove the Blackfin backend. 
llvm-svn: 142880
 2011-10-25 00:05:42 +00:00
Dan Gohman
b54d296fd4 Remove the SystemZ backend. 
llvm-svn: 142878
 2011-10-24 23:48:32 +00:00
Chad Rosier
6fddc7abd1 Add options to enable each individual level for the show-diagnostics tool. 
rdar://9683410

llvm-svn: 142856
 2011-10-24 21:56:50 +00:00
Bill Wendling
743c5bcb96 Rename the script to indicate that this is for the TEST=simple tests. 
llvm-svn: 142764
 2011-10-23 20:14:06 +00:00
Bill Wendling
de530037c1 Resurrect the 'find regressions for the TEST=nightly tests' script. 
llvm-svn: 142763
 2011-10-23 20:13:14 +00:00
Craig Topper
0e63b4485c Add X86 RORX instruction 
llvm-svn: 142741
 2011-10-23 07:34:00 +00:00
Benjamin Kramer
03065133c3 Move various generated tables into read-only memory, fixing up const correctness along the way. 
llvm-svn: 142726
 2011-10-22 16:50:00 +00:00
Jim Grosbach
a6e536367e Assembly parsing for 2-register sequential variant of VLD2. 
llvm-svn: 142691
 2011-10-21 22:21:10 +00:00
Jim Grosbach
68dfc88f95 Assembly parsing for 4-register variant of VLD1. 
llvm-svn: 142682
 2011-10-21 20:35:01 +00:00
Jim Grosbach
2c1ca90ac9 Assembly parsing for 3-register variant of VLD1. 
llvm-svn: 142675
 2011-10-21 20:02:19 +00:00
Jim Grosbach
6bb38d0e97 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670
 2011-10-21 18:54:25 +00:00
Duncan Sands
926a63ed67 Ensure timestamps are not embedded into files when doing a release build. 
llvm-svn: 142647
 2011-10-21 09:47:14 +00:00
Bill Wendling
7956e709bf Modify the script to output the regressions and passes into categories. My Python-fu could use some improving... 
llvm-svn: 142643
 2011-10-21 06:58:01 +00:00
Bill Wendling
e9d5765aba Check for divide by zero. 
llvm-svn: 142640
 2011-10-21 06:26:01 +00:00
Duncan Sands
b3278272ae Also compare the built dragonegg objects between phases 2 and 3. 
llvm-svn: 142608
 2011-10-20 20:14:18 +00:00
Duncan Sands
c52861c44e Reset the system compiler each time we start a new flavour. Otherwise 
the last compiler built for the previous flavour is used for the next,
for example the Debug clang compiler was being used for the initial build
of the Release LLVM.  Flavors should be independent of each other.  This
especially matters if the compiler built for the previous flavour doesn't
actually work!

llvm-svn: 142607
 2011-10-20 20:10:58 +00:00
Duncan Sands
6c9aa4404d Add support for testing dragonegg. This is disabled by default. 
In fact this commit is not intended to change anything unless you
use one of the new command line flags.

llvm-svn: 142577
 2011-10-20 11:13:04 +00:00
Bill Wendling
71741da8ac Revamp the script to handle the 'TEST=simple' output. 
llvm-svn: 142559
 2011-10-20 00:45:46 +00:00
Bill Wendling
29934af872 Duncan pointed out that sometimes CC and CXX are used to specify the compiler. Also that the configure script takes care of finding an appropriate compiler if one's not specified. 
llvm-svn: 142489
 2011-10-19 09:47:00 +00:00
Bill Wendling
c668bbe90f Use bash instead. 
llvm-svn: 142486
 2011-10-19 09:25:49 +00:00
Bill Wendling
f28fe31f2e Make changes so that this runs on FreeBSD. 
llvm-svn: 142482
 2011-10-19 08:42:07 +00:00
Joe Abbey
1a12882b26 Adding dependencies to allow -DBUILD_SHARED_LIBS=true to complete. 
llvm-svn: 142464
 2011-10-19 00:13:13 +00:00
Jim Grosbach
6a932d6ad1 ARM VTBL (one register) assembly parsing and encoding. 
llvm-svn: 142441
 2011-10-18 23:02:30 +00:00
Bill Wendling
8e0af5ff3b Don't exit just because some early commands fail. Use the -k flag when running the checks. 
llvm-svn: 142369
 2011-10-18 17:27:12 +00:00
Jim Grosbach
031bb99231 ARM assembly parsing and encoding for VMOV.i64. 
llvm-svn: 142356
 2011-10-18 16:18:11 +00:00
Jim Grosbach
bcfb4ed53c ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. 
llvm-svn: 142321
 2011-10-18 00:22:00 +00:00
Jim Grosbach
1e994e76a7 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. 
llvm-svn: 142303
 2011-10-17 23:09:09 +00:00
Jim Grosbach
f3d495fbbd ARM NEON "vmov.i8" immediate assembly parsing and encoding. 
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.

llvm-svn: 142293
 2011-10-17 22:26:03 +00:00
Bill Wendling
6e5fb6cb2c Forgot to add the project name to the 'svn ls' command. 
llvm-svn: 142282
 2011-10-17 21:45:07 +00:00
Bill Wendling
0200836f77 Add message to svn mkdir command. 
llvm-svn: 142280
 2011-10-17 21:42:29 +00:00
Owen Anderson
9e30a8355b Fix unused variable warning in the rare circumstance that we have no feature-dependent instructions. 
llvm-svn: 142193
 2011-10-17 16:56:47 +00:00
Benjamin Kramer
6ebeef58ed Pick low-hanging MatchEntry shrinkage fruit. 
Shaves 200k off Release-Asserts clang binaries on i386.

llvm-svn: 142191
 2011-10-17 16:18:09 +00:00
Bill Wendling
d425d074bd Don't download and compile compiler-rt, libcxx, and libcxxabi by default. 
llvm-svn: 142185
 2011-10-17 08:41:20 +00:00
Bill Wendling
f3cbc7f9a3 Update to disable asserts. Build a phase 3 compiler, and compare phase 2 files against phase 3. 
llvm-svn: 142173
 2011-10-17 04:46:54 +00:00
Bill Wendling
dae5ca9d5b Overhaul the 'test-release' script. 
This removes support for building llvm-gcc. It will eventually add support for
building other projects.

llvm-svn: 142165
 2011-10-16 22:44:08 +00:00
Bill Wendling
885861ca36 Update the tree before applying patch. 
llvm-svn: 142155
 2011-10-16 20:59:25 +00:00
Craig Topper
6c900d9810 Add X86 PEXTR and PDEP instructions. 
llvm-svn: 142141
 2011-10-16 16:50:08 +00:00
Craig Topper
2cd868184c Add X86 BZHI instruction as well as BMI2 feature detection. 
llvm-svn: 142122
 2011-10-16 07:55:05 +00:00
Craig Topper
91b4292682 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. 
llvm-svn: 142117
 2011-10-16 07:05:40 +00:00
Chris Lattner
391d90c9a6 Make SMDiagnostic a little more sane. Instead of passing around note/warning/error as a 
string, pass it around as an enum.

llvm-svn: 142107
 2011-10-16 05:43:57 +00:00
Chris Lattner
321335142c Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance 
the X86 asmparser to produce ranges in the one case that was annoying me, for example:

test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
              ^~~~~~~

It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use 
ranges where appropriate if someone is interested.

llvm-svn: 142106
 2011-10-16 04:47:35 +00:00
Craig Topper
4c6357d4af Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen 
llvm-svn: 142105
 2011-10-16 03:51:13 +00:00
Bill Wendling
47d9e6b496 Add a helper script to create branches and tag release candidates. 
llvm-svn: 142098
 2011-10-16 02:03:18 +00:00
Bill Wendling
8cb937e255 Add a script that helps merge changes into a release branch. 
llvm-svn: 142097
 2011-10-16 01:54:03 +00:00
Craig Topper
62e63d9bb9 Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. 
llvm-svn: 142082
 2011-10-15 20:46:47 +00:00
David Greene
49763ec294 Fix threads/jobs Calculation 
Pass the correct jobs and threads information to the builder.
We were underutilizing the number of jobs and threads specified
by the user.

llvm-svn: 141977
 2011-10-14 19:12:37 +00:00
David Greene
81607c1378 Add Helpful Messages 
Bit just a bit more verbose about what's going on.  Print options
to make to aid debugging.

llvm-svn: 141976
 2011-10-14 19:12:35 +00:00
David Greene
082a0faa50 Add Option to Skip Install 
Add a --no-install option to skip installing components.  This
speeds up the develop/test cycle.

llvm-svn: 141975
 2011-10-14 19:12:34 +00:00
David Greene
2e7a259810 Add Option to Skip gcc Build 
And a --no-gcc option to skip dragonegg and gcc builds.
This greatly speeds up the develop/test cycle.

llvm-svn: 141974
 2011-10-14 19:12:33 +00:00
Craig Topper
0a11eb1b21 Add X86 ANDN instruction. Including instruction selection. 
llvm-svn: 141947
 2011-10-14 07:06:56 +00:00
Jakob Stoklund Olesen
a31553dbf7 Ban rematerializable instructions with side effects. 
TableGen infers unmodeled side effects on instructions without a
pattern.  Fix some instruction definitions where that was overlooked.

Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.

llvm-svn: 141929
 2011-10-14 01:00:49 +00:00
Jim Grosbach
eb7acc978a ARM parsing and encoding for the <option> form of LDC/STC instructions. 
llvm-svn: 141786
 2011-10-12 17:34:41 +00:00
Eli Friedman
0a06205b37 Remove extra semicolon. 
llvm-svn: 141699
 2011-10-11 19:53:40 +00:00
Craig Topper
7ae42fbd7e Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 
llvm-svn: 141642
 2011-10-11 04:34:23 +00:00
Jakob Stoklund Olesen
ad7ffa5235 Emit full ED initializers even for pseudo-instructions. 
This should unbreak the picky buildbots.

llvm-svn: 141575
 2011-10-10 20:15:49 +00:00
Jakob Stoklund Olesen
f46c756068 Insert dummy ED table entries for pseudo-instructions. 
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.

Add a test case for xorps which has a very high opcode that exposes this
problem.

llvm-svn: 141562
 2011-10-10 18:30:16 +00:00
Jim Grosbach
94980a23e6 ARM NEON assembly parsing and encoding for VDUP(scalar). 
llvm-svn: 141446
 2011-10-07 23:56:00 +00:00
David Greene
ae3329d597 Remove Multidefs 
Multidefs are a bit unwieldy and incomplete.  Remove them in favor of
another mechanism, probably for loops.

Revert "Make Test More Thorough"
Revert "Fix a typo."
Revert "Vim Support for Multidefs"
Revert "Emacs Support for Multidefs"
Revert "Document Multidefs"
Revert "Add a Multidef Test"
Revert "Update Test for Multidefs"
Revert "Process Multidefs"
Revert "Parser Multidef Support"
Revert "Lexer Support for Multidefs"
Revert "Add Multidef Data Structures"

llvm-svn: 141378
 2011-10-07 18:25:05 +00:00
Craig Topper
f083691b6d Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. 
llvm-svn: 141353
 2011-10-07 05:35:38 +00:00
Peter Collingbourne
fe4c1d613c Remove the Clang tblgen backends from LLVM. 
llvm-svn: 141293
 2011-10-06 13:21:42 +00:00
Craig Topper
2614f6f120 Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. 
llvm-svn: 141274
 2011-10-06 06:44:41 +00:00
Peter Collingbourne
253c6a3690 Build system infrastructure for multiple tblgens. 
llvm-svn: 141266
 2011-10-06 01:51:51 +00:00
Jakob Stoklund Olesen
eca6f0542b Remove the TRI::getSubRegisterRegClass() hook. 
This restores my karma after I added TRI::getSubClassWithSubReg().

Register constraints are applied 'backwards'.  Starting from the
register class required by an instruction operand, the correct question
is: 'How can I constrain the super-register register class so all its
sub-registers satisfy the instruction constraint?' The
getMatchingSuperRegClass() hook answers that.

We never need to go 'forwards': Starting from a super-register register
class, what register class are the sub-registers in?  The
getSubRegisterRegClass() hook did that.

llvm-svn: 141258
 2011-10-06 00:08:27 +00:00
David Greene
479bee70de Vim Support for Multidefs 
Add vim highlighting support for multidefs.

llvm-svn: 141238
 2011-10-05 22:42:52 +00:00
David Greene
a92afc5d12 Emacs Support for Multidefs 
Add Emacs font-lock keyword support for multidefs.

llvm-svn: 141237
 2011-10-05 22:42:51 +00:00
Jakob Stoklund Olesen
82905dfc94 Add TRI::getSubClassWithSubReg(RC, Idx) function. 
This function is used to constrain a register class to a sub-class that
supports the given sub-register index.

For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.

The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.

The version provided by TableGen is usually adequate, but targets can
override.

llvm-svn: 141142
 2011-10-05 00:35:49 +00:00
Jakob Stoklund Olesen
da923230c8 Properly use const_iterator. 
This should unbreak the Windows build.

llvm-svn: 141105
 2011-10-04 20:18:39 +00:00
Jakob Stoklund Olesen
703cd60307 Teach TableGen to infer missing register classes. 
The set of register classes should be closed under sub-register
operations and intersections. That will allow the register allocator to
model combinations of constraints accurately.

This patch implements the easiest form of register class inference:  For
every register class, and for every sub-register SubIdx, the subset of
registers in RC that have a SubIdx sub-register should also be a register
class.

This does create some new register classes for the targets in the tree:

ARM gets a new QQQQPR_with_ssub_0.  This class was omitted from the .td
file on purpose because it only has two registers.  InstrEmitter and
RegisterCoalescer have safeguards against selecting too small register
classes, so it is harmless.

PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32
sub-register of LR8.  I think that might be an omission?

X86 puts RIP in the GR64 class, and since that register doesn't have
8-bit sub-registers, we get:

  GR64_with_sub_8bit
  GR64_TC_with_sub_8bit
  GR64_NOREX_with_sub_8bit
  GR64_TC_with_sub_8bit_hi

The various CodeGen classes have already been fixed so adding new
register classes should not affect compile time.

llvm-svn: 141084
 2011-10-04 15:28:49 +00:00
Jakob Stoklund Olesen
af50ba10a0 TableGen: Store all allocation orders together. 
There is no need to keep the primary order separate.

llvm-svn: 141082
 2011-10-04 15:28:44 +00:00
Jakob Stoklund Olesen
c36b745e2e TableGen: Privatize CodeGenRegisterClass::TheDef and Name. 
When TableGen starts creating its own register classes, the synthesized
classes won't have a Record reference.  All register classes must have a
name, though.

llvm-svn: 141081
 2011-10-04 15:28:08 +00:00
Jakob Stoklund Olesen
1e0d8b4237 TableGen: Don't add synthetic Records to the RecordKeeper. 
The RecordKeeper could be shared by multiple target instances, causing
duplicate record errors.

llvm-svn: 141080
 2011-10-04 15:27:53 +00:00
Craig Topper
9d32602cfd Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
llvm-svn: 141065
 2011-10-04 06:30:42 +00:00
Rafael Espindola
0158ec7cce Remove last references to hotpatch. 
llvm-svn: 141057
 2011-10-04 03:08:43 +00:00
Bob Wilson
3cbd97d1a6 Find the strip tool that works with the specified SDKROOT. rdar://10165908 
llvm-svn: 141013
 2011-10-03 18:48:16 +00:00
Craig Topper
7b5028ec10 Fix typo in r140954. 
llvm-svn: 140962
 2011-10-02 04:54:26 +00:00
Craig Topper
43fd621df8 Fix disassembling of INVEPT and INVVPID to take operands 
llvm-svn: 140955
 2011-10-01 21:20:14 +00:00
Craig Topper
99ad3cc23e Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. 
llvm-svn: 140954
 2011-10-01 19:54:56 +00:00
Peter Collingbourne
01246536d9 Move TableGen's parser and entry point into a library 
This is the first step towards splitting LLVM and Clang's tblgen executables.

llvm-svn: 140951
 2011-10-01 16:41:13 +00:00
Bob Wilson
270da20c9e Subtarget getFeatureBits() returns a uint64_t, not unsigned. 
llvm-svn: 140928
 2011-10-01 02:47:54 +00:00
Jakob Stoklund Olesen
05823401a6 Use precomputed BitVector for CodeGenRegisterClass::hasSubClass(). 
All the sub-class bit vectors are computed when first creating the
register bank.

llvm-svn: 140905
 2011-09-30 23:47:05 +00:00
Jakob Stoklund Olesen
010e9bb778 Store sub-class lists as a bit vector. 
This uses less memory and it reduces the complexity of sub-class
operations:

- hasSubClassEq() and friends become O(1) instead of O(N).

- getCommonSubClass() becomes O(N) instead of O(N^2).

In the future, TableGen will infer register classes.  This makes it
cheap to add them.

llvm-svn: 140898
 2011-09-30 22:19:07 +00:00
Jakob Stoklund Olesen
4c57e66252 Extract a slightly more general BitVector printer. 
This one can also print 32-bit groups.

llvm-svn: 140897
 2011-09-30 22:18:54 +00:00
Jakob Stoklund Olesen
402aa89d8a Compute lists of super-classes in CodeGenRegisterClass. 
Use these lists instead of computing them on the fly in
RegisterInfoEmitter.

llvm-svn: 140895
 2011-09-30 22:18:45 +00:00
David Greene
2d3533a153 Implement VarListElementInit:: resolveListElementReference 
Implement VarListElementInit:: resolveListElementReference so that
lists of lists can be indexed.

llvm-svn: 140882
 2011-09-30 20:59:49 +00:00
Jakob Stoklund Olesen
82a55057c4 Precompute a bit vector of register sub-classes. 
llvm-svn: 140827
 2011-09-30 00:10:40 +00:00
Jakob Stoklund Olesen
35c649f61b Order register classes topologically. 
All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.

This will be used to simplify some sub-class operations.

llvm-svn: 140826
 2011-09-30 00:10:36 +00:00
Jakob Stoklund Olesen
d7b6708541 Switch to ArrayRef<CodeGenRegisterClass*>. 
This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

llvm-svn: 140816
 2011-09-29 22:28:37 +00:00
Daniel Dunbar
d499233312 tblgen/ClangDiagnostics: Add support for split default warning "no-werror" and 
"show-in-system-header" bits, which I will be adding in Clang shortly.

llvm-svn: 140741
 2011-09-29 00:29:04 +00:00
Bob Wilson
cf35a852f5 Remove old hack for compiling with gcc-4.0. 
llvm-svn: 140573
 2011-09-26 22:30:57 +00:00
Owen Anderson
7742c81cde ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. 
llvm-svn: 140560
 2011-09-26 21:06:22 +00:00
Jakob Stoklund Olesen
cbd2c336ab Add target hook for pseudo instruction expansion. 
Many targets use pseudo instructions to help register allocation.  Like
the COPY instruction, these pseudos can be expanded after register
allocation.  The early expansion can make life easier for PEI and the
post-ra scheduler.

This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.

llvm-svn: 140472
 2011-09-25 19:21:35 +00:00
Craig Topper
655f8a01e6 Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700. 
llvm-svn: 140370
 2011-09-23 06:57:25 +00:00
Andrew Trick
bfac89c238 Restore hasPostISelHook tblgen flag. 
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.

llvm-svn: 140160
 2011-09-20 18:22:31 +00:00
Andrew Trick
53aeb9f663 ARM isel bug fix for adds/subs operands. 
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile

llvm-svn: 140134
 2011-09-20 03:17:40 +00:00
Eric Christopher
6cf9c3efe8 Remove more of llvmc and dependencies. 
llvm-svn: 140121
 2011-09-20 00:34:27 +00:00
Jim Grosbach
6da9e6b23d Thumb2 assembly parsing and encoding for TBB/TBH. 
llvm-svn: 140078
 2011-09-19 22:21:13 +00:00
David Greene
799578fee4 Better Error Reporting 
Report missing template arguments more helpfully by supplying the name
of the missing argument in the error message.

llvm-svn: 140034
 2011-09-19 18:26:07 +00:00
Eric Christopher
2e1f5823a1 Migrate this to use clang by default as well. 
llvm-svn: 139936
 2011-09-16 20:36:22 +00:00
Eric Christopher
3163b0a2ce We now look for clang, then llvm-gcc, then gcc as our compiler. We don't need 
this anymore.

llvm-svn: 139935
 2011-09-16 20:36:20 +00:00
Craig Topper
60719c7bfb Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler. 
llvm-svn: 139691
 2011-09-14 06:41:26 +00:00
Argyrios Kyrtzidis
d0acbd50a7 [tablegen] In ClangAttrEmitter.cpp handle SourceLocation arguments to attributes. 
llvm-svn: 139617
 2011-09-13 18:41:43 +00:00
Argyrios Kyrtzidis
56cc934d76 In ClangAttrEmitter.cpp emit code that allows attributes to keep their source range. 
llvm-svn: 139598
 2011-09-13 16:05:43 +00:00
Craig Topper
03c833ff84 Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. 
llvm-svn: 139588
 2011-09-13 06:54:58 +00:00
Craig Topper
a9b27eecc9 Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. 
llvm-svn: 139485
 2011-09-11 21:41:45 +00:00
Craig Topper
8361de67b5 Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W. 
llvm-svn: 139484
 2011-09-11 20:23:20 +00:00
Douglas Gregor
6a808433ce Update Clang AST attribute reader tblgen generation to match with ASTReader change 
llvm-svn: 139414
 2011-09-09 21:37:29 +00:00
Jim Grosbach
eb2d668899 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. 
llvm-svn: 139381
 2011-09-09 18:37:27 +00:00
Eli Friedman
fd4451674b Make sure to handle the case where emitPredicateMatch returns false. Noticed by inspection. 
llvm-svn: 139317
 2011-09-08 21:00:31 +00:00
Caitlin Sadowski
ac6881fc85 Added LateParsed property to TableGen attributes. 
This patch was written by DeLesley Hutchins.

llvm-svn: 139300
 2011-09-08 17:40:49 +00:00
James Molloy
090d019a29 Fix warning on windows; use of comparison with bool argument. 
llvm-svn: 139286
 2011-09-08 08:12:01 +00:00
Andrew Trick
dc3f981b08 Fix a use of freed string contents. 
Speculatively try to fix our windows testers with a patch I found on the internet.

llvm-svn: 139279
 2011-09-08 05:25:49 +00:00
Andrew Trick
daeb007cee whitespace 
llvm-svn: 139278
 2011-09-08 05:23:14 +00:00
Jim Grosbach
8b54d19514 Thumb2 assembly parsing and encoding for LDRBT. 
llvm-svn: 139267
 2011-09-07 23:39:14 +00:00
Jim Grosbach
20642fb479 Thumb2 parsing and encoding for LDR(immediate). 
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.

llvm-svn: 139254
 2011-09-07 20:58:57 +00:00
James Molloy
ac057f13a5 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 
llvm-svn: 139250
 2011-09-07 19:42:28 +00:00
Joerg Sonnenberger
9fa9ed6961 Dependency should be on the output file name, not the dependency file 
name.

llvm-svn: 139220
 2011-09-07 02:12:03 +00:00
Benjamin Kramer
b98ae4dc68 valgrind: Suppress glibc's optiized strcasecmp harder. 
llvm-svn: 139084
 2011-09-03 17:59:31 +00:00
Andrew Trick
cac23d1858 Attempt to silence known valgrind errors. 
llvm-svn: 139048
 2011-09-02 22:59:34 +00:00
David Greene
9cb3b3dd2e Make RecordVal Name an Init 
Store a RecordVal's name as an Init to allow class-qualified Record
members to reference Records that have Init names.  We'll use this to
provide more programmability in how we name defs and their associated
members.

llvm-svn: 139031
 2011-09-02 20:12:07 +00:00
Kevin Enderby
edfcba2f3c Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702. 
llvm-svn: 139014
 2011-09-02 18:03:03 +00:00
Craig Topper
316c7bfe37 Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806. 
llvm-svn: 138997
 2011-09-02 04:17:54 +00:00
James Molloy
4a63186421 Fix up r137380 based on post-commit review by Jim Grosbach. 
llvm-svn: 138948
 2011-09-01 18:02:14 +00:00
NAKAMURA Takumi
d18caf57a3 lit: Normalize pathsep slashes also on %T. 
On Python-w32 with mingw msys bash, %T was replaced to "x:\foo\bar...". msys bash cannot handle DOSish paths.

llvm-svn: 138852
 2011-08-31 03:56:17 +00:00
Evan Cheng
91aa81acaa Follow up to r138791. 
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.

llvm-svn: 138810
 2011-08-30 19:09:48 +00:00
Andrew Trick
e1de7514f3 Lit option for ignoring stderr output. 
This is useful for testing a build a temporarily hand instrumented
build.
Patch by arrowdodger!

llvm-svn: 138804
 2011-08-30 17:42:33 +00:00
Craig Topper
5556444bf7 Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807. 
llvm-svn: 138795
 2011-08-30 07:09:35 +00:00
Kevin Enderby
f1aef98ad2 Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217 
llvm-svn: 138771
 2011-08-29 22:06:28 +00:00
Andrew Trick
1b89583203 Reverted r138652, valgrind doesn't understand obj:*/tblgen. 
llvm-svn: 138703
 2011-08-27 06:17:30 +00:00
Owen Anderson
fd21da3506 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. 
llvm-svn: 138675
 2011-08-26 23:32:08 +00:00
Andrew Trick
0c3e000af1 valgrind: Always suppress tblgen leaks. 
I'll clean up the rest of the XFAIL: vg_leak lines if this works.

llvm-svn: 138652
 2011-08-26 20:41:20 +00:00
Douglas Gregor
7d590ad966 lit: Add %T as a replacement for the output directory 
llvm-svn: 138640
 2011-08-26 19:05:18 +00:00
Craig Topper
5af7ba783d Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678. 
llvm-svn: 138552
 2011-08-25 07:42:00 +00:00
Jim Grosbach
b2b155a93f Thumb parsing and encoding support for ADD SP instructions. 
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.

llvm-svn: 138488
 2011-08-24 21:22:15 +00:00
Jim Grosbach
b33129ebad Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode. 
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.

llvm-svn: 138445
 2011-08-24 17:46:13 +00:00
Caitlin Sadowski
9a011eafa9 Thread safety: Adding in an option for variadic expr* array of arguments 
llvm-svn: 138351
 2011-08-23 18:49:23 +00:00
Eric Christopher
cd47076a67 Fix fpimmm->fpimm typo. 
Patch by Micah Villmow!

llvm-svn: 138330
 2011-08-23 15:42:35 +00:00