Jim Grosbach
9c4a598ef2
Add ARM mode operand encoding information for ADDE/SUBE instructions.
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llvm-svn: 116412
2010-10-13 18:00:52 +00:00
Rafael Espindola
b1ae74bd73
Fix another case where we were preferring instructions with large
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immediates instead of 8 bits ones.
llvm-svn: 116410
2010-10-13 17:14:25 +00:00
Benjamin Kramer
3d87b36b64
Remove noisy semicolon.
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llvm-svn: 116407
2010-10-13 15:55:12 +00:00
Rafael Espindola
ff7f11c151
Fix PR8365 by adding a more specialized Pat that checks if an 'and' with
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8 bit constants can be used.
llvm-svn: 116403
2010-10-13 13:31:20 +00:00
Tobias Grosser
70507511ae
Add Region::isTopLevelRegion().
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llvm-svn: 116402
2010-10-13 11:02:44 +00:00
Eric Christopher
f7ab2cd3df
Start handling more global variables.
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llvm-svn: 116401
2010-10-13 09:11:46 +00:00
Tobias Grosser
1eba2917fa
RegionInfo: Fix trivial error that slipped in last minute.
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llvm-svn: 116400
2010-10-13 08:00:53 +00:00
Tobias Grosser
85dce73ab5
RegionInfo: Update RegionInfo after a BB was split.
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llvm-svn: 116398
2010-10-13 05:54:13 +00:00
Tobias Grosser
6aac855519
RegioInfo: Add getExpandedRegion().
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getExpandedRegion() enables us to create non canonical regions. Those regions
can be used to define the largerst region, that fullfills a certain property.
llvm-svn: 116397
2010-10-13 05:54:11 +00:00
Tobias Grosser
ecfaf92c1a
RegionInfo: Allow to update exit and entry of a region.
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llvm-svn: 116396
2010-10-13 05:54:10 +00:00
Tobias Grosser
84dd4b54fc
RegionInfo: Enhance addSubregion.
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llvm-svn: 116395
2010-10-13 05:54:09 +00:00
Tobias Grosser
a2b5df5a6d
RegionInfo: Allow to set the parent region of a basic block.
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llvm-svn: 116394
2010-10-13 05:54:07 +00:00
Rafael Espindola
16d5617ec3
Fix PR8313 by changing ValueToValueMap use a TrackingVH.
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llvm-svn: 116390
2010-10-13 02:08:17 +00:00
Evan Cheng
d07bee932d
Limit load / store issues (at least until we have a true multi-issue aware scheduler).
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llvm-svn: 116389
2010-10-13 01:54:21 +00:00
Rafael Espindola
aa5448f520
Be more consistent in using ValueToValueMapTy.
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llvm-svn: 116387
2010-10-13 01:36:30 +00:00
Bill Wendling
6d8a23c978
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
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just yet.
llvm-svn: 116386
2010-10-13 01:17:33 +00:00
Bill Wendling
ea062d454d
Add encodings for VCVT instructions.
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llvm-svn: 116385
2010-10-13 00:56:35 +00:00
Jim Grosbach
3fe0337063
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
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arithmetic-with-carry-in instructions.
llvm-svn: 116384
2010-10-13 00:50:27 +00:00
Bill Wendling
e6c2fdebbd
Add VCMPZ and VABS.
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llvm-svn: 116383
2010-10-13 00:38:07 +00:00
Tobias Grosser
e5d4a07ab3
RegionInfo: Free the RegionNodes in cache.
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Contributed by: ether
llvm-svn: 116380
2010-10-13 00:07:59 +00:00
Bill Wendling
fddde4cc72
Refactor VCMP instructions.
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llvm-svn: 116379
2010-10-13 00:04:29 +00:00
Jim Grosbach
79cebf409d
Add the rest of the ARM so_reg encoding options (register shifted register)
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and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.
llvm-svn: 116377
2010-10-12 23:53:58 +00:00
Eric Christopher
efbd4146d8
FileCheckize this in a hope to quiet a valgrind warning on grep.
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llvm-svn: 116376
2010-10-12 23:47:58 +00:00
Bill Wendling
47155cfddd
Add encodings for VNMUL[SD].
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llvm-svn: 116375
2010-10-12 23:47:37 +00:00
Bill Wendling
185b548b07
Add encodings for VDIV and VMUL.
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llvm-svn: 116370
2010-10-12 23:22:27 +00:00
Evan Cheng
eefee972cf
Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457.
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llvm-svn: 116368
2010-10-12 23:19:28 +00:00
Jim Grosbach
de78ccb013
Move the ARM so_imm encoding into a custom operand encoder and remove the
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explicit handling of the instructions referencing it from the MC code
emitter.
llvm-svn: 116367
2010-10-12 23:18:08 +00:00
Jim Grosbach
0038f2eec6
Be nitpicky and line up the comments.
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llvm-svn: 116365
2010-10-12 23:14:03 +00:00
Bill Wendling
d1f06024ce
Refactor some of the encoding logic into a base class. This keeps us from having
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to add 10+ lines to every instruction.
It may turn out that we can move this base class into it's parent class.
llvm-svn: 116362
2010-10-12 23:06:54 +00:00
Jim Grosbach
f4cf5bef46
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
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instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
llvm-svn: 116360
2010-10-12 23:00:24 +00:00
Bill Wendling
cd3cb8da45
Add encoding for VSUB and VCMP.
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Fear not! I'm going to try a refactoring right now. :)
llvm-svn: 116359
2010-10-12 22:55:35 +00:00
Bill Wendling
fad2800dbd
Don't need to specify calling convention. Add 'readnone' to functions.
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llvm-svn: 116354
2010-10-12 22:24:10 +00:00
Jim Grosbach
394bc160f9
Allow targets to optionally specify custom binary encoder functions for
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operand values. This is useful for operands which require additional trickery
to encode into the instruction. For example, the ARM shifted immediate and
shifted register operands.
llvm-svn: 116353
2010-10-12 22:21:57 +00:00
Bill Wendling
33a26354c1
Encoding for VADDD. Plus a test for the VFP instructions.
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llvm-svn: 116348
2010-10-12 22:08:41 +00:00
Bill Wendling
79d57782ad
Split out the "size" field from the encoding. The newer documentation has it as
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a separate bit in the coding.
llvm-svn: 116347
2010-10-12 22:03:19 +00:00
Eric Christopher
af5b22e150
Fix thinko in arm fast isel alloca rewrite.
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llvm-svn: 116339
2010-10-12 21:23:43 +00:00
Jim Grosbach
58ee6f3972
Encoding for ARM-mode VADD.F32 instruction.
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llvm-svn: 116338
2010-10-12 21:22:40 +00:00
Owen Anderson
63f757463c
Begin adding static dependence information to passes, which will allow us to
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perform initialization without static constructors AND without explicit initialization
by the client. For the moment, passes are required to initialize both their
(potential) dependencies and any passes they preserve. I hope to be able to relax
the latter requirement in the future.
llvm-svn: 116334
2010-10-12 19:48:12 +00:00
Eric Christopher
303692631e
Combine these together - should probably have some text associated
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that says what why what we just asserted is wrong.
llvm-svn: 116333
2010-10-12 19:44:17 +00:00
Michael J. Spencer
26bda5a647
KillTheDoctor: Fix VS2008 build.
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llvm-svn: 116330
2010-10-12 19:27:44 +00:00
Nick Lewycky
a6815ae877
Mark variable 'NoImplicitFloatOps' used only in an assert as used.
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llvm-svn: 116323
2010-10-12 18:18:03 +00:00
Jim Grosbach
d18b416075
Comment grammar tweakage.
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llvm-svn: 116322
2010-10-12 18:11:41 +00:00
Jim Grosbach
a0f673b561
Add MOVi ARM encoding.
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llvm-svn: 116321
2010-10-12 18:09:12 +00:00
Dan Gohman
d904add908
Initial va_arg support for x86-64. Patch by David Meyer!
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llvm-svn: 116319
2010-10-12 18:00:49 +00:00
Jim Grosbach
dbf116be66
Nuke unused wrapper function.
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llvm-svn: 116318
2010-10-12 17:53:25 +00:00
Jakob Stoklund Olesen
499fe39d23
Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions.
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The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.
The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.
llvm-svn: 116314
2010-10-12 17:15:00 +00:00
Jim Grosbach
10d9bbe0ca
Add encoding information for the remainder of the generic arithmetic
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ARM instructions.
llvm-svn: 116313
2010-10-12 17:11:26 +00:00
Bob Wilson
bbb91c6a1c
PR8359: The ARM backend may end up allocating registers D16 to D31 when
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"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!
llvm-svn: 116310
2010-10-12 16:22:47 +00:00
Eric Christopher
0763cc04c5
Rework alloca handling so that we can load or store from casted
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address that we've looked through.
Fixes compilation problems in tramp3d from earlier patch.
llvm-svn: 116296
2010-10-12 05:39:06 +00:00
Eric Christopher
8a4621b7df
Fix the last two commits to configure - configure is a generated file.
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Made necessary edits to configure.ac and regenerated.
llvm-svn: 116291
2010-10-12 02:42:05 +00:00