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2680 Commits

Author SHA1 Message Date
Andrew Lenharth
a2bda5b0e1 Start on my todo list 
llvm-svn: 28752
 2006-06-12 16:07:18 +00:00
Chris Lattner
a05c244289 Fix X86/inline-asm.ll:test2, a case where an input value was implicitly 
truncated.

llvm-svn: 28733
 2006-06-08 18:27:11 +00:00
Chris Lattner
963fd11359 Fix Regression/CodeGen/X86/inline-asm.ll, a case where inline asm causes 
implement extension of a register.

llvm-svn: 28731
 2006-06-08 18:22:48 +00:00
Chris Lattner
8affee249a Fix an assert-on-inline-inline-asm bug. 
llvm-svn: 28727
 2006-06-08 18:00:47 +00:00
Reid Spencer
81abe5c7f9 For PR798: 
Provide GraphViz support for MingW32. Patch provided by Anton Korobeynikov

llvm-svn: 28688
 2006-06-05 16:26:06 +00:00
Reid Spencer
d9e9ae6b64 For PR798: 
Add support for Graphviz. Patch contributed by Anton Korobeynikov.

llvm-svn: 28684
 2006-06-05 15:44:46 +00:00
Reid Spencer
490c23de9b Prevent the -pedantic option from causing Mac OS/X build problems: 
LiveIntervalAnalysis.cpp:218: error: floating constant exceeds range of 'double'

llvm-svn: 28620
 2006-06-01 06:12:21 +00:00
Reid Spencer
94a443bb29 Use archive libraries instead of object files for VMCore, BCReader, 
BCWriter, and bzip2 libraries. Adjust the various makefiles to accommodate
these changes. This was done to speed up link times.

llvm-svn: 28610
 2006-06-01 01:30:27 +00:00
Evan Cheng
5b6029f577 commuteInstruction() does not always create a new MI! 
llvm-svn: 28592
 2006-05-31 18:03:39 +00:00
Evan Cheng
6a09baaff4 Eliminate a memory leak. 
llvm-svn: 28585
 2006-05-31 07:13:03 +00:00
Evan Cheng
bbc183c90e visitVBinOp: Can't fold divide by zero! 
llvm-svn: 28584
 2006-05-31 06:08:35 +00:00
Evan Cheng
ae1c91ec10 Make sure the register pressure reduction schedulers work for non-uniform 
latency targets, e.g. PPC32.

llvm-svn: 28561
 2006-05-30 18:05:39 +00:00
Evan Cheng
7e0c2d106e When a priority_queue is empty, the behavior of top() operator is 
non-deterministic. Returns NULL when it's empty!

llvm-svn: 28560
 2006-05-30 18:04:34 +00:00
Chris Lattner
d8bd52bfd2 Fix a nasty dag combiner bug that caused nondeterminstic crashes (MY FAVORITE!): 
SimplifySelectOps would eliminate a Select, delete it, then return true.

The clients would see that it did something and return null.

The top level would see a null return, and decide that nothing happened,
proceeding to process the node in other ways: boom.

The fix is simple: clients of SimplifySelectOps should return the select
node itself.

In order to catch really obnoxious boogs like this in the future, add an
assert that nodes are not deleted.  We do this by checking for a sentry node
type that the SDNode dtor sets when a node is destroyed.

llvm-svn: 28514
 2006-05-27 00:43:02 +00:00
Evan Cheng
58bfb4e600 Make CALL node consistent with RET node. Signness of value has type MVT::i32 
instead of MVT::i1. Either is fine except MVT::i32 is probably a legal type
for most (if not all) platforms while MVT::i1 is not.

llvm-svn: 28511
 2006-05-26 23:13:20 +00:00
Evan Cheng
f53c4cc192 Change RET node to include signness information of the return values. e.g. 
RET chain, value1, sign1, value2, sign2

llvm-svn: 28509
 2006-05-26 23:09:09 +00:00
Evan Cheng
328b47bc28 Remove a bogus cast. 
llvm-svn: 28492
 2006-05-26 08:00:14 +00:00
Evan Cheng
6fdd4960aa Turn on -sched-commute-nodes by default. 
llvm-svn: 28465
 2006-05-25 08:37:31 +00:00
Evan Cheng
920d9c86f1 CALL node change: now including signness of every argument. 
llvm-svn: 28461
 2006-05-25 00:55:32 +00:00
Chris Lattner
f604017e47 Patches to make the LLVM sources more -pedantic clean. Patch provided 
by Anton Korobeynikov!  This is a step towards closing PR786.

llvm-svn: 28447
 2006-05-24 17:04:05 +00:00
Evan Cheng
6909147763 -enable-unsafe-fp-math implies -enable-finite-only-fp-math 
llvm-svn: 28437
 2006-05-23 18:18:46 +00:00
Vladimir Prus
125917432a Fix missing include 
llvm-svn: 28435
 2006-05-23 13:43:15 +00:00
Evan Cheng
19e9e63dcd Incorrect SETCC CondCode used for FP comparisons. 
llvm-svn: 28433
 2006-05-23 06:40:47 +00:00
Evan Cheng
00c1318055 lib/Target/Target.td 
llvm-svn: 28386
 2006-05-18 20:42:07 +00:00
Chris Lattner
b2ecc1b1e7 Fix the result of the call to use a correct vbitconvert. There is no need to 
use getPackedTypeBreakdown at all here.

llvm-svn: 28365
 2006-05-17 20:49:36 +00:00
Chris Lattner
924f3fed13 Correct a previous patch which broke CodeGen/PowerPC/vec_call.ll 
llvm-svn: 28364
 2006-05-17 20:43:21 +00:00
Evan Cheng
00f391f87b Fixed a LowerCallTo and LowerArguments bug. They were introducing illegal 
VBIT_VECTOR nodes. There were some confusion about the semantics of
getPackedTypeBreakdown(). e.g. for <4 x f32> it returns 1 and v4f32, not 4,
and f32.

llvm-svn: 28352
 2006-05-17 18:16:39 +00:00
Chris Lattner
4252704561 When we legalize target nodes, do not use getNode to create a new node, 
use UpdateNodeOperands to just update the operands!  This is important because
getNode will allocate a new node if the node returns a flag and this breaks
assumptions in the legalizer that you can legalize some things multiple times
and get exactly the same results.

This latent bug was exposed by my ppc patch last night, and this fixes
gsm/toast.

llvm-svn: 28348
 2006-05-17 18:00:08 +00:00
Chris Lattner
d3ff015877 Add an assertion, avoid some unneeded work for each call. No functionality 
change.

llvm-svn: 28347
 2006-05-17 17:55:45 +00:00
Chris Lattner
30f61c8bb1 Add support for calls that pass and return legal vectors. 
llvm-svn: 28340
 2006-05-16 23:39:44 +00:00
Chris Lattner
01f4f28837 Add a new ISD::CALL node, make the default impl of TargetLowering::LowerCallTo 
produce it.

llvm-svn: 28338
 2006-05-16 22:53:20 +00:00
Andrew Lenharth
14504c85ed Move this code to a common place 
llvm-svn: 28329
 2006-05-16 17:42:15 +00:00
Chris Lattner
ba1dfc1da7 Add a chain to FORMAL_ARGUMENTS. This is a minimal port of the X86 backend, 
it doesn't currently use/maintain the chain properly.  Also, make the
X86ISelLowering.cpp file 80-col clean.

llvm-svn: 28320
 2006-05-16 06:45:34 +00:00
Chris Lattner
fdd62b9073 Move function-live-in-handling code from the sdisel code to the scheduler. 
This code should be emitted after legalize, so it can't be in sdisel.

Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG.  The X86 backend is the only one currently using this hook.

llvm-svn: 28315
 2006-05-16 06:10:58 +00:00
Chris Lattner
fa068a16e1 Print the vreg that livein physregs are live in 
llvm-svn: 28314
 2006-05-16 05:55:30 +00:00
Chris Lattner
b79e3f7155 Legalize FORMAL_ARGUMENTS nodes correctly, we don't want to legalize them once 
for each argument.

llvm-svn: 28313
 2006-05-16 05:49:56 +00:00
Evan Cheng
489f9bd68f Fixing 2006-05-01-SchedCausingSpills.ll; some clean up 
llvm-svn: 28279
 2006-05-13 08:22:24 +00:00
Evan Cheng
7bb257e178 Revert an un-intended change 
llvm-svn: 28278
 2006-05-13 05:53:47 +00:00
Chris Lattner
c439f96b2c Merge identical code. 
llvm-svn: 28274
 2006-05-13 02:11:14 +00:00
Evan Cheng
772647518f If the register allocator cannot find a register to spill, try the aliases. If 
that still fails (because all the register spill weights are inf), just grab
one.

llvm-svn: 28262
 2006-05-12 19:07:46 +00:00
Chris Lattner
9e29384a4b Remove dead vars 
llvm-svn: 28255
 2006-05-12 18:06:45 +00:00
Chris Lattner
9a24639afc remove dead vars 
llvm-svn: 28254
 2006-05-12 18:04:28 +00:00
Chris Lattner
11064741d3 Remove dead variable 
llvm-svn: 28253
 2006-05-12 18:02:04 +00:00
Chris Lattner
474e1b7ef3 Comment out dead variables 
llvm-svn: 28252
 2006-05-12 17:57:54 +00:00
Chris Lattner
90527550c1 Remove dead var 
llvm-svn: 28250
 2006-05-12 17:50:35 +00:00
Chris Lattner
db5b91f6a8 Compile: 
%tmp152 = setgt uint %tmp144, %tmp149           ; <bool> [#uses=1]
        %tmp159 = setlt uint %tmp144, %tmp149           ; <bool> [#uses=1]
        %bothcond2 = or bool %tmp152, %tmp159           ; <bool> [#uses=1]

To setne, not setune, which causes an assertion fault.

llvm-svn: 28244
 2006-05-12 17:03:46 +00:00
Owen Anderson
29e4d70aed Refactor a bunch of includes so that TargetMachine.h doesn't have to include 
TargetData.h.  This should make recompiles a bit faster with my current
TargetData tinkering.

llvm-svn: 28238
 2006-05-12 06:33:49 +00:00
Evan Cheng
f3d7bb7a9e Backing out fix for PR770. Need to re-apply it after live range splitting is possible 
llvm-svn: 28236
 2006-05-12 06:06:34 +00:00
Evan Cheng
c24d0f281c Duh. That could take a long time. 
llvm-svn: 28235
 2006-05-12 06:05:18 +00:00
Chris Lattner
a500852895 Two simplifications for token factor nodes: simplify tf(x,x) -> x. 
simplify tf(x,y,y,z) -> tf(x,y,z).

llvm-svn: 28233
 2006-05-12 05:01:37 +00:00
Evan Cheng
0b8e4bca80 Add capability to scheduler to commute nodes for profit. 
If a two-address code whose first operand has uses below, it should be commuted
when possible.

llvm-svn: 28230
 2006-05-12 01:58:24 +00:00
Evan Cheng
cb2a0f392c Refactor scheduler code. Move register-reduction list scheduler to a 
separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.

llvm-svn: 28226
 2006-05-11 23:55:42 +00:00
Evan Cheng
7028ff2e25 Set weight of zero length intervals to infinite to prevent them from being 
spilled.

llvm-svn: 28220
 2006-05-11 07:29:24 +00:00
Evan Cheng
da04c3aab4 Backing out previous check-in. 
llvm-svn: 28219
 2006-05-11 07:28:16 +00:00
Evan Cheng
03fa9eb65e If the live interval legnth is essentially zero, i.e. in every live range 
the use follows def immediately, it doesn't make sense to spill it and
hope it will be easier to allocate for this LI.

llvm-svn: 28217
 2006-05-10 22:30:41 +00:00
Evan Cheng
9f269c1bef Templatify RegReductionPriorityQueue 
llvm-svn: 28212
 2006-05-10 06:16:44 +00:00
Nate Begeman
3af196c9b2 Fix PR773 
llvm-svn: 28207
 2006-05-09 18:20:51 +00:00
Chris Lattner
486e0660b7 Fix a regression in my patch from last night that broke the llvmgcc4 build on 
ppc

llvm-svn: 28205
 2006-05-09 16:41:59 +00:00
Evan Cheng
1a8feb189e Add pseudo dependency to force a def&use operand to be scheduled last (unless 
the distance between the def and another use is much longer). This is under
option control for now "-sched-lower-defnuse".

llvm-svn: 28201
 2006-05-09 07:13:34 +00:00
Evan Cheng
3f72d2121b Debugging info 
llvm-svn: 28200
 2006-05-09 06:55:15 +00:00
Evan Cheng
aad3fe008e PR 770 - permit coallescing of registers in subset register classes. 
llvm-svn: 28197
 2006-05-09 06:37:48 +00:00
Chris Lattner
b7152b0b42 Implement MASM sections correctly, without a "has masm sections flag" and a bunch of special case code. 
llvm-svn: 28194
 2006-05-09 05:33:48 +00:00
Chris Lattner
28fe830b3b Oh yeah, there are two of these now, unify both. 
llvm-svn: 28192
 2006-05-09 05:24:50 +00:00
Chris Lattner
d2aea9851e Setting SwitchToSectionDirective properly in the MASM backend permits a bunch 
of code to be unified.

llvm-svn: 28191
 2006-05-09 05:23:12 +00:00
Chris Lattner
830bed591e Don't prefix section directives with a tab. Doing so causes blank lines to 
be emitted to the .s file.

llvm-svn: 28189
 2006-05-09 05:19:59 +00:00
Chris Lattner
baefeb1e09 Make the masm codepath work like the normal code path. 
llvm-svn: 28188
 2006-05-09 05:15:58 +00:00
Chris Lattner
6ede576b55 The MASM asmprinter has been fixed, these hacks are no longer needed. 
llvm-svn: 28186
 2006-05-09 05:13:34 +00:00
Chris Lattner
f45b6d5c08 Split SwitchSection into SwitchTo{Text|Data}Section methods. 
llvm-svn: 28184
 2006-05-09 04:59:56 +00:00
Chris Lattner
eed10e837c Make the case I just checked in stronger. Now we compile this: 
short test2(short X, short x) {
  int Y = (short)(X+x);
  return Y >> 1;
}

to:

_test2:
        add r2, r3, r4
        extsh r2, r2
        srawi r3, r2, 1
        blr

instead of:

_test2:
        add r2, r3, r4
        extsh r2, r2
        srwi r2, r2, 1
        extsh r3, r2
        blr

llvm-svn: 28175
 2006-05-08 21:18:59 +00:00
Chris Lattner
7b8a0cfff3 Implement and_sext.ll:test3, generating: 
_test4:
        srawi r3, r3, 16
        blr

instead of:

_test4:
        srwi r2, r3, 16
        extsh r3, r2
        blr

for:

short test4(unsigned X) {
  return (X >> 16);
}

llvm-svn: 28174
 2006-05-08 20:59:41 +00:00
Chris Lattner
4f66de151c Compile this: 
short test4(unsigned X) {
  return (X >> 16);
}

to:

_test4:
        movl 4(%esp), %eax
        sarl $16, %eax
        ret

instead of:

_test4:
        movl $-65536, %eax
        andl 4(%esp), %eax
        sarl $16, %eax
        ret

llvm-svn: 28171
 2006-05-08 20:51:54 +00:00
Chris Lattner
bbe4393bc4 Fold shifts with undef operands. 
llvm-svn: 28167
 2006-05-08 17:29:49 +00:00
Nate Begeman
1f359b07de Make emission of jump tables a bit less conservative; they are now required 
to be only 31.25% dense, rather than 75% dense.

llvm-svn: 28165
 2006-05-08 16:51:36 +00:00
Nate Begeman
b8e351aec5 Fix PR772 
llvm-svn: 28161
 2006-05-08 01:35:01 +00:00
Chris Lattner
f76c0b6662 Simplify some code, add a couple minor missed folds 
llvm-svn: 28152
 2006-05-06 23:06:26 +00:00
Chris Lattner
4a4cbde0bb constant fold sign_extend_inreg 
llvm-svn: 28151
 2006-05-06 23:05:41 +00:00
Chris Lattner
3d5d01a74b remove cases handled elsewhere 
llvm-svn: 28150
 2006-05-06 22:43:44 +00:00
Jeff Cohen
248e133255 Fix some loose ends in MASM support. 
llvm-svn: 28148
 2006-05-06 21:27:14 +00:00
Chris Lattner
ca06e2522e Use the new TargetLowering::ComputeNumSignBits method to eliminate 
sign_extend_inreg operations.  Though ComputeNumSignBits is still rudimentary,
this is enough to compile this:

short test(short X, short x) {
  int Y = X+x;
  return (Y >> 1);
}
short test2(short X, short x) {
  int Y = (short)(X+x);
  return Y >> 1;
}

into:

_test:
        add r2, r3, r4
        srawi r3, r2, 1
        blr
_test2:
        add r2, r3, r4
        extsh r2, r2
        srawi r3, r2, 1
        blr

instead of:

_test:
        add r2, r3, r4
        srawi r2, r2, 1
        extsh r3, r2
        blr
_test2:
        add r2, r3, r4
        extsh r2, r2
        srawi r2, r2, 1
        extsh r3, r2
        blr

llvm-svn: 28146
 2006-05-06 09:30:03 +00:00
Chris Lattner
02d3258820 When inserting casts, be careful of where we put them. We cannot insert 
a cast immediately before a PHI node.

This fixes Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll

llvm-svn: 28143
 2006-05-06 09:10:37 +00:00
Chris Lattner
32e96402c0 Fold trunc(any_ext). This gives stuff like: 
27,28c27
<       movzwl %di, %edi
<       movl %edi, %ebx
---
>       movw %di, %bx

llvm-svn: 28137
 2006-05-05 22:56:26 +00:00
Chris Lattner
c912cf0b07 Shrink shifts when possible. 
llvm-svn: 28136
 2006-05-05 22:53:17 +00:00
Chris Lattner
06cb36074a Indent multiline asm strings more nicely 
llvm-svn: 28132
 2006-05-05 21:47:05 +00:00
Chris Lattner
4b581e4167 Fold (fpext (load x)) -> (extload x) 
llvm-svn: 28130
 2006-05-05 21:34:35 +00:00
Chris Lattner
229d3e3c2d More aggressively sink GEP offsets into loops. For example, before we 
generated:

        movl 8(%esp), %eax
        movl %eax, %edx
        addl $4316, %edx
        cmpb $1, %cl
        ja LBB1_2       #cond_false
LBB1_1: #cond_true
        movl L_QuantizationTables720$non_lazy_ptr, %ecx
        movl %ecx, (%edx)
        movl L_QNOtoQuantTableShift720$non_lazy_ptr, %edx
        movl %edx, 4460(%eax)
        ret
...

Now we generate:

        movl 8(%esp), %eax
        cmpb $1, %cl
        ja LBB1_2       #cond_false
LBB1_1: #cond_true
        movl L_QuantizationTables720$non_lazy_ptr, %ecx
        movl %ecx, 4316(%eax)
        movl L_QNOtoQuantTableShift720$non_lazy_ptr, %ecx
        movl %ecx, 4460(%eax)
        ret

... which uses one fewer register.

llvm-svn: 28129
 2006-05-05 21:17:49 +00:00
Chris Lattner
d7637651b6 Fold some common code. 
llvm-svn: 28124
 2006-05-05 06:32:04 +00:00
Chris Lattner
584874682a Implement: 
// fold (and (sext x), (sext y)) -> (sext (and x, y))
  // fold (or  (sext x), (sext y)) -> (sext (or  x, y))
  // fold (xor (sext x), (sext y)) -> (sext (xor x, y))
  // fold (and (aext x), (aext y)) -> (aext (and x, y))
  // fold (or  (aext x), (aext y)) -> (aext (or  x, y))
  // fold (xor (aext x), (aext y)) -> (aext (xor x, y))

llvm-svn: 28123
 2006-05-05 06:31:05 +00:00
Chris Lattner
bec98440f4 Pull and through and/or/xor. This compiles some bitfield code to: 
mov EAX, DWORD PTR [ESP + 4]
        mov ECX, DWORD PTR [EAX]
        mov EDX, ECX
        add EDX, EDX
        or EDX, ECX
        and EDX, -2147483648
        and ECX, 2147483647
        or EDX, ECX
        mov DWORD PTR [EAX], EDX
        ret

instead of:

        sub ESP, 4
        mov DWORD PTR [ESP], ESI
        mov EAX, DWORD PTR [ESP + 8]
        mov ECX, DWORD PTR [EAX]
        mov EDX, ECX
        add EDX, EDX
        mov ESI, ECX
        and ESI, -2147483648
        and EDX, -2147483648
        or EDX, ESI
        and ECX, 2147483647
        or EDX, ECX
        mov DWORD PTR [EAX], EDX
        mov ESI, DWORD PTR [ESP]
        add ESP, 4
        ret

llvm-svn: 28122
 2006-05-05 06:10:43 +00:00
Chris Lattner
02bb78abd3 Implement a variety of simplifications for ANY_EXTEND. 
llvm-svn: 28121
 2006-05-05 05:58:59 +00:00
Chris Lattner
53e8cbbb83 Factor some code, add these transformations: 
// fold (and (trunc x), (trunc y)) -> (trunc (and x, y))
  // fold (or  (trunc x), (trunc y)) -> (trunc (or  x, y))
  // fold (xor (trunc x), (trunc y)) -> (trunc (xor x, y))

llvm-svn: 28120
 2006-05-05 05:51:50 +00:00
Jeff Cohen
953baf0494 Fix VC++ compilation error. 
llvm-svn: 28117
 2006-05-05 01:47:05 +00:00
Chris Lattner
56694d0bb0 Sink noop copies into the basic block that uses them. This reduces the number 
of cross-block live ranges, and allows the bb-at-a-time selector to always
coallesce these away, at isel time.

This reduces the load on the coallescer and register allocator.  For example
on a codec on X86, we went from:

   1643 asm-printer           - Number of machine instrs printed
    419 liveintervals         - Number of loads/stores folded into instructions
   1144 liveintervals         - Number of identity moves eliminated after coalescing
   1022 liveintervals         - Number of interval joins performed
    282 liveintervals         - Number of intervals after coalescing
   1304 liveintervals         - Number of original intervals
     86 regalloc              - Number of times we had to backtrack
1.90232 regalloc              - Ratio of intervals processed over total intervals
     40 spiller               - Number of values reused
    182 spiller               - Number of loads added
    121 spiller               - Number of stores added
    132 spiller               - Number of register spills
      6 twoaddressinstruction - Number of instructions commuted to coalesce
    360 twoaddressinstruction - Number of two-address instructions

to:

   1636 asm-printer           - Number of machine instrs printed
    403 liveintervals         - Number of loads/stores folded into instructions
   1155 liveintervals         - Number of identity moves eliminated after coalescing
   1033 liveintervals         - Number of interval joins performed
    279 liveintervals         - Number of intervals after coalescing
   1312 liveintervals         - Number of original intervals
     76 regalloc              - Number of times we had to backtrack
1.88998 regalloc              - Ratio of intervals processed over total intervals
      1 spiller               - Number of copies elided
     41 spiller               - Number of values reused
    191 spiller               - Number of loads added
    114 spiller               - Number of stores added
    128 spiller               - Number of register spills
      4 twoaddressinstruction - Number of instructions commuted to coalesce
    356 twoaddressinstruction - Number of two-address instructions

On this testcase, this change provides a modest reduction in spill code,
regalloc iterations, and total instructions emitted.  It increases the number
of register coallesces.

llvm-svn: 28115
 2006-05-05 01:04:50 +00:00
Chris Lattner
db888e7880 Final pass of minor cleanups for MachineInstr 
llvm-svn: 28110
 2006-05-04 19:36:09 +00:00
Evan Cheng
ceb7645d40 Initial support for register pressure aware scheduling. The register reduction 
scheduler can go into a "vertical mode" (i.e. traversing up the two-address
chain, etc.) when the register pressure is low.
This does seem to reduce the number of spills in the cases I've looked at. But
with x86, it's no guarantee the performance of the code improves.
It can be turned on with -sched-vertically option.

llvm-svn: 28108
 2006-05-04 19:16:39 +00:00
Chris Lattner
32adc4592f Remove redundancy and a level of indirection when creating machine operands 
llvm-svn: 28107
 2006-05-04 19:14:44 +00:00
Chris Lattner
075404adaa Remove and simplify some more machineinstr/machineoperand stuff. 
llvm-svn: 28105
 2006-05-04 18:16:01 +00:00
Chris Lattner
eb41c99161 Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. 
llvm-svn: 28104
 2006-05-04 18:05:43 +00:00
Chris Lattner
685568510a Move some methods out of MachineInstr into MachineOperand 
llvm-svn: 28102
 2006-05-04 17:52:23 +00:00
Chris Lattner
97f1af2f14 There shalt be only one "immediate" operand type! 
llvm-svn: 28099
 2006-05-04 17:21:20 +00:00
Chris Lattner
51b0cac238 Change "value" in MachineOperand to be a GlobalValue, as that is the only 
thing that can be in it.  Remove a dead method.

llvm-svn: 28098
 2006-05-04 17:02:51 +00:00