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Commit Graph

206823 Commits

Author SHA1 Message Date
Arthur Eubanks
9df829612b [DCE] Port -redundant-dbg-inst-elim to NPM
This is used to test RemoveRedundantDbgInstrs(), which is used by other
passes.

Reviewed By: ychen

Differential Revision: https://reviews.llvm.org/D91477
2020-11-14 16:55:20 -08:00
Florian Hahn
19840b7955 Recommit "[VPlan] Use VPValue def for VPWidenSelectRecipe."
This reverts the revert commit c8d73d939fa4fda9c87b3979225d02d63062bd68.

It includes a fix for cases where we missed inserting VPValues
for some selects, which should fix PR48142.
2020-11-14 20:00:25 +00:00
David Green
ce6cf752cd [AArch64] Remove unused check prefixes. NFC 2020-11-14 18:30:17 +00:00
Paul C. Anagnostopoulos
151d493181 [TableGen] Fix missing braces in if statement 2020-11-14 12:38:44 -05:00
Mehdi Amini
75727d2f3e Fix build (ninja check without running ninja first)
9218ff50f9 removed the BUILD.txt file, and as a subtle side-effect
libLLVMFrontendOpenACC wasn't a dependency of `ninja check` anymore.
However llvm-config requires all components to be built, and the
relevant test is broken when libLLVMFrontendOpenACC isn't built.

Unittest for libLLVMFrontendOpenACC are pending, but this addition
should fix some bots in the meantime.
2020-11-14 16:57:28 +00:00
Nathan James
0973aff95b [llvm][NFC] Remove unnecessary vector creation in Annotations 2020-11-14 15:55:09 +00:00
Nikita Popov
7c3186ef2c [BasicAA] Remove unnecessary size limitation
We're dropping a common offset from both GEPs here. It's not
necessary for the access sizes to be the same as well.
2020-11-14 16:51:31 +01:00
David Green
b34da80b48 [ARM] Remove more unused check prefixes, NFC 2020-11-14 15:37:53 +00:00
Nico Weber
02db4f902b Fix build after 54f9ee334 2020-11-14 10:23:22 -05:00
Nico Weber
106408c120 [gn build] (manually) merge e51631ca4cf 2020-11-14 10:12:15 -05:00
Paul C. Anagnostopoulos
17cd31c30e [TableGen] Add frontend/backend phase timing capability.
Describe in the BackEnd Developer's Guide. Instrument a few backends.

Remove an old unused timing facility. Add a null backend for timing
the parser.

Differential Revision: https://reviews.llvm.org/D91388
2020-11-14 10:10:29 -05:00
Sanjay Patel
47294cfe00 [CostModel] make default size cost for libcalls small (again)
This was changed recently with D90554 / f7eac51b9b3f
...because we had a regression testing blindspot for intrinsics
that are expected to be lowered to libcalls.

In general, we want the *size* cost for a scalar call to be cheap
even if the other costs are expensive - we expect it to just be
a branch with some optional stack manipulation.

It is likely that we will want to carve out some
exceptions/overrides to this rule as follow-up patches for
calls that have some general and/or target-specific difference
to the expected lowering.

This was noticed as a regression in unrolling, so we have a test
for that now along with a couple of direct cost model tests.

If the assumed scalarization costs for the oversized vector
calls are not realistic, that would be another follow-up
refinement of the cost models.
2020-11-14 08:15:35 -05:00
Sanjay Patel
1fb5766336 [CostModel] add tests for math library calls; NFC 2020-11-14 08:15:35 -05:00
Arnold Schwaighofer
2537f5b63c [Coroutines] Make sure that async coroutine context size is a multiple of the alignment requirement
This simplifies the code the allocator has to executed

Differential Revision: https://reviews.llvm.org/D91471
2020-11-14 04:56:56 -08:00
Paul C. Anagnostopoulos
f82f4bca37 [TableGen] Clean up more .td files
Differential Revision: https://reviews.llvm.org/D91431
2020-11-14 07:32:25 -05:00
Roman Lebedev
f948b65a66 Revert "clang-misexpect: Profile Guided Validation of Performance Annotations in LLVM"
See discussion in https://bugs.llvm.org/show_bug.cgi?id=45073 / https://reviews.llvm.org/D66324#2334485
the implementation is known-broken for certain inputs,
the bugreport was up for a significant amount of timer,
and there has been no activity to address it.
Therefore, just completely rip out all of misexpect handling.

I suspect, fixing it requires redesigning the internals of MD_misexpect.
Should anyone commit to fixing the implementation problem,
starting from clean slate may be better anyways.

This reverts commit 7bdad08429411e7d0ecd58cd696b1efe3cff309e,
and some of it's follow-ups, that don't stand on their own.
2020-11-14 13:12:38 +03:00
Craig Topper
207cb5cde4 [RISCV] Add test cases for fsrw/fslw that don't sign extend the result. NFC
These currently fail to select fsrw/fslw.
2020-11-13 23:31:16 -08:00
Arthur Eubanks
f99e276212 [test] Fix const-addr-no-neg-offset.ll under NPM 2020-11-13 23:29:58 -08:00
Mehdi Amini
5fd6b9a08c Revert "Switch libLLVMFrontendOpenACC to be a regular CMake library and not a "component""
This reverts commit e7ed27653292b2ec545e87204031282b4b237754.

Build is broken with  -DLLVM_LINK_LLVM_DYLIB=ON
2020-11-14 04:14:17 +00:00
Mehdi Amini
c98c27f79e Switch libLLVMFrontendOpenACC to be a regular CMake library and not a "component"
This library is only used in Flang at the moment and not tested withing LLVM.
Having it as a component is breaking llvm-config:

  $ bin/llvm-config --shared-mode
  llvm-config: error: component libraries and shared library

  llvm-config: error: missing: [...]/lib/libLLVMFrontendOpenACC.a

This will reverted when unit-tests are provided for it.

Reviewed By: clementval

Differential Revision: https://reviews.llvm.org/D91470
2020-11-14 02:18:25 +00:00
Mehdi Amini
738b5c2c48 Add an assertion in SmallVector::push_back()
This assertion ensures the input value isn't part of the vector when
growing is required. In such cases the vector will grow and the input
value is invalidated before being read from.

This found 14 failed Tests.

Reviewed By: bkramer

Differential Revision: https://reviews.llvm.org/D84293
2020-11-14 00:55:34 +00:00
Arthur Eubanks
ed0d6ec053 [MemProf][NewPM] Make memprof passes required
Just like other sanitizers.
Fixes check-memprof under NPM.

Reviewed By: leonardchan

Differential Revision: https://reviews.llvm.org/D91389
2020-11-13 15:15:27 -08:00
Stanislav Mekhanoshin
2faf2dbdbb [AMDGPU] Mark sin/cos load folding as modifying the function.
When the load value is folded into the sin/cos operation, the
AMDGPU library calls simplifier could still mark the function
as unmodified. Instead ensure if there is an early return,
return whether the load was folded into the sin/cos call.

Authored by MJDSys

Differential Revision: https://reviews.llvm.org/D91401
2020-11-13 14:49:33 -08:00
Sam Clegg
372af5a9de [WebAssembly] Move GlobalTLSAddress handling to WebAssemblyISelLowering. NFC
I'm not why it was added to DAGToDAG oringally but it seems
to make sense alongside the non-TLS version:  LowerGlobalAddress

Differential Revision: https://reviews.llvm.org/D91432
2020-11-13 14:35:51 -08:00
Lang Hames
4f4c287383 [ORC] Fix missing return value. 2020-11-14 09:31:20 +11:00
Sanjay Patel
03f38b6ec2 [LoopUnroll] add test for full unroll that is sensitive to cost-model; NFC
See discussion in D90554.
2020-11-13 17:15:23 -05:00
Akira Hatanaka
05f0b5f315 [ObjC][ARC] Add and use a function which finds and returns the single
dependency. NFC

Use findSingleDependency in place of FindDependencies and stop passing a
set of Instructions around. Modify FindDependencies to return a boolean
flag which indicates whether the dependencies it has found are all
valid.
2020-11-13 14:02:58 -08:00
Akira Hatanaka
c9d70c3f7d Move variable declarations to functions in which they are used. NFC 2020-11-13 14:02:58 -08:00
Jessica Paquette
3b906a1bea [GlobalISel] Add convenience matchers for nots and all-ones constants
Add a convenience matcher which handles

```
G_XOR %not_reg, -1
```

And a convenience matcher which returns true if an integer constant is
all-ones.

Differential Revision: https://reviews.llvm.org/D91459
2020-11-13 13:54:08 -08:00
Arthur Eubanks
06d1415754 [DFSan][NewPM] Handle dfsan under NPM
Make it required. Since it's a module pass, optnone won't test it, so
extend the clang test to also use opt-bisect now that it's supported.

14/16 check-dfsan tests failed with NPM enabled, now all pass.

Reviewed By: leonardchan

Differential Revision: https://reviews.llvm.org/D91385
2020-11-13 13:41:38 -08:00
Nikita Popov
1c4b501829 [KnownBits] Combine abs() implementations
ValueTracking was using a more powerful abs() implementation. Roll
it into KnownBits::abs(). Also add an exhaustive test for abs(),
in both the poisoning and non-poisoning variants.
2020-11-13 22:23:50 +01:00
Craig Topper
56317fb7c6 [RISCV] Add test case showing failure to use GREVIW for i32 bitreverse if result is not sign extended. NFC 2020-11-13 12:41:41 -08:00
Matt Arsenault
846afa6d9e emacs: Add callbr to keyword list 2020-11-13 15:20:06 -05:00
Matt Arsenault
bc050eb862 GlobalISel: Fix typos 2020-11-13 15:19:26 -05:00
Heejin Ahn
fb835643a1 [WebAssembly] Rename atomic.notify and *.atomic.wait
- atomic.notify -> memory.atomic.notify
- i32.atomic.wait -> memory.atomic.wait32
- i64.atomic.wait -> memory.atomic.wait64

See https://github.com/WebAssembly/threads/pull/149.

Reviewed By: tlively

Differential Revision: https://reviews.llvm.org/D91447
2020-11-13 12:04:48 -08:00
Guozhi Wei
e65607b8ff [AlwaysInliner] Call mergeAttributesForInlining after inlining
Like inlineCallIfPossible and InlinerPass, after inlining mergeAttributesForInlining
should be called to merge callee's attributes to caller. But it is not called in
AlwaysInliner, causes caller's attributes inconsistent with inlined code.

Attached test case demonstrates that attribute "min-legal-vector-width"="512" is
not merged into caller without this patch, and it causes failure in SelectionDAG
when lowering the inlined AVX512 intrinsic.

Differential Revision: https://reviews.llvm.org/D91446
2020-11-13 12:01:35 -08:00
Craig Topper
74d7f5951b [RISCV] Add test case for failure to use GREVIW for i32 bswap if result is not sign extended. NFC 2020-11-13 11:59:12 -08:00
Jianzhou Zhao
a69c398ebc Extend the dfsan store/load callback with write/read address
This helped debugging.

Reviewed-by: morehouse

Differential Revision: https://reviews.llvm.org/D91236
2020-11-13 19:46:32 +00:00
Craig Topper
1de19f0131 [RISCV] Add RORW/ROLW/RORIW/ROLIW test cases that don't sign extend the result. NFC
This shows that we currently fail to select RORIW/ROLIW.
2020-11-13 10:59:32 -08:00
Baptiste Saleil
f21e542c3b [PowerPC] Add paired vector load and store builtins and intrinsics
This patch adds the Clang builtins and LLVM intrinsics to load and store vector pairs.

Differential Revision: https://reviews.llvm.org/D90799
2020-11-13 12:35:10 -06:00
Jessica Paquette
ea446fa791 [AArch64][GlobalISel] Select G_SELECT cc, t, (G_SUB 0, x) -> CSNEG t, x, cc
When we see

```
%sub = G_SUB 0, %x
%select = G_SELECT %cc, %t, %sub
```

Fold away the G_SUB by producing

```
%select = CSNEG %t, %x, cc
```

Simple IR example: https://godbolt.org/z/K8TEnh

This is valid on both sides of the select, but for now, just handle one side.
It may make more sense to handle swapping sides during post-legalizer lowering.

Differential Revision: https://reviews.llvm.org/D90723
2020-11-13 10:12:51 -08:00
Nikita Popov
94141ff663 [Local] Emit nsw for inbounds offset calculation
In line with D90708, we can use nsw for the inbounds offset
calculation -- the muls were already using nsw, but the adds were
not.
2020-11-13 18:39:46 +01:00
Jessica Paquette
ea9106c312 [AArch64][GlobalISel] NFC: Use CmpInst::isUnsigned instead of static helper
Reducing some code duplication.

We had a helper for checking if a predicate is unsigned. Remove that and use
the existing function in Instructions.cpp.

Differential Revision: https://reviews.llvm.org/D91288
2020-11-13 09:35:42 -08:00
Wouter van Oortmerssen
fcaec2bb33 [WebAssembly] Added R_WASM_FUNCTION_OFFSET_I64 for use with DWARF DW_AT_low_pc
Needed for wasm64, see discussion in https://reviews.llvm.org/D91203

Differential Revision: https://reviews.llvm.org/D91395
2020-11-13 09:32:31 -08:00
Simon Pilgrim
ba4efb3482 [CostModel][X86] Remove unused CHECK prefixes
Allows us to remove the "CHECK: {{^}}" hack and help simplify D91275
2020-11-13 17:31:48 +00:00
Nikita Popov
aad72ef238 [Local] Clean up EmitGEPOffset
Handle the emission of the add in a single place, instead of three
different ones.

Don't emit an unnecessary add with zero to start with. It will get
dropped by InstCombine, but we may as well not create it in the
first place. This also means that InstCombine does not need to
specially handle this extra add.

This is conceptually NFC, but can affect worklist order etc.
2020-11-13 18:30:56 +01:00
Yuanfang Chen
06613d74b4 [CGProfile] allows bitcast in metadata node storing function pointers
For example,  during RAUW in IRMover, the `Function` ValueAsMetadata in "CG Profile" could become bitcast.

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D88433
2020-11-13 09:28:21 -08:00
Jessica Paquette
18f4a04bc7 [GlobalISel] Add matchers for specific constants and a matcher for negations
It's fairly common to need matchers for a specific constant value, or for
common idioms like finding a negated register.

Add

- `m_SpecificICst`, which returns true when matching a specific value..
- `m_ZeroInt`, which returns true when an integer 0 is matched.
- `m_Neg`, which returns when a register is negated.

Also update a few places which use idioms related to the new matchers.

Differential Revision: https://reviews.llvm.org/D91397
2020-11-13 09:24:54 -08:00
Nikita Popov
318f4a3446 [SCEV] Fix nsw flags for GEP expressions
The SCEV code for constructing GEP expressions currently assumes
that the addition of the base and all the offsets is nsw if the GEP
is inbounds. While the addition of the offsets is indeed nsw, the
addition to the base address is not, as the base address is
interpreted as an unsigned value.

Fix the GEP expression code to not assume nsw for the base+offset
calculation. However, do assume nuw if we know that the offset is
non-negative. With this, we use the same behavior as the
construction of GEP addrecs does. (Modulo the fact that we
disregard SCEV unification, as the pre-existing FIXME points out).

Differential Revision: https://reviews.llvm.org/D90648
2020-11-13 18:19:32 +01:00
Arthur Eubanks
27a2f57976 [gn build] Port 8741a76f 2020-11-13 09:17:52 -08:00