Jan Vesely
4192bbafb1
AMDGPU: Remove read_workdim intrinsic
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Differential revision: https://reviews.llvm.org/D22732
llvm-svn: 276682
2016-07-25 20:17:02 +00:00
Matt Arsenault
f3c657912f
AMDGPU: Add intrinsic for s_flbit_i32/v_ffbh_i32
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llvm-svn: 275871
2016-07-18 18:35:05 +00:00
Matt Arsenault
924a52e452
AMDGPU/R600: Replace barrier intrinsics
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llvm-svn: 275870
2016-07-18 18:34:59 +00:00
Matt Arsenault
e7de44dc23
AMDGPU: Remove brev intrinsic
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llvm-svn: 275620
2016-07-15 21:27:13 +00:00
Matt Arsenault
3bfc10ac74
AMDGPU: Remove legacy rsq.clamped intrinsic
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Mesa still has a use of llvm.AMDGPU.rsq.f64 remaining.
Also fix mismatch with non-IEEE rsq selecting to IEEE rsq.
llvm-svn: 275617
2016-07-15 21:26:52 +00:00
Matt Arsenault
cfd2c39f42
AMDGPU: Remove unused intrinsics
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llvm-svn: 275371
2016-07-14 05:23:19 +00:00
Matt Arsenault
b343e465ee
AMDGPU: Remove last AMDIL intrinsics
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llvm-svn: 275309
2016-07-13 19:42:06 +00:00
Matt Arsenault
eed0ad4e3e
AMDGPU: Remove bfi and bfm intrinsics
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Nothing is using them.
llvm-svn: 260123
2016-02-08 19:06:01 +00:00
Matt Arsenault
b119805900
AMDGPU: Remove 24-bit intrinsics
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The known bit matching code seems to work reasonably well,
so these shouldn't really be needed.
llvm-svn: 259180
2016-01-29 10:05:16 +00:00
Matt Arsenault
9094a66425
AMDGPU: Move AMDGPU intrinsics only used by R600
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llvm-svn: 258790
2016-01-26 04:49:24 +00:00
Matt Arsenault
581518df24
AMDGPU: Add new amdgcn intrinsics for cube instructions
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More cleanup to try to get all intrinsics using the correct
amdgcn prefix that are as close to the instruction as possible.
llvm-svn: 258786
2016-01-26 04:29:56 +00:00
Matt Arsenault
97a3b39dcb
AMDGPU: Restore AMDGPU prefixed rsq intrinsic for now
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Also move into backend intrinsics to discourage use of the old name.
llvm-svn: 258783
2016-01-26 04:14:16 +00:00
Matt Arsenault
fe8ee22547
AMDGPU: Remove more unused intrinsics
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Replace tests with lrp with basic IR expansion
llvm-svn: 258612
2016-01-23 05:42:38 +00:00
Matt Arsenault
7a5e15697d
AMDGPU: Rename intrinsics to use amdgcn prefix
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The intrinsic target prefix should match the target name
as it appears in the triple.
This is not yet complete, but gets most of the important ones.
llvm.AMDGPU.* intrinsics used by mesa and libclc are still handled
for compatability for now.
llvm-svn: 258557
2016-01-22 21:30:34 +00:00
Matt Arsenault
351925633e
AMDGPU: Remove random TGSI intrinsic
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I don't think this was ever used.
llvm-svn: 258514
2016-01-22 18:42:44 +00:00
Matt Arsenault
21c6e6f537
AMDGPU: Remove AMDGPU.fract intrinsic
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Mesa doesn't use this, and this is pattern matched already
from fsub x, (ffloor x)
llvm-svn: 258513
2016-01-22 18:42:38 +00:00
Matt Arsenault
8442657275
AMDGPU: Remove AMDGPU.trunc intrinsic
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llvm-svn: 258348
2016-01-20 21:05:53 +00:00
Matt Arsenault
ef8d51e654
AMDGPU: Remove AMDIL.fraction intrinsic
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llvm-svn: 258347
2016-01-20 21:05:49 +00:00
Matt Arsenault
d256fbf59a
AMDGPU: Remove AMDIL.round.nearest intrinsic
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llvm-svn: 258346
2016-01-20 21:05:40 +00:00
Matt Arsenault
c463ea6063
AMDGPU: Remove abs intrinsic
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llvm-svn: 258343
2016-01-20 20:58:29 +00:00
Matt Arsenault
97bf24516f
AMDGPU: Remove min/max intrinsics
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This removes support for mesa 11.0.x
llvm-svn: 258342
2016-01-20 20:50:19 +00:00
Matt Arsenault
db9fbb2b79
AMDGPU: Switch barrier intrinsics to using convergent
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noduplicate prevents unrolling of small loops that happen to have
barriers in them. If a loop has a barrier in it, it is OK to duplicate
it for the unroll.
llvm-svn: 256075
2015-12-19 01:46:41 +00:00
Tom Stellard
3f1708598e
R600 -> AMDGPU rename
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llvm-svn: 239657
2015-06-13 03:28:10 +00:00
Tom Stellard
39f7e52397
Revert "AMDGPU: Add core backend files for R600/SI codegen v6"
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This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea.
llvm-svn: 160303
2012-07-16 18:19:53 +00:00
Tom Stellard
9f326179fc
AMDGPU: Add core backend files for R600/SI codegen v6
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llvm-svn: 160270
2012-07-16 14:17:08 +00:00