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Author SHA1 Message Date
Bill Wendling
a0113617f1 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183572
 2013-06-07 21:04:35 +00:00
Bill Wendling
08d9887c0e Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183571
 2013-06-07 21:00:34 +00:00
Bill Wendling
497a10ca08 Remove unused c'tor. 
llvm-svn: 183570
 2013-06-07 20:59:31 +00:00
Tom Stellard
7c091ffbf7 R600: Fix calculation of stack offset in AMDGPUFrameLowering 
We weren't computing structure size correctly and we were relying on
the original alloca instruction to compute the offset, which isn't
always reliable.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183568
 2013-06-07 20:52:05 +00:00
Bill Wendling
9cb1ea6c00 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183567
 2013-06-07 20:42:15 +00:00
Tom Stellard
0ffa8d28b1 R600: Rework subtarget info and remove AMDILDevice classes 
This should simplify the subtarget definitions and make it easier to
add new ones.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183566
 2013-06-07 20:37:48 +00:00
Bill Wendling
ec5227fffd Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183565
 2013-06-07 20:35:25 +00:00
Rui Ueyama
3b2443052a [docs] Add link to Microsoft PE/COFF Spec. 
llvm-svn: 183562
 2013-06-07 20:30:27 +00:00
Bill Wendling
aa15a56463 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183561
 2013-06-07 20:28:55 +00:00
Tom Stellard
f4646ab025 R600: Fix the fetch limits for R600 generation GPUs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64257

llvm-svn: 183560
 2013-06-07 20:28:55 +00:00
Tom Stellard
1ffd5f5a26 R600: Move Subtarget feature definitions into AMDGPU.td 
This is the convention used by the other targets.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183559
 2013-06-07 20:28:49 +00:00
Tom Stellard
17c5c164b3 R600: Remove unnecessary include 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183558
 2013-06-07 20:28:43 +00:00
Eli Bendersky
5881ae7cf3 Add more explicit link targets to headers in LangRef.rst 
llvm-svn: 183555
 2013-06-07 20:24:43 +00:00
Quentin Colombet
474d9dcceb Add a backend option to warn on a given stack size limit. 
Option: -mllvm -warn-stack-size=<limit>
Output (if limit is exceeded):
warning: Stack size limit exceeded (<actual size>) in <functionName>.

The longer term plan is to hook that to a clang warning.
PR:4072
<rdar://problem/13987214>

llvm-svn: 183552
 2013-06-07 20:18:12 +00:00
JF Bastien
c950ffbe08 ARM FastISel integer sext/zext improvements 
My recent ARM FastISel patch exposed this bug:
  http://llvm.org/bugs/show_bug.cgi?id=16178
The root cause is that it can't select integer sext/zext pre-ARMv6 and
asserts out.

The current integer sext/zext code doesn't handle other cases gracefully
either, so this patch makes it handle all sext and zext from i1/i8/i16
to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This
should fix the bug as well as make FastISel faster because it bails to
SelectionDAG less often. See fastisel-ext.patch for this.

fastisel-ext-tests.patch changes current tests to always use reg-imm AND
for 8-bit zext instead of UXTB. This simplifies code since it is
supported on ARMv4t and later, and at least on A15 both should perform
exactly the same (both have exec 1 uop 1, type I).

2013-05-31-char-shift-crash.ll is a bitcode version of the above bug
16178 repro.

fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel
should now handle.

Note that my ARM FastISel enabling patch was reverted due to a separate
failure when dealing with MCJIT, I'll fix this second failure and then
turn FastISel on again for non-iOS ARM targets.

I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15
hardware.

llvm-svn: 183551
 2013-06-07 20:10:37 +00:00
Benjamin Kramer
8a5e172647 R600: Don't compare iterators of different maps. 
Found be libstdc's debug mode.

llvm-svn: 183549
 2013-06-07 19:59:34 +00:00
Eli Bendersky
ef135f44df Add explicit link targets to some headers in LangRef.rst 
llvm-svn: 183548
 2013-06-07 19:40:08 +00:00
Manman Ren
c327cbd696 No functionality change. 
Constify a few member functions.

llvm-svn: 183546
 2013-06-07 18:53:29 +00:00
Quentin Colombet
a8970e620f Teach AsmPrinter how to print odd constants. 
Fix an assertion when the compiler encounters big constants whose bit width is
not a multiple of 64-bits.
Although clang would never generate something like this, the backend should be
able to handle any legal IR.

<rdar://problem/13363576>

llvm-svn: 183544
 2013-06-07 18:36:03 +00:00
Manman Ren
a9cbca5c30 DIBuilder: No functionality change. 
Use the correct DIType when creating types in DIBuilder.

llvm-svn: 183543
 2013-06-07 18:35:53 +00:00
Benjamin Kramer
ed67a770b9 Vincent says the element is at most once in the vector, so we don't need a full std::remove. 
llvm-svn: 183541
 2013-06-07 18:18:12 +00:00
Rafael Espindola
e13931ce6e Use isxdigit. 
Thanks to Benjamin Kramer for the suggestion.

llvm-svn: 183540
 2013-06-07 18:05:03 +00:00
Rafael Espindola
81fff91aac Make operator== non-member for greater symmetry. 
Thanks to David Blaikie for the suggestion.

llvm-svn: 183539
 2013-06-07 18:00:04 +00:00
Roman Divacky
8439b144e6 Fix a typo in asm string of BP* family of instructions. With this fix 
I am able to compile/assemble/link/run /bin/echo from FreeBSD.

llvm-svn: 183537
 2013-06-07 17:46:57 +00:00
Rui Ueyama
8be98a268d [Object/COFF] BaseOfData field should be absent in PE32+. 
llvm-svn: 183534
 2013-06-07 16:58:30 +00:00
Rafael Espindola
7b8382bcbc Support OpenBSD's native frame protection conventions. 
OpenBSD's stack smashing protection differs slightly from other
platforms:

  1. The smash handler function is "__stack_smash_handler(const char
     *funcname)" instead of "__stack_chk_fail(void)".

  2. There's a hidden "long __guard_local" object that gets linked
     into each executable and DSO.

Patch by Matthew Dempsky.

llvm-svn: 183533
 2013-06-07 16:35:57 +00:00
Benjamin Kramer
0c09c2c229 R600: Fix a potential iterator invalidation issue. 
As a bonus this reduces the loop from O(n^2) to O(n).

llvm-svn: 183532
 2013-06-07 16:13:49 +00:00
Vincent Lejeune
016ed40e3b R600: Remove an extra break in R600OptimizeVectorRegisters.cpp 
llvm-svn: 183528
 2013-06-07 15:44:53 +00:00
Alexey Samsonov
07bb3e55fa [llvm-symbolizer] rewrite r183213 in a more clear way 
llvm-svn: 183526
 2013-06-07 15:25:27 +00:00
Benjamin Kramer
2fbc7287e4 BitVector: Do the right thing in all() when Size is a multiple of BITWORD_SIZE. 
llvm-svn: 183525
 2013-06-07 15:14:31 +00:00
Benjamin Kramer
5f752c703f Optimize BitVector::all(). 
llvm-svn: 183521
 2013-06-07 14:14:38 +00:00
Benjamin Kramer
9c60daaa4e Fold variable that's only used in assert into the assert. 
Avoids unused variable warnings in Release builds.

llvm-svn: 183512
 2013-06-07 11:23:35 +00:00
Bill Wendling
d9867ccd7f Add a script to help us create source tar balls for the release. 
llvm-svn: 183509
 2013-06-07 11:15:30 +00:00
Bill Wendling
6ce38e3d9c Use proper exit code. 
llvm-svn: 183508
 2013-06-07 11:14:37 +00:00
Duncan Sands
79aedbb4f5 Correct wrong register in this example, pointed out by Baoshan Pang. 
llvm-svn: 183495
 2013-06-07 08:30:55 +00:00
Bill Wendling
56998a5288 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183494
 2013-06-07 07:55:53 +00:00
Bill Wendling
d6271f8e18 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

llvm-svn: 183493
 2013-06-07 07:04:14 +00:00
Bill Wendling
1ae9358b15 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

llvm-svn: 183492
 2013-06-07 06:30:15 +00:00
Bill Wendling
a5f92e4100 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

llvm-svn: 183491
 2013-06-07 06:26:43 +00:00
Bill Wendling
df29381d34 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

llvm-svn: 183490
 2013-06-07 06:19:56 +00:00
Michael Gottesman
f1426487a9 [objc-arc] Ensure that the cfg path count does not overflow when we multiply TopDownPathCount/BottomUpPathCount. 
rdar://12480535

llvm-svn: 183489
 2013-06-07 06:16:49 +00:00
Bill Wendling
8bc6d84739 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

llvm-svn: 183488
 2013-06-07 05:54:19 +00:00
Bill Wendling
a4eb2d279b Don't cache the instruction info and register info objects. 
These objects are internal to the TargetMachine object and may change.

llvm-svn: 183485
 2013-06-07 05:00:11 +00:00
Manman Ren
177367f799 DIBuilder: No functionality change. 
Use the correct DIType when creating vector types.

llvm-svn: 183484
 2013-06-07 03:13:46 +00:00
Arnold Schwaighofer
ae78fdcfbc ARM sched model: Use the right resources for DIV 
llvm-svn: 183477
 2013-06-07 01:16:15 +00:00
Arnold Schwaighofer
7ab0e93c53 ARM sched model: Add VFP div instruction on Swift 
Reapply 183271.

llvm-svn: 183472
 2013-06-07 01:10:36 +00:00
Arnold Schwaighofer
f006a2373b CodeGenSchedule: Use resize instead of copying a vector 
llvm-svn: 183465
 2013-06-07 00:04:30 +00:00
Arnold Schwaighofer
e735cf9e6d ARM sched model: Add SIMD/VFP load/store instructions on Swift 
Reapply 183270 again (because three is a magic number).

This should now no longer seg fault after r183459.

llvm-svn: 183464
 2013-06-07 00:04:28 +00:00
Venkatraman Govindaraju
867986b1ff [Sparc]: Use cmp instruction instead of subcc to compare integers. 
llvm-svn: 183463
 2013-06-07 00:03:36 +00:00
Jakub Staszak
0c829ecc2b Simplify code. No functionality change. 
llvm-svn: 183461
 2013-06-06 23:34:59 +00:00