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43 Commits

Author SHA1 Message Date
Evan Cheng
239d9b439d Conditional moves are slightly more expensive than moves. 
llvm-svn: 118985
 2010-11-13 05:14:20 +00:00
Evan Cheng
eab7251695 Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. 
llvm-svn: 118160
 2010-11-03 06:34:55 +00:00
Evan Cheng
e156473432 Modify scheduling itineraries to correct instruction latencies (not operand 
latencies) of loads.

llvm-svn: 118134
 2010-11-03 00:40:22 +00:00
Bob Wilson
248c691f9a Add NEON VST1-lane instructions. Partial fix for Radar 8599955. 
llvm-svn: 118069
 2010-11-02 21:18:25 +00:00
Bob Wilson
b6bc135df8 Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. 
llvm-svn: 117964
 2010-11-01 22:04:05 +00:00
Evan Cheng
7695213793 Fix fpscr <-> GPR latency info. 
llvm-svn: 117737
 2010-10-29 23:16:55 +00:00
Evan Cheng
bc4588c439 Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. 
llvm-svn: 117531
 2010-10-28 06:47:08 +00:00
Evan Cheng
fdc80a0316 Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh. 
llvm-svn: 117520
 2010-10-28 02:00:25 +00:00
Evan Cheng
5c358e02ea - Assign load / store with shifter op address modes the right itinerary classes. 
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".

llvm-svn: 117519
 2010-10-28 01:49:06 +00:00
Andrew Trick
4a3b819c1f putback r116983 and fix simple-fp-encoding.ll tests 
llvm-svn: 116992
 2010-10-21 03:40:16 +00:00
Owen Anderson
7da515c665 Revert r116983, which is breaking all the buildbots. 
llvm-svn: 116987
 2010-10-21 03:11:16 +00:00
Evan Cheng
0b9eaaf45d Add missing scheduling itineraries for transfers between core registers and VFP registers. 
llvm-svn: 116983
 2010-10-21 01:12:00 +00:00
Evan Cheng
d07bee932d Limit load / store issues (at least until we have a true multi-issue aware scheduler). 
llvm-svn: 116389
 2010-10-13 01:54:21 +00:00
Evan Cheng
6aac1548ab More ARM scheduling itinerary fixes. 
llvm-svn: 116266
 2010-10-11 23:41:41 +00:00
Evan Cheng
77ba7b098a Proper VST scheduling itineraries. 
llvm-svn: 116251
 2010-10-11 22:03:18 +00:00
Evan Cheng
8c17a06411 Add VLD4 scheduling itineraries. 
llvm-svn: 116143
 2010-10-09 04:07:58 +00:00
Evan Cheng
df7f5672ee Finish vld3 and vld4. 
llvm-svn: 116140
 2010-10-09 01:45:34 +00:00
Evan Cheng
15fc769cf2 Correct some load / store instruction itinerary mistakes: 
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.

llvm-svn: 116134
 2010-10-09 01:03:04 +00:00
Evan Cheng
1ce29574c2 Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc. 
llvm-svn: 115898
 2010-10-07 01:50:48 +00:00
Evan Cheng
6fbb6dea7c - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This 
allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.

llvm-svn: 115755
 2010-10-06 06:27:31 +00:00
Evan Cheng
e8eec016c8 Major changes to Cortex-A9 itinerary. 
1. Model dual issues as two FUs.
2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a
   dependent pipeline on ALU0.
The changes do not have much impact on codegen right now. But I plan to make
pre-RA scheduler multi-issue aware which should take good advantage of the
changes.

llvm-svn: 115457
 2010-10-03 02:03:59 +00:00
Evan Cheng
b068d1483a Fix r115332: correctly model AGU / NEON mux. 
llvm-svn: 115365
 2010-10-01 22:52:29 +00:00
Evan Cheng
cf5ed3cd53 Add operand cycles for vldr / vstr. 
llvm-svn: 115353
 2010-10-01 21:40:30 +00:00
Evan Cheng
fc1aee5b3c NEON scheduling info fix. vmov reg, reg are single cycle instructions. 
llvm-svn: 115344
 2010-10-01 20:50:58 +00:00
Evan Cheng
c7c6c2d04d Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. 
llvm-svn: 115332
 2010-10-01 19:41:46 +00:00
Evan Cheng
fa5d40dbff ARM instruction itinerary fixes: 
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.

llvm-svn: 115121
 2010-09-30 01:08:25 +00:00
Evan Cheng
b44d480808 Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP 
pipeline forwarding path.

llvm-svn: 115098
 2010-09-29 22:42:35 +00:00
Evan Cheng
7eb08b1ad9 Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. 
llvm-svn: 115010
 2010-09-29 00:49:25 +00:00
Evan Cheng
7fffe3cf58 Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub. 
llvm-svn: 115008
 2010-09-29 00:27:46 +00:00
Evan Cheng
39c462b4f1 Add support to model pipeline bypass / forwarding. 
llvm-svn: 115005
 2010-09-28 23:50:49 +00:00
Evan Cheng
b64d587918 Fix IIC_iEXTAr itinerary class of Cortex-A9. 
llvm-svn: 114784
 2010-09-25 01:09:28 +00:00
Evan Cheng
2279dc1d2a Remove a unused instruction itinerary class. 
llvm-svn: 114782
 2010-09-25 01:06:02 +00:00
Evan Cheng
64a24ab747 Fix zero and sign extension instructions scheduling itineraries. 
llvm-svn: 114780
 2010-09-25 00:49:35 +00:00
Evan Cheng
124ae30ef8 More pseudo instruction scheduling itinerary fixes. 
llvm-svn: 114768
 2010-09-24 22:41:41 +00:00
Evan Cheng
eb81dc39dc Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions. 
llvm-svn: 114766
 2010-09-24 22:03:46 +00:00
Evan Cheng
b87520ca74 Fix LDM_RET schedule itinery. 
llvm-svn: 113435
 2010-09-08 22:57:08 +00:00
Jim Grosbach
a0473aa51c minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change. 
llvm-svn: 106988
 2010-06-28 04:27:01 +00:00
Anton Korobeynikov
d8f3fc0f33 Some A9 load/store cleanups 
llvm-svn: 105109
 2010-05-29 19:25:39 +00:00
Anton Korobeynikov
16e9c73153 Some rough approximations for load/stores on A9 
llvm-svn: 105108
 2010-05-29 19:25:34 +00:00
Anton Korobeynikov
fb3252df43 NEON/VFP stuff can be issued only via Pipe1 on A9 
llvm-svn: 105107
 2010-05-29 19:25:29 +00:00
Anton Korobeynikov
ba7aa2f492 Add some integer instruction itineraries for A9 
llvm-svn: 105106
 2010-05-29 19:25:17 +00:00
Anton Korobeynikov
e325c693a5 Make processor FUs unique for given itinerary. This extends the limit of 32 
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

llvm-svn: 101754
 2010-04-18 20:31:01 +00:00
Anton Korobeynikov
51fba0e4eb Split A8/A9 itins - they already were too big. 
llvm-svn: 100672
 2010-04-07 18:22:11 +00:00