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Commit Graph

1273 Commits

Author SHA1 Message Date
Jim Grosbach
9f0533c5d2 ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.

llvm-svn: 136509
2011-07-29 20:26:09 +00:00
Jim Grosbach
1b69dbc796 ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.

llvm-svn: 136479
2011-07-29 18:47:24 +00:00
Jim Grosbach
43e281bec4 ARM update tests for CPS instruction.
llvm-svn: 136472
2011-07-29 17:39:27 +00:00
Jim Grosbach
666e97a0ce CBZ/CBNZ are Thumb2 only. No need for ARM mode tests for them.
llvm-svn: 136408
2011-07-28 21:59:38 +00:00
Jim Grosbach
01d878a4ea ARM assembly parsing and encoding for BLX (immediate).
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.

llvm-svn: 136406
2011-07-28 21:57:55 +00:00
Jim Grosbach
adeee03ea2 Remove obsolete FIXME reference in comment.
llvm-svn: 136400
2011-07-28 21:37:05 +00:00
Jim Grosbach
3bbf68ce6e ARM assembly parsing and encoding for BFC and BFI.
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).

llvm-svn: 136399
2011-07-28 21:34:26 +00:00
Jim Grosbach
2378f8a15e ARM parsing and encoding for ADR.
The label does not have a '#' prefix. Add parsing and encoding tests.

llvm-svn: 136360
2011-07-28 16:33:54 +00:00
Jim Grosbach
68241cddd8 Update ARM tests for parsing and encoding of WFE, WFI and YIELD.
llvm-svn: 136358
2011-07-28 16:00:41 +00:00
Jim Grosbach
992112a797 ARM parsing and encoding tests.
UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.

llvm-svn: 136312
2011-07-28 00:37:03 +00:00
Evan Cheng
04762a3cf5 Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588

llvm-svn: 136292
2011-07-27 23:22:03 +00:00
Jim Grosbach
37586957ee ARM assembly parsing and encoding for USUB16 and USUB8.
llvm-svn: 136289
2011-07-27 23:10:05 +00:00
Jim Grosbach
3e48c1f676 ARM assembly parsing and encoding for USAX.
llvm-svn: 136288
2011-07-27 23:07:00 +00:00
Kevin Enderby
9adbbfffd0 Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
    pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored.  The others remain unchanged.

llvm-svn: 136287
2011-07-27 23:01:50 +00:00
Jim Grosbach
b0bde240c1 Clean up tabs.
llvm-svn: 136286
2011-07-27 22:35:06 +00:00
Jim Grosbach
094803b4d0 ARM assembly parsing and encoding support for USAT and USAT16.
Use range checked immediate operands for instructions. Add tests.

llvm-svn: 136285
2011-07-27 22:34:17 +00:00
Jim Grosbach
e8619cb279 ARM assembly parsing and encoding tests for USAD8 and USADA8.
llvm-svn: 136284
2011-07-27 22:23:02 +00:00
Jim Grosbach
04ab1fa0bc ARM assembly parsing and encoding tests for UQSUB16 and UQSUB8.
llvm-svn: 136282
2011-07-27 22:13:08 +00:00
Jim Grosbach
2c4ea41358 Fix comment copy/paste-o.
llvm-svn: 136281
2011-07-27 22:11:41 +00:00
Jim Grosbach
a91fcf98c9 ARM assembly parsing and encoding tests for UQASX and UQSAX.
llvm-svn: 136280
2011-07-27 22:09:30 +00:00
Jim Grosbach
a85f517680 ARM assembly parsing and encoding tests for UQADD16 and UQADD8.
llvm-svn: 136279
2011-07-27 22:08:14 +00:00
Jim Grosbach
df8040c528 ARM assembly parsing and encoding for UMULL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136277
2011-07-27 22:01:42 +00:00
Jim Grosbach
dd55e1de02 ARM assembly parsing and encoding for UMLAL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136274
2011-07-27 21:58:11 +00:00
Jim Grosbach
f48e465aa5 ARM assembly parsing and encoding tests for UMAAL.
llvm-svn: 136272
2011-07-27 21:53:42 +00:00
Jim Grosbach
91f7d83f9c ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8.
llvm-svn: 136267
2011-07-27 21:21:59 +00:00
Jim Grosbach
6f34be1f69 ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX.
llvm-svn: 136266
2011-07-27 21:20:45 +00:00
Jim Grosbach
c5cd3228c4 ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].

llvm-svn: 136264
2011-07-27 21:09:25 +00:00
Jim Grosbach
8393f12ec5 ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX.
llvm-svn: 136261
2011-07-27 20:43:44 +00:00
Jim Grosbach
1f818d0f25 ARM assembly parsing and encoding tests for TST instruction.
llvm-svn: 136260
2011-07-27 20:38:58 +00:00
Jim Grosbach
e74be6ad39 ARM assembly parsing and encoding tests for TEQ instruction.
llvm-svn: 136259
2011-07-27 20:37:36 +00:00
Owen Anderson
d2cd33b911 Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
llvm-svn: 136255
2011-07-27 20:29:48 +00:00
Jim Grosbach
624acaffd7 ARM assembly parsing and encoding for extend instructions.
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.

llvm-svn: 136252
2011-07-27 20:15:40 +00:00
Jim Grosbach
8e642b2b18 ARM diagnostics for ldrexd/stredx out of order paired register operands.
llvm-svn: 136110
2011-07-26 18:25:39 +00:00
Jim Grosbach
7b56b1cf0e ARM parsing and encoding tests for load/store exclusive instructions.
llvm-svn: 136105
2011-07-26 18:07:21 +00:00
Jim Grosbach
6fbee17fef ARM assembly parsing and encoding for SWP[B] instructions.
llvm-svn: 136098
2011-07-26 17:15:11 +00:00
Jim Grosbach
d3152480f2 ARM parsing and encoding for SVC instruction.
llvm-svn: 136090
2011-07-26 16:24:27 +00:00
Jim Grosbach
422ac2fc64 ARM assembly parsing and encoding tests for SUB instruction.
llvm-svn: 136089
2011-07-26 15:44:05 +00:00
Jim Grosbach
3efad526c2 Update ARM STM tests. Fix check: prefix for diagnostic tests.
llvm-svn: 136088
2011-07-26 15:41:22 +00:00
Jim Grosbach
41a5cd3fa2 ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8.
llvm-svn: 136013
2011-07-25 23:32:14 +00:00
Jim Grosbach
ef3d573e31 ARM assembly parsing and encoding for SSAT16 instruction.
llvm-svn: 136006
2011-07-25 23:09:14 +00:00
Jim Grosbach
c1fe042da0 ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').

Add tests for diagnostics and proper encoding.

llvm-svn: 135990
2011-07-25 22:20:28 +00:00
Jim Grosbach
2f728674cf Move some ELF directives into ELF asm parser.
The .local, .hidden, .internal, and .protected are not legal for all supported
file formats (in particular, they're invalid for MachO). Move the parsing for
them into the ELF assembly parser since that's the format they're for.
Similarly, .weak is used by COFF and ELF, but not MachO, so move the parsing
to the COFF and ELF asm parsers. Previously, using any of these directives
on Darwin would result in an assertion failure in the parser; now we get
a diagnostic as we should.

rdar://9827089

llvm-svn: 135921
2011-07-25 17:55:35 +00:00
Jim Grosbach
0bfa6a6db7 Add FIXME
llvm-svn: 135819
2011-07-22 22:15:38 +00:00
Jim Grosbach
daf04c88c2 ARM encoding and assembly parsing tests for SMULWB, SMULWT, SMUSD and SMUSDX.
llvm-svn: 135818
2011-07-22 22:13:00 +00:00
Jim Grosbach
a7a6658647 ARM assembly parsing and encoding updates.
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.

llvm-svn: 135817
2011-07-22 22:06:05 +00:00
Jim Grosbach
1e724e3217 ARM assembly parsing and encoding tests.
Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,
SMMUL, SMMULR, SMUAD and SMUADX.

llvm-svn: 135810
2011-07-22 21:34:56 +00:00
Jim Grosbach
f7780d14ce ARM assembly parsing and encoding tests for SMLAWB/SMLAWT.
llvm-svn: 135800
2011-07-22 20:51:24 +00:00
Jim Grosbach
7ee1e3dc6c ARM assembly parsing and encoding tests.
Tests for SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, and SMLALDX
instructions.

llvm-svn: 135798
2011-07-22 20:30:40 +00:00
Jim Grosbach
9ffa43becc ARM assembly parsing and encoding of SMLAL instruction.
Fix parsing of carry-setting variant SMLALS and add tests.

llvm-svn: 135797
2011-07-22 20:18:21 +00:00
Jim Grosbach
4f1031662f ARM encoding and assembly parsing of SMLAD{X} instructions.
Fix encoding of destination register. Add tests.

llvm-svn: 135796
2011-07-22 20:11:20 +00:00