1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-02 00:42:52 +01:00
Commit Graph

395 Commits

Author SHA1 Message Date
Dan Gohman
13d1327796 Factor the addressing mode and the load/store VT out of LoadSDNode
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.

llvm-svn: 46538
2008-01-30 00:15:11 +00:00
Scott Michel
dc780aeb57 Overhaul Cell SPU's addressing mode internals so that there are now
only two addressing mode nodes, SPUaform and SPUindirect (vice the
three previous ones, SPUaform, SPUdform and SPUxform). This improves
code somewhat because we now avoid using reg+reg addressing when
it can be avoided. It also simplifies the address selection logic,
which was the main point for doing this.

Also, for various global variables that would be loaded using SPU's
A-form addressing, prefer D-form offs[reg] addressing, keeping the
base in a register if the variable is used more than once.

llvm-svn: 46483
2008-01-29 02:16:57 +00:00
Scott Michel
506e61bad1 Forward progress: crtbegin.c now compiles successfully!
Fixed CellSPU's A-form (local store) address mode, so that all globals,
externals, constant pool and jump table symbols are now wrapped within
a SPUISD::AFormAddr pseudo-instruction. This now identifies all local
store memory addresses, although it requires a bit of legerdemain during
instruction selection to properly select loads to and stores from local
store, properly generating "LQA" instructions.

Also added mul_ops.ll test harness for exercising integer multiplication.

llvm-svn: 46142
2008-01-17 20:38:41 +00:00
Chris Lattner
41717f6989 This commit changes:
1. Legalize now always promotes truncstore of i1 to i8. 
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
   X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
   safe.

The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:

_foo:
	fldt	20(%esp)
	fldt	4(%esp)
	faddp	%st(1)
	movl	36(%esp), %eax
	fstps	(%eax)
	ret

instead of:

_foo:
	subl	$4, %esp
	fldt	24(%esp)
	fldt	8(%esp)
	faddp	%st(1)
	fstps	(%esp)
	movl	40(%esp), %eax
	movss	(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$4, %esp
	ret

llvm-svn: 46140
2008-01-17 19:59:44 +00:00
Chris Lattner
6846e346a8 rename SDTRet -> SDTNone.
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.

llvm-svn: 46017
2008-01-15 22:02:54 +00:00
Chris Lattner
7fa87a190a improve cygwin compatibility, patch by Sam Bishop
llvm-svn: 45917
2008-01-12 22:54:07 +00:00
Scott Michel
5afa19350b More CellSPU refinements:
- struct_2.ll: Completely unaligned load/store testing

- call_indirect.ll, struct_1.ll: Add test lines to exercise
   X-form [$reg($reg)] addressing

At this point, loads and stores should be under control (he says
in an optimistic tone of voice.)

llvm-svn: 45882
2008-01-11 21:01:19 +00:00
Scott Michel
1e9496e4d4 More CellSPU refinement and progress:
- Cleaned up custom load/store logic, common code is now shared [see note
  below], cleaned up address modes

- More test cases: various intrinsics, structure element access (load/store
  test), updated target data strings, indirect function calls.

Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode
structures: they now share a common base class, LSBaseSDNode, that
provides an interface to their common functionality. There is some hackery
to access the proper operand depending on the derived class; otherwise,
to do a proper job would require finding and rearranging the SDOperands
sent to StoreSDNode's constructor. The current refactor errs on the
side of being conservatively and backwardly compatible while providing
functionality that reduces redundant code for targets where loads and
stores are custom-lowered.

llvm-svn: 45851
2008-01-11 02:53:15 +00:00
Chris Lattner
4421b821f5 no need to explicitly clear these fields.
llvm-svn: 45683
2008-01-07 04:55:09 +00:00
Chris Lattner
55343065e3 remove MachineOpCode typedef.
llvm-svn: 45679
2008-01-07 02:48:55 +00:00
Owen Anderson
f19692b2f6 Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over...

llvm-svn: 45672
2008-01-07 01:35:02 +00:00
Chris Lattner
14310afe42 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
llvm-svn: 45667
2008-01-06 23:38:27 +00:00
Chris Lattner
8b4b75c771 Change the 'isStore' inferrer to look for 'SDNPMayStore'
instead of "ISD::STORE".  This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores).  This allows us to remove
more explicit isStore flags from the .td files.

Finally, add a warning for when a .td file contains an explicit 
isStore and tblgen is able to infer it.

llvm-svn: 45654
2008-01-06 06:44:58 +00:00
Owen Anderson
e6856128ab Move some more instruction creation methods from RegisterInfo into InstrInfo.
llvm-svn: 45484
2008-01-01 21:11:32 +00:00
Chris Lattner
1285ec2ae7 Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen.  This violates a layering order: codegen
depends on target, not the other way around.  The fix to this is to 
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen.  It is defined in libcodegen, where 
the base is not.

llvm-svn: 45475
2008-01-01 01:03:04 +00:00
Owen Anderson
ae7e2c1e03 Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.

llvm-svn: 45470
2007-12-31 06:32:00 +00:00
Chris Lattner
96167aa93c Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.

llvm-svn: 45467
2007-12-31 04:13:23 +00:00
Chris Lattner
9e5cc35593 Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock().  I don't plan on 
switching everything over, so new clients should just start using the 
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(), 
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.

llvm-svn: 45464
2007-12-30 23:10:15 +00:00
Chris Lattner
12477d46b4 Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
llvm-svn: 45453
2007-12-30 20:49:49 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Chris Lattner
8193d4af33 remove attribution from lib Makefiles.
llvm-svn: 45415
2007-12-29 20:09:26 +00:00
Chris Lattner
a2156b160a fix some warnings. This code needs to be de-tabified :(
llvm-svn: 45325
2007-12-22 22:47:03 +00:00
Chris Lattner
1c6a1f71cb fix strict-aliasing violation
llvm-svn: 45324
2007-12-22 22:45:38 +00:00
Scott Michel
5cbdbd26a8 More working CellSPU tests:
- vec_const.ll: Vector constant loads
- immed64.ll: i64, f64 constant loads

llvm-svn: 45242
2007-12-20 00:44:13 +00:00
Scott Michel
83ac96e27d CellSPU testcase, extract_elt.ll: extract vector element.
llvm-svn: 45219
2007-12-19 21:17:42 +00:00
Scott Michel
6cb9f6d20c Two more test cases: or_ops.ll (arithmetic or operations) and vecinsert.ll
(vector insertions)

llvm-svn: 45216
2007-12-19 20:15:47 +00:00
Scott Michel
d4d96bb6f6 Add new immed16.ll test case, fix CellSPU errata to make test case work.
llvm-svn: 45196
2007-12-19 07:35:06 +00:00
Scott Michel
4f980e1acd - Restore some i8 functionality in CellSPU
- New test case: nand.ll

llvm-svn: 45130
2007-12-17 22:32:34 +00:00
Chris Lattner
5e2b033d30 don't violate C TBAA rules, use FloatToBits instead.
llvm-svn: 45076
2007-12-16 20:41:33 +00:00
Scott Michel
307f334014 Start committing working test cases for CellSPU.
llvm-svn: 45050
2007-12-15 00:38:50 +00:00
Scott Michel
a9a40d4347 Minor updates:
- Fix typo in SPUCallingConv.td
- Credit myself for CellSPU work
- Add CellSPU to 'all' host target list

llvm-svn: 44627
2007-12-05 21:23:16 +00:00
Evan Cheng
aecb76bcc2 Update foldMemoryOperand.
llvm-svn: 44621
2007-12-05 18:36:37 +00:00
Chris Lattner
0914ad3008 fix warnings
llvm-svn: 44620
2007-12-05 18:32:18 +00:00
Chris Lattner
df5cd03710 allow this to build
llvm-svn: 44619
2007-12-05 18:30:11 +00:00
Evan Cheng
8464a0bf00 Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
the stored register is killed.

llvm-svn: 44600
2007-12-05 03:14:33 +00:00
Scott Michel
871b3a4fd4 More stuff for CellSPU -- this should be enough to get an error-free
compilation (no files missing). Test cases remain to be checked in.

llvm-svn: 44598
2007-12-05 02:01:41 +00:00
Scott Michel
8a2cb11b05 Updated source file headers to llvm coding standard.
llvm-svn: 44597
2007-12-05 01:40:25 +00:00
Scott Michel
026ace10b2 Two missing files.
llvm-svn: 44596
2007-12-05 01:31:18 +00:00
Scott Michel
191775d31f Main CellSPU backend files checked in. Intrinsics and autoconf files
remain.

llvm-svn: 44595
2007-12-05 01:24:05 +00:00
Scott Michel
512cb025cc More files in the CellSPU drop...
llvm-svn: 44584
2007-12-04 22:35:58 +00:00
Scott Michel
774da2e74c More of the Cell SPU code drop from "Team Aerospace".
llvm-svn: 44582
2007-12-04 22:23:35 +00:00
Scott Michel
3996f647d2 More CellSPU files... more to follow.
llvm-svn: 44559
2007-12-03 23:14:43 +00:00
Scott Michel
c312b999e6 Makefile fragment for CellSPU.
llvm-svn: 44558
2007-12-03 23:12:49 +00:00
Scott Michel
34987128e0 First commit to CellSPU. More to follow
llvm-svn: 44557
2007-12-03 23:09:49 +00:00
Scott Michel
ae7090641f First test check-in.
llvm-svn: 35429
2007-03-28 17:04:43 +00:00