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3507 Commits

Author SHA1 Message Date
Evan Cheng
b7ec9433b3 Re-materialize all loads from fixed stack slots. 
llvm-svn: 35660
 2007-04-04 07:40:01 +00:00
Evan Cheng
48b94106d6 Trivially re-materializable instructions have spill weights that are half of what it would be otherwise. 
llvm-svn: 35658
 2007-04-04 07:04:55 +00:00
Evan Cheng
bad40843ec Bad bad bug. findRegisterUseOperand() returns -1 if a use if not found. 
llvm-svn: 35618
 2007-04-03 06:43:29 +00:00
Scott Michel
d6b3d3d6ab 1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL. 
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.

llvm-svn: 35605
 2007-04-02 21:36:32 +00:00
Evan Cheng
d0366b0024 Ugh. Copy coalescer does not update register numbers. 
llvm-svn: 35600
 2007-04-02 18:49:18 +00:00
Reid Spencer
419407379c For PR1297: 
Make sure that the CTPOP result is casted to i32 as the bit counting
intrinsics all return i32 now (this affects CTLZ and CTTZ as well).

llvm-svn: 35567
 2007-04-02 01:01:49 +00:00
Reid Spencer
88fb617695 For PR1297: 
Support overloaded intrinsics bswap, ctpop, cttz, ctlz.

llvm-svn: 35547
 2007-04-01 07:35:23 +00:00
Reid Spencer
4a28a16efb For PR1297: 
Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.

llvm-svn: 35546
 2007-04-01 07:34:11 +00:00
Reid Spencer
77c46f6cf5 For PR1297: 
Change getOperationName to return std::string instead of const char*

llvm-svn: 35545
 2007-04-01 07:32:19 +00:00
Chris Lattner
f01b0a800b move a bunch of code out of the sdisel pass into its own opt pass "codegenprepare". 
llvm-svn: 35529
 2007-03-31 04:18:03 +00:00
Chris Lattner
8747705792 switch TL::getValueType to use MVT::getValueType. 
llvm-svn: 35527
 2007-03-31 04:05:24 +00:00
Chris Lattner
330464a91c Add a -print-lsr-output option to LLC, to print the output of the LSR pass. 
llvm-svn: 35522
 2007-03-31 00:24:43 +00:00
Chris Lattner
143464e05f add one addressing mode description hook to rule them all. 
llvm-svn: 35520
 2007-03-30 23:14:50 +00:00
Dale Johannesen
d4ab7d28e9 Fix incorrect combination of different loads. Reenable zext-over-truncate 
combination.

llvm-svn: 35517
 2007-03-30 21:38:07 +00:00
Evan Cheng
d814ad9d50 Don't add the same MI to register reuse "last def/use" twice if it reads the 
register more than once.

llvm-svn: 35513
 2007-03-30 20:21:35 +00:00
Evan Cheng
fc6519b457 Bug fix for PR1279. When isDead is propagate by copy coalescing, we keep length 
of dead def live interval at 1 to avoid multiple def's targeting the same
register. The previous patch missed a case where the source operand is live-in.
In that case, remove the whole interval.

llvm-svn: 35512
 2007-03-30 20:18:35 +00:00
Evan Cheng
2d09850760 Disable load width reduction xform of variant (zext (truncate load x)) for 
big endian targets until llvm-gcc build issue has been resolved.

llvm-svn: 35449
 2007-03-29 07:56:46 +00:00
Evan Cheng
a72a3b7a74 New entries. 
llvm-svn: 35445
 2007-03-29 02:48:56 +00:00
Evan Cheng
29fcdd1b2f Notes on re-materialization. 
llvm-svn: 35420
 2007-03-28 08:30:04 +00:00
Evan Cheng
13037fbfb4 Move rematerialization out of beta. 
llvm-svn: 35419
 2007-03-28 08:26:40 +00:00
Evan Cheng
13cc34e91b Scale 1 is always ok. 
llvm-svn: 35407
 2007-03-28 01:55:52 +00:00
Evan Cheng
a55449c051 Remove isLegalAddressImmediate. 
llvm-svn: 35406
 2007-03-28 01:53:55 +00:00
Evan Cheng
6056fd729d GEP index sinking fixes: 
1) Take address scale into consideration. e.g. i32* -> scale 4.
2) Examine all the users of GEP.
3) Generalize to inter-block GEP's (no longer uses loopinfo).
4) Don't do xform if GEP has other variable index(es).

llvm-svn: 35403
 2007-03-28 01:49:39 +00:00
Evan Cheng
a182608846 Fix for PR1279. Dead def has a live interval of length 1. Copy coalescing should 
not violate that.

llvm-svn: 35396
 2007-03-28 01:30:37 +00:00
Anton Korobeynikov
64622a0ddf Remove dead code 
llvm-svn: 35380
 2007-03-27 12:05:48 +00:00
Anton Korobeynikov
b58a93156f Split big monster into small helpers. No functionality change. 
llvm-svn: 35379
 2007-03-27 11:29:11 +00:00
Evan Cheng
7218d782fe SDISel does not preserve all, it changes CFG and other info. 
llvm-svn: 35376
 2007-03-27 00:53:36 +00:00
Evan Cheng
c81bdb4100 Don't call getOperandConstraint() if operand index is greater than 
TID->numOperands.

llvm-svn: 35375
 2007-03-27 00:48:28 +00:00
Evan Cheng
0ff19780f9 Fix for PR1266. Don't mark a two address operand IsKill. 
llvm-svn: 35365
 2007-03-26 22:40:42 +00:00
Evan Cheng
201771637e Change findRegisterUseOperand() to return operand index instead. 
llvm-svn: 35363
 2007-03-26 22:37:45 +00:00
Dale Johannesen
3ad8ab7b61 Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable to 
hopefully forestall similar errors.

llvm-svn: 35362
 2007-03-26 22:23:54 +00:00
Evan Cheng
5b1c21d27b SIGN_EXTEND_INREG requires one extra operand, a ValueType node. 
llvm-svn: 35350
 2007-03-26 07:12:51 +00:00
Anton Korobeynikov
6f78c59650 First step of switch lowering refactoring: perform worklist-driven 
strategy, emit JT's where possible.

llvm-svn: 35338
 2007-03-25 15:07:15 +00:00
Chris Lattner
6f17a615cb Implement support for vector operands to inline asm, implementing 
CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll

llvm-svn: 35332
 2007-03-25 05:00:54 +00:00
Chris Lattner
4a7feb72f5 implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll 
llvm-svn: 35327
 2007-03-25 04:35:41 +00:00
Chris Lattner
91adfbe0ff Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll 
llvm-svn: 35324
 2007-03-25 02:18:14 +00:00
Chris Lattner
b19069959d switch TargetLowering::getConstraintType to take the entire constraint, 
not just the first letter.  No functionality change.

llvm-svn: 35322
 2007-03-25 02:14:49 +00:00
Chris Lattner
57d0c197e6 don't rely on ADL 
llvm-svn: 35299
 2007-03-24 17:37:03 +00:00
Evan Cheng
a484f31d4b Adjust offset to compensate for big endian machines. 
llvm-svn: 35293
 2007-03-24 00:02:43 +00:00
Evan Cheng
84aecc56e7 Make sure SEXTLOAD of the specific type is supported on the target. 
llvm-svn: 35289
 2007-03-23 22:13:36 +00:00
Evan Cheng
7dd7666120 Also replace uses of SRL if that's also folded during ReduceLoadWidth(). 
llvm-svn: 35286
 2007-03-23 20:55:21 +00:00
Evan Cheng
62ccdaea67 A couple of bug fixes for reducing load width xform: 
1. Address offset is in bytes.
2. Make sure truncate node uses are replaced with new load.

llvm-svn: 35274
 2007-03-23 02:16:52 +00:00
Dan Gohman
d0a0ea9916 Change uses of Function::front to Function::getEntryBlock for readability. 
llvm-svn: 35265
 2007-03-22 16:38:57 +00:00
Evan Cheng
d7be4893f4 More opportunities to reduce load size. 
llvm-svn: 35254
 2007-03-22 01:54:19 +00:00
Evan Cheng
da92165bab Fix for PR1257. Bug in live range shortening as a result of copy coalescing 
where the destination is dead.

llvm-svn: 35252
 2007-03-22 01:26:05 +00:00
Dale Johannesen
44c0a5d545 repair x86 performance, dejagnu problems from previous change 
llvm-svn: 35245
 2007-03-21 21:51:52 +00:00
Evan Cheng
9867632e64 fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits)) 
llvm-svn: 35239
 2007-03-21 20:14:05 +00:00
Evan Cheng
516a83595d Potential spiller improvement. 
llvm-svn: 35228
 2007-03-20 22:22:38 +00:00
Dale Johannesen
3e422e3b49 do not share old induction variables when this would result in invalid 
instructions (that would have to be split later)

llvm-svn: 35227
 2007-03-20 21:54:54 +00:00
Dale Johannesen
50a22f6fe6 maintain LiveIn when splitting blocks (register scavenging needs it) 
llvm-svn: 35226
 2007-03-20 21:35:06 +00:00