RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 20:23:11 +01:00
Code Issues Projects Releases Wiki Activity
59,429 Commits 4 Branches 5 Tags 704 MiB
a58082f349
Commit Graph

37678 Commits

Author SHA1 Message Date
Chris Lattner
a58082f349 add newlines at end of files. 
llvm-svn: 100706
 2010-04-07 22:54:55 +00:00
Chris Lattner
0768c834fe remove some unneeded errorhandling stuff. 
llvm-svn: 100703
 2010-04-07 22:44:07 +00:00
Chris Lattner
f927d33d8c minor tidying up 
llvm-svn: 100702
 2010-04-07 22:41:29 +00:00
Chris Lattner
cc827ee016 tidy up 
llvm-svn: 100700
 2010-04-07 22:29:10 +00:00
Dan Gohman
b5210c934f Generalize IVUsers to track arbitrary expressions rather than expressions 
explicitly split into stride-and-offset pairs. Also, add the
ability to track multiple post-increment loops on the same expression.

This refines the concept of "normalizing" SCEV expressions used for
to post-increment uses, and introduces a dedicated utility routine for
normalizing and denormalizing expressions.

This fixes the expansion of expressions which are post-increment users
of more than one loop at a time. More broadly, this takes LSR another
step closer to being able to reason about more than one loop at a time.

llvm-svn: 100699
 2010-04-07 22:27:08 +00:00
Johnny Chen
b024d0a612 Missed this one line for the previous checkin to fix build warnings. 
llvm-svn: 100697
 2010-04-07 22:21:03 +00:00
Johnny Chen
9fdf028fd3 Fixed warnings pointed out by clang. 
llvm-svn: 100696
 2010-04-07 22:03:27 +00:00
Johnny Chen
16c0653745 Fixed warnings pointed out by clang. 
Next to work on is ARMDisassemblerCore.cpp.

llvm-svn: 100695
 2010-04-07 21:52:48 +00:00
Sean Callanan
3c69c6593a Fixed a bug where the disassembler would allow an immediate 
argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter.  Now, the
disassembler rejects instructions with out-of-range values
for that immediate.

llvm-svn: 100694
 2010-04-07 21:42:19 +00:00
Johnny Chen
4dc93f2195 Fixed 3 warnings pointed out by clang. 
llvm-svn: 100693
 2010-04-07 21:23:48 +00:00
Johnny Chen
2c992fb384 Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in 
ARMDecoderEmitter.cpp, with FIXME comment.

llvm-svn: 100690
 2010-04-07 20:53:12 +00:00
Sean Callanan
8ac8cf3f10 Added an AsmLexer for the ARM target, which uses 
a simple mapping of register names to IDs to
identify register tokens.

llvm-svn: 100685
 2010-04-07 20:29:34 +00:00
Dale Johannesen
8691bcbc2a Educate GetInstrSizeInBytes implementations that 
DBG_VALUE does not generate code.

llvm-svn: 100681
 2010-04-07 19:51:44 +00:00
Gabor Greif
f2480270e1 fix 80-col violations 
llvm-svn: 100677
 2010-04-07 18:59:26 +00:00
Anton Korobeynikov
e5c1563130 Remove late ARM codegen optimization pass committed by accident. 
It is not ready for public yet.

llvm-svn: 100673
 2010-04-07 18:23:27 +00:00
Anton Korobeynikov
51fba0e4eb Split A8/A9 itins - they already were too big. 
llvm-svn: 100672
 2010-04-07 18:22:11 +00:00
Anton Korobeynikov
7d6384b376 Add some crude itin approximation for VFP load / stores on A9 
llvm-svn: 100671
 2010-04-07 18:22:03 +00:00
Anton Korobeynikov
f2a19a64d1 Add some crude approximation for neon load/store instructions 
llvm-svn: 100670
 2010-04-07 18:21:58 +00:00
Anton Korobeynikov
1bd6022529 Add some A8-based approximation for instructions with unknown cycle times 
llvm-svn: 100669
 2010-04-07 18:21:52 +00:00
Anton Korobeynikov
51d00a7f48 Move NEON-VFP domain fixer upper, so post-RA scheduler would benefit from it. 
llvm-svn: 100668
 2010-04-07 18:21:46 +00:00
Anton Korobeynikov
0401f43ddc Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore. 
llvm-svn: 100667
 2010-04-07 18:21:41 +00:00
Anton Korobeynikov
cdb0066e5f Fix A8 FP NEON MAC itins 
llvm-svn: 100666
 2010-04-07 18:21:33 +00:00
Anton Korobeynikov
a63bb55ad7 A9 NEON FP itins 
llvm-svn: 100665
 2010-04-07 18:21:27 +00:00
Anton Korobeynikov
d2770462d1 Some permute goodness for A9 
llvm-svn: 100664
 2010-04-07 18:21:22 +00:00
Anton Korobeynikov
4eb354a908 More shift itins for A9 
llvm-svn: 100663
 2010-04-07 18:21:16 +00:00
Anton Korobeynikov
f9463f5b98 More fixes for itins 
llvm-svn: 100662
 2010-04-07 18:21:10 +00:00
Anton Korobeynikov
0c3bc7a9ce Fix invalid itins for 32-bit varians of VMLAL and friends 
llvm-svn: 100661
 2010-04-07 18:21:04 +00:00
Anton Korobeynikov
103c4e9803 Add MAC stuff for A9 
llvm-svn: 100660
 2010-04-07 18:20:58 +00:00
Anton Korobeynikov
bca57ef16b Fix invalid NEON MAC itins on A8 
llvm-svn: 100659
 2010-04-07 18:20:53 +00:00
Anton Korobeynikov
dce0e2a918 Fix itins for VPAL 
llvm-svn: 100658
 2010-04-07 18:20:47 +00:00
Anton Korobeynikov
be68ff5b2c Fix itins for VABA 
llvm-svn: 100657
 2010-04-07 18:20:42 +00:00
Anton Korobeynikov
fbc58bba2f Correct VMVN itinerary: operand is read in the second cycle, not in the first. 
llvm-svn: 100656
 2010-04-07 18:20:36 +00:00
Anton Korobeynikov
2abd52b692 More A9 itineraries 
llvm-svn: 100655
 2010-04-07 18:20:29 +00:00
Anton Korobeynikov
13df6eaf1c Correct itinerary class for VPADD 
llvm-svn: 100654
 2010-04-07 18:20:24 +00:00
Anton Korobeynikov
982f9a042b VP{MAX, MIN} are of IIC_VSUBi4D itin class as well. 
llvm-svn: 100653
 2010-04-07 18:20:18 +00:00
Anton Korobeynikov
058984f2a8 VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP. 
llvm-svn: 100652
 2010-04-07 18:20:13 +00:00
Anton Korobeynikov
e8688b87a4 Some easy NEON scheduling goodness for A9 
llvm-svn: 100651
 2010-04-07 18:20:07 +00:00
Anton Korobeynikov
7339733c80 Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :( 
llvm-svn: 100650
 2010-04-07 18:20:02 +00:00
Anton Korobeynikov
5ab38590b2 FCONST{S,D} behaves the same way as FP unary instructions. This is true for both A8 and A9. 
llvm-svn: 100649
 2010-04-07 18:19:56 +00:00
Anton Korobeynikov
7c19b34d69 Proper cycle times for locks, since wbck latency can be larger than fwd latency. 
llvm-svn: 100648
 2010-04-07 18:19:51 +00:00
Anton Korobeynikov
5954edc79b Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9. 
llvm-svn: 100647
 2010-04-07 18:19:46 +00:00
Anton Korobeynikov
b68aa8b5ab Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly. 
llvm-svn: 100646
 2010-04-07 18:19:40 +00:00
Anton Korobeynikov
f93145e685 Initial support for different kinds of FU reservation. 
llvm-svn: 100645
 2010-04-07 18:19:32 +00:00
Anton Korobeynikov
bf7bbe3e94 Factor out scoreboard into separate class. This way we might have several different score boards. 
llvm-svn: 100644
 2010-04-07 18:19:24 +00:00
Anton Korobeynikov
7a3b393469 Some bits of A9 scheduling: VFP 
llvm-svn: 100643
 2010-04-07 18:19:18 +00:00
Anton Korobeynikov
a2b6818832 Separate const from non-const stuff during mergeing 
llvm-svn: 100642
 2010-04-07 18:19:13 +00:00
Anton Korobeynikov
aa8b0d11a5 Some initial version of global merger 
llvm-svn: 100641
 2010-04-07 18:19:07 +00:00
Anton Korobeynikov
d873a16430 Add hook to insert late LLVM=>LLVM passes just before isel 
llvm-svn: 100640
 2010-04-07 18:18:42 +00:00
Chris Lattner
f520500a06 fix 80 col violation, patch by Alastair Lynn 
llvm-svn: 100639
 2010-04-07 18:13:33 +00:00
Chris Lattner
7816ae8fd0 add a comment line that got dropped 
llvm-svn: 100638
 2010-04-07 18:10:38 +00:00