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47981 Commits

Author SHA1 Message Date
Jim Grosbach
a58c6a0c37 Fix off-by-one error. 
(low two bits always zero, so off by one bit of encoded value).

llvm-svn: 134247
 2011-07-01 19:07:09 +00:00
Evan Cheng
157d40fba1 Hide the call to InitMCInstrInfo into tblgen generated ctor. 
llvm-svn: 134244
 2011-07-01 17:57:27 +00:00
Jim Grosbach
48ec24b950 Pseudo-ize t2MOVCC[ri]. 
t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them.
The Thumb1 versions, tMOVCC[ri] were only present for use by the size-
reduction pass, so they're no longer necessary at all and can be deleted.

llvm-svn: 134242
 2011-07-01 17:14:11 +00:00
Evan Cheng
a4b2c3d5ba Eliminate one extra conversion. 
llvm-svn: 134240
 2011-07-01 16:59:30 +00:00
Duncan Sands
cfea0dd707 Disable commit 134216 ("Add 134199 back, but disable the optimization when the second 
copy is a kill") to see if it fixes the i386 dragonegg buildbot, which is timing out
because gcc built with dragonegg is going into an infinite loop.

llvm-svn: 134237
 2011-07-01 12:01:00 +00:00
Francois Pichet
f143a222d0 Another misuse of StringRef. MSVC is very sensitive to that kind of error. 
llvm-svn: 134236
 2011-07-01 09:23:41 +00:00
Nick Lewycky
465651fe6e Fix likely typo, reduce number of instruction name collisions. 
llvm-svn: 134235
 2011-07-01 06:27:03 +00:00
Rafael Espindola
018ca8fea8 Fix use after free. 
llvm-svn: 134234
 2011-07-01 04:40:50 +00:00
Rafael Espindola
ac24a57bdb Avoid DenseMap lookup. 
llvm-svn: 134231
 2011-07-01 04:15:02 +00:00
Rafael Espindola
0b7dda94fb Fix off by one error. I misunderstood the comment about killedAt. 
llvm-svn: 134229
 2011-07-01 03:31:29 +00:00
Rafael Espindola
0a0153608f Check the liveinterval, not the kill flag. 
llvm-svn: 134228
 2011-07-01 02:35:06 +00:00
Jakob Stoklund Olesen
20986ee7bb Don't inflate register classes used by inline asm. 
The constraints are represented by the register class of the original
virtual register created for the inline asm. If the register class were
included in the operand descriptor, we might be able to do this.

For now, just give up on regclass inflation when inline asm is involved.

No test case, this bug hasn't happened yet.

llvm-svn: 134226
 2011-07-01 01:24:25 +00:00
Akira Hatanaka
960f6898a6 Improve Mips back-end's handling of DBG_VALUE. 
llvm-svn: 134224
 2011-07-01 01:04:43 +00:00
Dan Gohman
ba1afd789e Improve constant folding of undef for cmp and select operators. 
llvm-svn: 134223
 2011-07-01 01:03:43 +00:00
Eric Christopher
d369a9fe83 Add support for the 'j' immediate constraint. This is conditionalized on 
supporting the instruction that the constraint is for 'movw'.

Part of rdar://9119939

llvm-svn: 134222
 2011-07-01 01:00:07 +00:00
Dan Gohman
b4be67ddb0 Improve constant folding of undef for binary operators. 
llvm-svn: 134221
 2011-07-01 00:42:17 +00:00
Eric Christopher
4bc6b7e1a6 Add support for the ARM 't' register constraint. And another testcase 
for the 'x' register constraint.

Part of rdar://9119939

llvm-svn: 134220
 2011-07-01 00:30:46 +00:00
Evan Cheng
1fa6460e3f Switch SubtargetFeatures from std::string to StringRef. 
llvm-svn: 134219
 2011-07-01 00:23:10 +00:00
Eric Christopher
aec0b9ae1f We'll return a null RC by default if we can't match. 
Part of rdar://9119939

llvm-svn: 134217
 2011-07-01 00:19:27 +00:00
Rafael Espindola
c09ce29b8b Add 134199 back, but disable the optimization when the second copy is a kill. 
llvm-svn: 134216
 2011-07-01 00:16:54 +00:00
Eric Christopher
d40f06b48f Add support for the 'x' constraint. 
Part of rdar://9307836 and rdar://9119939

llvm-svn: 134215
 2011-07-01 00:14:47 +00:00
Bill Wendling
770794cc60 Remove tabs. 
llvm-svn: 134212
 2011-06-30 23:59:38 +00:00
Eric Christopher
cf52a1d739 Capitalize the unsigned part of the initializer. 
llvm-svn: 134211
 2011-06-30 23:59:16 +00:00
Eric Christopher
c0f8984efa Rename Pair to RCPair lacking any better naming ideas. 
llvm-svn: 134210
 2011-06-30 23:50:52 +00:00
Bill Wendling
995ebcfd4c Improve comment: Show the register the DWARF label is added to. 
llvm-svn: 134209
 2011-06-30 23:47:40 +00:00
Bill Wendling
6aa9fb80dc Use the correct registers on X86_64. 
llvm-svn: 134208
 2011-06-30 23:47:14 +00:00
Jakob Stoklund Olesen
8b22811785 Fix a problem with fast-isel return values introduced in r134018. 
We would put the return value from long double functions in the wrong
register.

This fixes gcc.c-torture/execute/conversion.c

llvm-svn: 134205
 2011-06-30 23:42:18 +00:00
Jim Grosbach
351dcca2cb Refact ARM Thumb1 tMOVr instruction family. 
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.

llvm-svn: 134204
 2011-06-30 23:38:17 +00:00
Eric Christopher
2582061ec1 Add support for the 'h' constraint. 
Part of rdar://9119939

llvm-svn: 134203
 2011-06-30 23:23:01 +00:00
Bill Wendling
28c3cfe015 Add target a target hook to get the register number used by the compact unwind 
encoding for the registers it knows about. Return -1 if it can't handle that
register.

llvm-svn: 134202
 2011-06-30 23:20:32 +00:00
Rafael Espindola
6201f80bc0 Revert my previous patch while I debug llvm-gcc bootstrap. 
llvm-svn: 134201
 2011-06-30 22:58:17 +00:00
Bill Wendling
80c39ac9a5 Add one more comment to the FDE verbose asm output. 
llvm-svn: 134200
 2011-06-30 22:35:49 +00:00
Rafael Espindola
63769912fc Don't give up on coalescing A and B when we find 
A = X
B = X

Instead, proceed as if we had found

A = X
B = A

llvm-svn: 134199
 2011-06-30 22:24:13 +00:00
Eric Christopher
8539ecdf7e Add a convenience typedef for std::pair<unsigned, const TargetRegisterClass*>. 
No functional change.

Part of rdar://9119939

llvm-svn: 134198
 2011-06-30 22:17:01 +00:00
Jim Grosbach
32d3b2625b Thumb1 register to register MOV instruction is predicable. 
Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.

llvm-svn: 134197
 2011-06-30 22:10:46 +00:00
Bill Wendling
834cb876e6 Add comments to the FDE. 
llvm-svn: 134196
 2011-06-30 22:02:20 +00:00
Bill Wendling
eace9970bd Add more comments to the ASM output for the CIE's "moves". 
llvm-svn: 134194
 2011-06-30 21:45:12 +00:00
Jakob Stoklund Olesen
074d0abb1a Tweak error messages to match GCC. Should fix gcc.target/i386/pr30848.c 
llvm-svn: 134193
 2011-06-30 21:30:30 +00:00
Bill Wendling
7a94c43c7a Add comments to the ASM output to help understand the compact unwind and CIE tables. 
llvm-svn: 134191
 2011-06-30 21:25:51 +00:00
Rafael Espindola
83789b3b8d Create a isFullCopy predicate. 
llvm-svn: 134189
 2011-06-30 21:15:52 +00:00
Rafael Espindola
03cd7c7b76 Add r134057 back, but splice the predecessor after the successors phi 
nodes.

Original message:
Let simplify cfg simplify bb with only debug and lifetime intrinsics.

llvm-svn: 134182
 2011-06-30 20:14:24 +00:00
Jim Grosbach
fddcf02338 Pseudo-ize the Thumb tTPsoft instruction. 
It's just a call to a special helper function. Get rid of the T2 variant
entirely, as it's identical to the Thumb1 version.

llvm-svn: 134178
 2011-06-30 19:38:01 +00:00
Andrew Trick
bcaaa0ae73 indvars -disable-iv-rewrite: handle cloning binary operators that cannot overflow. 
llvm-svn: 134177
 2011-06-30 19:02:17 +00:00
Jim Grosbach
8c1fb3c4e1 Pseudo-ize the t2LDMIA_RET instruction. 
It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.

llvm-svn: 134173
 2011-06-30 18:25:42 +00:00
Jim Grosbach
733634d051 Pseudo-ize the Thumb tPOP_RET instruction. 
It's just a tPOP instruction with additional code-gen properties, so it
doesn't need encoding information.

llvm-svn: 134172
 2011-06-30 17:34:04 +00:00
Rafael Espindola
a324c7e6bb Remove dead code. 
llvm-svn: 134148
 2011-06-30 13:17:24 +00:00
Jim Grosbach
1638e9f891 Kill dead code. 
llvm-svn: 134131
 2011-06-30 02:23:05 +00:00
Jim Grosbach
4f7cde70a9 Size reducing SP adjusting t2ADDri needs to check predication. 
tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the
predicate is anything other than "always."

llvm-svn: 134130
 2011-06-30 02:22:49 +00:00
Evan Cheng
ac2e40ad2c Fix ARMSubtarget feature parsing. 
llvm-svn: 134129
 2011-06-30 02:12:44 +00:00
Evan Cheng
034261674b Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to 
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.

The fix is to just have the clients explictly pass the CPU name!

llvm-svn: 134127
 2011-06-30 01:53:36 +00:00