Jim Grosbach
a678ad9ecc
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
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rdar://10558523
llvm-svn: 147189
2011-12-22 22:19:05 +00:00
Bob Wilson
63bc016e30
Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp.
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Noticed by inspection; I don't have a testcase for this.
llvm-svn: 147188
2011-12-22 22:12:44 +00:00
Jim Grosbach
59fccb5809
Tidy up. Use predicate function a bit more liberally.
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llvm-svn: 147184
2011-12-22 22:02:35 +00:00
Rafael Espindola
eba1c0eb00
Fix incorrect relocation generation. Patch by Kristof Beyls.
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Fixes PR11214.
llvm-svn: 147180
2011-12-22 21:36:43 +00:00
Jim Grosbach
06dffd2643
ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.
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The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.
Partial for: rdar://10558523
llvm-svn: 147170
2011-12-22 19:55:21 +00:00
Jim Grosbach
5824007e4d
Remove some bogus comments.
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llvm-svn: 147169
2011-12-22 19:45:01 +00:00
Jim Grosbach
970c4cab9e
ARM pre-UAL aliases. fcmp[sd].
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llvm-svn: 147158
2011-12-22 19:20:45 +00:00
Jim Grosbach
100e3aaffa
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
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Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
llvm-svn: 147153
2011-12-22 18:04:04 +00:00
Jim Grosbach
90f8398ee6
ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.
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llvm-svn: 147152
2011-12-22 17:37:00 +00:00
Jim Grosbach
8ca95cbf58
Tidy up. Trailing whitespace.
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llvm-svn: 147151
2011-12-22 17:17:10 +00:00
Jim Grosbach
65cd6c7acc
Nuke invalid comment from copy/paste.
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llvm-svn: 147150
2011-12-22 17:04:50 +00:00
Rafael Espindola
57dea1bf84
Make the virtual methods in ARMELFObjectWriter public.
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llvm-svn: 147132
2011-12-22 02:58:12 +00:00
Rafael Espindola
6f3a1698f3
Hopefully fix the cmake build.
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llvm-svn: 147121
2011-12-22 01:11:01 +00:00
Rafael Espindola
6f21886d7e
Fix name in comments.
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llvm-svn: 147119
2011-12-22 01:06:53 +00:00
Richard Smith
9b355262f5
Unbreak cmake build after r147115.
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llvm-svn: 147117
2011-12-22 01:03:35 +00:00
Rafael Espindola
ee837037ee
Move the ARM specific parts of the ELF writer to Target/ARM.
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llvm-svn: 147115
2011-12-22 00:37:50 +00:00
Jim Grosbach
1b11b334a4
ARM NEON mnemonic aliase for vrecpeq.
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llvm-svn: 147109
2011-12-21 23:52:37 +00:00
Jim Grosbach
7d31680e2d
ARM VFP optional data type on VMOV GPR<-->SPR.
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llvm-svn: 147104
2011-12-21 23:24:15 +00:00
Jim Grosbach
35b5afad26
ARM NEON optional data type on VSWP instructions.
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llvm-svn: 147103
2011-12-21 23:09:28 +00:00
Jim Grosbach
64df852f5b
ARM NEON mnemonic aliases for vzipq and vswpq.
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llvm-svn: 147102
2011-12-21 23:04:33 +00:00
Jim Grosbach
88eacffd72
ARM asm parser should be more lenient w/ .thumb_func directive.
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Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.
rdar://10611140
llvm-svn: 147100
2011-12-21 22:30:16 +00:00
Jim Grosbach
2bbc41fa26
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
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Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
llvm-svn: 147096
2011-12-21 21:04:19 +00:00
Jim Grosbach
91faf5d15f
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
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These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
llvm-svn: 147094
2011-12-21 20:54:00 +00:00
Jakob Stoklund Olesen
893037ce23
Move common code into an MRI function.
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llvm-svn: 147071
2011-12-21 19:50:05 +00:00
Jim Grosbach
f7236d1084
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
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llvm-svn: 147069
2011-12-21 19:40:55 +00:00
Chad Rosier
c2f31859cc
Fix a couple of copy-n-paste bugs. Noticed by George Russell!
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llvm-svn: 147064
2011-12-21 18:56:22 +00:00
Rafael Espindola
f9c7f9e3f3
Reduce the exposure of Triple::OSType in the ELF object writer. This will
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avoid including ADT/Triple.h in many places when the target specific bits are
moved.
llvm-svn: 147059
2011-12-21 17:00:36 +00:00
Evan Cheng
fb22f64814
Fix a couple of copy-n-paste bugs. Noticed by George Russell.
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llvm-svn: 147032
2011-12-21 03:04:10 +00:00
Jim Grosbach
2c2140a128
ARM assembly parsing allows constant expressions for lane indices.
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llvm-svn: 147028
2011-12-21 01:19:23 +00:00
Jim Grosbach
6bd1044b03
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
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llvm-svn: 147025
2011-12-21 00:38:54 +00:00
Jim Grosbach
7baaa0fc64
ARM .req register name aliases are case insensitive, just like regnames.
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llvm-svn: 147009
2011-12-20 23:11:00 +00:00
Jim Grosbach
ff31b81fe2
Move comment to appropriate place.
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llvm-svn: 147000
2011-12-20 22:26:38 +00:00
Jakob Stoklund Olesen
2b24e1eac4
Heed spill slot alignment on ARM.
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Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.
Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack. Don't use aligned spill code in that case.
llvm-svn: 146997
2011-12-20 22:15:04 +00:00
Jim Grosbach
8978194025
ARM assembly parsing and encoding for VST2 single-element, double spaced.
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llvm-svn: 146990
2011-12-20 20:46:29 +00:00
Jim Grosbach
8156a5dcee
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
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llvm-svn: 146983
2011-12-20 19:21:26 +00:00
Evan Cheng
46b085721a
ARM target code clean up. Check for iOS, not Darwin where it makes sense.
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llvm-svn: 146981
2011-12-20 18:26:50 +00:00
Jason W Kim
139dd49440
First steps in ARM AsmParser support for .eabi_attribute and .arch
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(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)
llvm-svn: 146977
2011-12-20 17:38:12 +00:00
Chandler Carruth
1663697160
Fix up the CMake build for the new files added in r146960, they're
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likely to stay either way that discussion ends up resolving itself.
llvm-svn: 146966
2011-12-20 08:42:11 +00:00
David Blaikie
576aba04f1
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
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llvm-svn: 146960
2011-12-20 02:50:00 +00:00
Bob Wilson
8439df9506
Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.
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We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers. But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore. Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early. This also more accurately reflects
when the registers are clobbered.
llvm-svn: 146949
2011-12-20 01:29:27 +00:00
Jim Grosbach
3f5493c136
ARM assembly shifts by zero should be plain 'mov' instructions.
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"mov r1, r2, lsl #0 " should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
llvm-svn: 146937
2011-12-20 00:59:38 +00:00
Jim Grosbach
b1b83d2f58
ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.
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e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117 "
rdar://10603913
llvm-svn: 146925
2011-12-19 23:51:07 +00:00
Jim Grosbach
343f270350
ARM assembly parsing and encoding support for LDRD(label).
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rdar://9932658
llvm-svn: 146921
2011-12-19 23:06:24 +00:00
Jim Grosbach
797a88284c
ARM NEON two-operand aliases for VPADD.
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rdar://10602276
llvm-svn: 146895
2011-12-19 19:51:03 +00:00
Jim Grosbach
f9910809c5
ARM VFP pre-UAL mnemonic aliases for fmul[sd].
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llvm-svn: 146892
2011-12-19 19:43:50 +00:00
Jim Grosbach
6e9471925b
ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
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llvm-svn: 146887
2011-12-19 19:02:41 +00:00
Jim Grosbach
520db82971
ARM NEON implied destination aliases for VMAX/VMIN.
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llvm-svn: 146885
2011-12-19 18:57:38 +00:00
Jim Grosbach
f4ca84a7ab
ARM NEON relax parse time diagnostics for alignment specifiers.
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There's more variation that we need to handle. Error checking will need
to be on operand predicates.
llvm-svn: 146884
2011-12-19 18:31:43 +00:00
Jim Grosbach
2a0ced60a5
Tidy up.
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llvm-svn: 146882
2011-12-19 18:11:17 +00:00
Jakob Stoklund Olesen
7b1b08eb77
Remove a register class that can just as well be synthesized.
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Add the new TableGen register class synthesizer feature to the release
notes.
llvm-svn: 146875
2011-12-19 16:53:40 +00:00