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Commit Graph

201174 Commits

Author SHA1 Message Date
Xing GUO
a709c04972 [DWARFYAML][debug_aranges] Make the 'Descriptors' field optional. 2020-08-02 21:39:44 +08:00
Simon Pilgrim
b4529b09f8 [X86] Use const APInt& in for-range loop to avoid unnecessary copies. NFCI.
Fixes clang-tidy warning.
2020-08-02 14:32:23 +01:00
Simon Pilgrim
66bc0292a3 [X86] Pass SDLoc by const reference. NFCI. 2020-08-02 14:32:22 +01:00
Simon Pilgrim
0e00b656e7 [X86] Use const APInt& in for-range loop to avoid unnecessary copies. NFCI.
Fixes clang-tidy warning.
2020-08-02 14:32:22 +01:00
Simon Pilgrim
8ccdc8c8e2 [X86] combineX86ShuffleChain - pull out repeated RootVT.getSizeInBits() calls. NFCI. 2020-08-02 14:32:22 +01:00
Shinji Okumura
5dd3ff33f5 [Attributor] AAPotentialValues Interface
This is a split patch of D80991.
This patch introduces AAPotentialValues and its interface only.
For more detail of AAPotentialValues abstract attribute, see the original patch.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D83283
2020-08-02 19:12:17 +09:00
Florian Hahn
59ddae8a70 [SCEV] Precommit tests with signed counting down loop.
From PR46939.
2020-08-02 10:26:26 +01:00
Michał Górny
484bce4c42 [CMake] Pass bugreport URL to standalone clang build
BUG_REPORT_URL is currently used both in LLVM and in Clang but declared
only in the latter.  This means that it's missing in standalone clang
builds and the driver ends up outputting:

  PLEASE submit a bug report to  and include [...]

(note the missing URL)

To fix this, include LLVM_PACKAGE_BUGREPORT in LLVMConfig.cmake
(similarly to how we pass PACKAGE_VERSION) and use it to fill
BUG_REPORT_URL when building clang standalone.

Differential Revision: https://reviews.llvm.org/D84987
2020-08-02 08:32:05 +02:00
Craig Topper
3beb1fadf1 [X86] Improve parity idiom recognition to handle (and (truncate (ctpop X)), 1).
Fixes part of PR46954
2020-08-01 22:59:43 -07:00
Craig Topper
8768bd7fc8 [X86] Add parity test cases for PR46954.
This adds tests cases where the parity idiom of (and (ctpop X, 1))
has a truncate in the middle.
2020-08-01 22:52:33 -07:00
AK
d76fd7858a [HotColdSplit] Add test case for unlikely attribute in outlined function
Authored by: rjf (Ruijie Fang)
Reviewed by: hiraditya,tejohnson,fhahn

Differential Revision: https://reviews.llvm.org/D69384
2020-08-01 22:34:59 -07:00
AK
b2bac552f1 Outline non returning functions unless a longjmp
__assert_fail, abort, exit etc. are cold.
TODO: outline throw

Authored by: rjf (Ruijie Fang)
Reviewed by: hiraditya,tejohnson,fhahn

Differential Revision: https://reviews.llvm.org/D69257
2020-08-01 22:16:14 -07:00
Kazu Hirata
6e4cee6f1e Use llvm::is_contained where appropriate (NFC)
Use llvm::is_contained where appropriate (NFC)

Reviewed By: kazu

Differential Revision: https://reviews.llvm.org/D85083
2020-08-01 21:51:06 -07:00
Lang Hames
b014cb8f2f [llvm-jitlink] Add -phony-externals option to suppress unresolved externals.
The -phony-externals option adds a generator which explicitly defines any
otherwise unresolved externals as null. This transforms link-time
unresolved-symbol errors into potential runtime null pointer accesses
(if an unresolved external is actually accessed during execution).

This option can be useful in -harness mode to avoid having to mock a
large number of symbols that are not reachable at runtime (e.g. unused
methods referenced by a class vtable).
2020-08-01 18:33:44 -07:00
Lang Hames
f9871c7f15 [llvm-jitlink] Support promotion of ODR weak symbols in -harness mode.
This prevents weak symbols from being immediately dead-stripped when not
directly referenced from the test harneess, enabling use of weak symbols
from the code under test.
2020-08-01 18:33:44 -07:00
Nikita Popov
ae08f299bd [NewPM][LVI] Abandon LVI after CVP
As mentioned on D70376, LVI can currently cause performance issues
when running under NewPM. The problem is that, unlike the legacy
pass manager, NewPM will not immediately discard the LVI analysis
if the following pass does not need it. This is a problem, because
LVI has a high memory requirement, and mass invalidation of LVI
values is very inefficient. LVI should only be alive during passes
that actively interact with it.

This patch addresses the issue by explicitly abandoning LVI after CVP,
which gets us back to the LegacyPM behavior.

Differential Revision: https://reviews.llvm.org/D84959
2020-08-01 23:47:46 +02:00
Craig Topper
ad26adfc58 [X86] Add assembler support for {disp8} and {disp32} to control the size of displacement used for memory operands.
These prefixes should override the default behavior and force a larger immediate size. I don't believe gas issues any warning if you use {disp8} when a 32-bit displacement is already required. And this patch doesn't either.

This completes the {disp8} and {disp32} support from PR46650.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D84793
2020-08-01 13:26:35 -07:00
Craig Topper
183d6fbbe7 [InstSimplify] Fold abs(abs(x)) -> abs(x)
It's always safe to pick the earlier abs regardless of the nsw flag. We'll just lose it if it is on the outer abs but not the inner abs.

Differential Revision: https://reviews.llvm.org/D85053
2020-08-01 13:25:00 -07:00
Craig Topper
8ed321d822 [InstCombine] Fold abs(-x) -> abs(x)
Negating the input doesn't matter. I left a FIXME to copy the nsw flag if its present on the neg but not on the abs.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D85055
2020-08-01 13:25:00 -07:00
Florian Hahn
ab94d6392d [PPC] Adjust run line for hardware-loops-crash.ll
Looks like %s was accidentally dropped.
2020-08-01 20:58:05 +01:00
Florian Hahn
a60d0184bb [LCSSA] Provide option for caller to clean up unused PHIs.
formLCSSAForInstructions is used by SCEVExpander, which tracks all
inserted instructions including LCSSA phis using asserting value
handles. This means cleanup needs to happen in the caller.

Extend formLCSSAForInstructions  to take an optional pointer to a
vector. If this argument is non-nullptr, instead of directly deleting
the phis, add them to the vector, so the caller can process them.

This should address various PPC buildbot failures, including
http://lab.llvm.org:8011/builders/clang-ppc64be-linux-lnt/builds/40567
2020-08-01 20:43:19 +01:00
Simon Pilgrim
63334e0fdd [X86][AVX512] Fold concat(and(x,y),and(z,w)) -> and(concat(x,z),concat(y,w)) for 512-bit vectors
Helps vpternlog folding on non-AVX512BW targets
2020-08-01 20:34:39 +01:00
Simon Pilgrim
6d5e604171 [X86][AVX] Ensure we only combine to PSHUFLW/PSHUFHW on supporting targets
Noticed while investigating combining from concatenated shuffle vectors, we weren't checking that PSHUFLW/PSHUFHW was legal - we were depending on lowering splitting to subvectors.
2020-08-01 19:18:11 +01:00
Florian Hahn
9f0a79c54a [LCSSA] Use IRBuilder for PHI creation.
Use IRBuilder instead PHINode::Create. This should not impact the
generated code, but IRBuilder provides a way to register callbacks for
inserted instructions, which is convenient for some users.

Reviewed By: lebedev.ri

Differential Revision: https://reviews.llvm.org/D85037
2020-08-01 18:44:15 +01:00
Sanjay Patel
3c783375b2 [VectorCombine] add tests for non-zero gep offsets; NFC 2020-08-01 10:18:37 -04:00
Luofan Chen
1a5b0cb812 [Attributor][NFC] Update description for the dependency graph
The word "dependency graph" is a bit misleading. When there is an
edge from node A to B (A -> B), it actually mean that B depends on
A and when the state of A is updated, B should also be updated. So
I update the comment to make the description clearer.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D85065
2020-08-01 21:27:16 +08:00
David Green
9b99990de0 [ARM] Distribute post-inc for Thumb2 sign/zero extending loads/stores
This adds sign/zero extending scalar loads/stores to the MVE
instructions added in D77813, allowing us to create up more post-inc
instructions. These are comparatively simple, compared to LDR/STR (which
may be better turned into an LDRD/LDM), but still require some additions
over MVE instructions. Because there are i12 and i8 variants of the
offset loads/stores dealing with different signs, we may need to convert
an i12 address to a i8 negative instruction. t2LDRBi12 can also be
shrunk to a tLDRi under the right conditions, so we need to be careful
with codesize too.

Differential Revision: https://reviews.llvm.org/D78625
2020-08-01 14:01:18 +01:00
Sanjay Patel
afc3df8955 [InstSimplify] simplify abs if operand is known non-negative
abs() should be rare enough that using value tracking is not going
to be a compile-time cost burden, so use it to reduce a variety of
potential patterns. We do this in DAGCombiner too.

Differential Revision: https://reviews.llvm.org/D85043
2020-08-01 07:47:06 -04:00
Sanjay Patel
5c3a911802 [InstSimplify] add abs test with assume; NFC 2020-08-01 07:47:06 -04:00
Simon Pilgrim
d8abe46054 [X86][AVX] Extend v2f64 BROADCAST(LOAD) -> BROADCAST_LOAD to v2i64/v4f32/v4i32
Minor precursor fix for D66004, but helps the SSE41 tests as well as they run with -disable-peephole
2020-08-01 12:28:29 +01:00
Evgeny Leviant
f0f5988a8b [MachineVerifier] Refactor calcRegsPassed. NFC
Patch improves performance of verify-machineinstrs pass up to 10x.
Differential revision: https://reviews.llvm.org/D84105
2020-08-01 12:58:52 +03:00
Craig Topper
6f1bb8dc02 [X86] Refactor the broadcast and load folding in tryVPTESTM to reduce some code.
Now we try to load and broadcast together for operand 1. Followed
by load and broadcast for operand 1. Previously we tried load
operand 1, load operand 1, broadcast operand 0, broadcast operand 1.

Now we have a single helper that tries load and broadcast for
one operand that we can just call twice.
2020-07-31 23:57:13 -07:00
Chen Zheng
a58d9fd6a7 [SCEV] don't query getSCEV() for incomplete phis
querying getSCEV() for incomplete phis leads to wrong cache value in `ExprToIVMap`,
because incomplete phis may be simplified to same value before get SCEV expression.

Reviewed By: lebedev.ri, mkazantsev

Differential Revision: https://reviews.llvm.org/D77560
2020-08-01 02:38:54 -04:00
Craig Topper
d64ed9b517 [X86] Use TargetLowering::getRegClassFor to simplify some code in tryVPTESTM. NFCI 2020-07-31 21:39:10 -07:00
Justin Hibbits
14a0a3dcce PowerPC: Don't lower SELECT_CC to PPCISD::FSEL on SPE
SPE doesn't have a fsel instruction, so don't try to lower to it.

This fixes a "Cannot select: tN: f64 = PPCISD::FSEL tX, tY, tZ" error.

Reviewed By: #powerpc, lkail
Differential Revision: https://reviews.llvm.org/D77773
2020-07-31 22:52:47 -05:00
Justin Hibbits
08824ee801 PowerPC: Fix SPE extloadf32 handling.
The patterns were incorrect copies from the FPU code, and are
unnecessary, since there's no extended load for SPE.  Just let LLVM
itself do the work by marking it expand.

Reviewed By: #powerpc, lkail
Differential Revision: https://reviews.llvm.org/D78670
2020-07-31 22:42:57 -05:00
Kazushi (Jam) Marukawa
f1ff8145c5 [VE] Change calling convention to follow ABI
Change to expand all arguments and return values to i64 to follow ABI.
Update regression tests also.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D84581
2020-08-01 10:08:54 +09:00
Huihui Zhang
864c46a52c [AArch64][SVE] Allow vector of pointers as legal type for masked load/store.
Refer to LangRef http://llvm.org/docs/LangRef.html#llvm-masked-load-intrinsics
'llvm.masked.load/store.*’ intrinsics are overloaded intrinsic, which allow the
load/store data to be a vector of any integer, floating-point or pointer data type.

Therefore, allow pointer data type when checking 'isLegalMaskedLoadStore()'.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D85045
2020-07-31 17:30:23 -07:00
Craig Topper
fd4b2918cb [X86] Simplify vpternlog immediate selection.
Rather than hardcoding immediate values for 12 different combinations
in a nested pair of switches, we can perform the matched logic
operation on 3 magic constants to calculate the immediate.

Special thanks to this tweet https://twitter.com/rygorous/status/1187034321992871936
for making me realize I could do this.
2020-07-31 17:16:27 -07:00
Hsiangkai Wang
7355c32ef8 Upgrade MC to v0.9.
Differential revision: https://reviews.llvm.org/D80802
2020-08-01 07:42:06 +08:00
Craig Topper
9eeafe7bcb [ValueTracking] Improve llvm.abs handling in computeKnownBits.
Add the optimizations we have in the SelectionDAG version.
Known non-negative copies all known bits. Any known one other than
the sign bit makes result non-negative.

Differential Revision: https://reviews.llvm.org/D85000
2020-07-31 15:55:03 -07:00
Sanjay Patel
78ec37cf30 [InstSimplify] add tests for abs intrinsic; NFC 2020-07-31 18:49:13 -04:00
Sriraman Tallam
c09ff709a2 Rename basic block sections options to be consistent.
D68049 created options for basic block sections: -fbasic-block-sections=,
-funique-basic-block-section-names. Rename options in llc and lld (--lto-)
to be consistent. Specifically,

+ Rename basicblock-sections to basic-block-sections
+ Rename unique-bb-section-names to unique-basic-block-section-names

Differential Revision: https://reviews.llvm.org/D84462
2020-07-31 11:50:55 -07:00
LLVM GN Syncbot
4def0a9062 [gn build] Port b7cfa6ca928 2020-07-31 18:32:54 +00:00
Sidharth Baveja
14aeea5cd6 [Loop Peeling] Separate the Loop Peeling Utilities from the Loop Unrolling Utilities
Summary: This patch separates the Loop Peeling Utilities from Loop Unrolling.
The reason for this change is that Loop Peeling is no longer only being used by
loop unrolling; Patch D82927 introduces loop peeling with fusion, such that
loops can be modified to have to same trip count, making them legal to be
peeled.

Reviewed By: Meinersbur

Differential Revision: https://reviews.llvm.org/D83056
2020-07-31 18:31:58 +00:00
Fangrui Song
a662655d26 [Support] Fix computeHostNumPhysicalCores() to respect affinity
computeHostNumPhysicalCores() is designed to respect CPU affinity.
D84764 used sysconf(_SC_NPROCESSORS_ONLN) which does not respect
affinity.
SupportTests Threading.PhysicalConcurrency may fail if taskset -c is specified.
2020-07-31 11:20:15 -07:00
Sanjay Patel
65a64fcb5b [ConstantFolding] fold abs intrinsic
The handling for minimum value is similar to cttz/ctlz with 0 just above this case.

Differential Revision: https://reviews.llvm.org/D84942
2020-07-31 14:08:44 -04:00
Hans Wennborg
30c3d4b6b4 RuntimeDyldELF: report_fatal_error instead of asserting for unimplemented relocations (PR46816)
This fixes the ExecutionEngine/MCJIT/stubs-sm-pic.ll test in no-asserts
builds which is set to XFAIL on some platforms like 32-bit x86. More
importantly, we probably don't want to silently error in these cases.

Differential revision: https://reviews.llvm.org/D84390
2020-07-31 20:06:47 +02:00
Craig Topper
2c4eee97f8 [ValueTracking] Add ComputeNumSignBits support for llvm.abs intrinsic
If absolute value needs turn a negative number into a positive number it reduces the number of sign bits by at most 1.

Differential Revision: https://reviews.llvm.org/D84971
2020-07-31 10:59:12 -07:00
Teresa Johnson
cd7ddd2dc4 [ThinLTO] Compile time improvement to propagateAttributes
I found that propagateAttributes was ~23% of a thin link's run time
(almost 4x higher than the second hottest function). The main reason is
that it re-examines a global var each time it is referenced. This
becomes unnecessary once it is marked both non read only and non write
only. I added a set to avoid doing redundant work, which dropped the
runtime of that thin link by almost 15%.

I made a smaller efficiency improvement (no measurable impact) to skip
all summaries for a VI if the first copy is dead. I added an assert to
ensure that all copies are dead if any is. The code in
computeDeadSymbols marks all summaries for a VI as live. There is one
corner case where it was skipping marking an alias as live, that I
fixed. However, since the code earlier marked all copies of a preserved
GUID's VI as live, and each 'visit' marks all copies live, the only case
where this could make a difference is summaries that were marked live
when they were built initially, and that is only a few special compiler
generated symbols and inline assembly symbols, so it likely is never
provoked in practice.

Differential Revision: https://reviews.llvm.org/D84985
2020-07-31 10:54:02 -07:00