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Commit Graph

64791 Commits

Author SHA1 Message Date
NAKAMURA Takumi
a8d8b5f3c3 test/CodeGen/X86: Add explicit triplet -mtriple=i686-linux to 3 tests incompatible to Win32 codegen.
r114297 raises 3 failures. They might fail also on mingw.

llvm-svn: 114317
2010-09-19 21:58:55 +00:00
Owen Anderson
9594834ec1 Revert r114312 while I sort out some issues.
llvm-svn: 114313
2010-09-19 21:01:26 +00:00
Owen Anderson
65f23dcf7e Tentatively enabled DAGCombiner Alias Analysis by default. As far as I know,
r114268 fixed the last of the blockers to enabling it.  I will be monitoring
for failures.

llvm-svn: 114312
2010-09-19 19:51:55 +00:00
Jakob Stoklund Olesen
8ae6803659 Add one more Core i7 model number.
llvm-svn: 114310
2010-09-19 17:54:28 +00:00
Misha Brukman
b7d800dd67 Using regexp-opt for keyword regex declarations makes the word lists more
readable and easier to edit.

llvm-svn: 114308
2010-09-19 03:44:22 +00:00
Chris Lattner
3203bf3688 idiom recognition should catch this.
llvm-svn: 114304
2010-09-19 00:37:34 +00:00
Chris Lattner
ac0afb0fbe add a readme.
llvm-svn: 114303
2010-09-19 00:34:58 +00:00
Chris Lattner
4e80799dbb add corei7, the laptop version.
llvm-svn: 114302
2010-09-19 00:31:58 +00:00
NAKAMURA Takumi
a4a0276d4f X86Subtarget.h: Fix Cygwin's TD.
llvm-svn: 114297
2010-09-18 19:50:42 +00:00
Eric Christopher
2901b19344 Add the exit instruction to the PTX target.
Patch by Che-Liang Chiou <clchiou@gmail.com>!

llvm-svn: 114294
2010-09-18 18:52:28 +00:00
Eric Christopher
8b626a2da9 Handle the odd case where we only have one instruction.
llvm-svn: 114293
2010-09-18 18:50:27 +00:00
Michael J. Spencer
3a9b3aae55 Fix build.
llvm-svn: 114292
2010-09-18 17:54:37 +00:00
Rafael Espindola
9c3a9bf8aa Make sure the STT_FILE symbol is the first one in the symbol table.
llvm-svn: 114285
2010-09-18 15:03:21 +00:00
Benjamin Kramer
89a330c4b9 Unbreak msvc build.
llvm-svn: 114284
2010-09-18 14:41:26 +00:00
Gabor Greif
25989ff0b4 restrict dyn_cast_or_null to pointer types, just like cast_or_null; re-commit of r114279, backed out in r114280
llvm-svn: 114282
2010-09-18 13:03:32 +00:00
Gabor Greif
01fd81d9e0 back out r114279 as some darwin buildbots get errors compiling clang:
svn merge -c -114279 llvm/include/llvm/Support/Casting.h

llvm-svn: 114280
2010-09-18 12:56:47 +00:00
Gabor Greif
de7f1d3c08 restrict dyn_cast_or_null to pointer types, just like cast_or_null
llvm-svn: 114279
2010-09-18 12:30:15 +00:00
Gabor Greif
dd1c709af4 do not rely on the implicit-dereference semantics of dyn_cast_or_null
llvm-svn: 114278
2010-09-18 11:55:34 +00:00
Gabor Greif
5348c51fbe do not rely on the implicit-dereference semantics of dyn_cast_or_null
llvm-svn: 114277
2010-09-18 11:53:39 +00:00
Gabor Greif
356c676d76 remove CallSite::get; it is still present (as protected) in the baseclass, use one of the constructors intead
llvm-svn: 114275
2010-09-18 11:48:36 +00:00
Lang Hames
2d87a43549 Fixed non-const iterator error.
llvm-svn: 114273
2010-09-18 09:49:08 +00:00
Lang Hames
4a8c999803 Added a separate class (PBQPBuilder) for PBQP Problem construction. This class can be extended to support custom constraints.
For now the allocator still uses the old (internal) construction mechanism by default. This will be phased out soon assuming 
no issues with the builder system come up.

To invoke the new construction mechanism just pass '-regalloc=pbqp -pbqp-builder' to llc. To provide custom constraints a
Target just needs to extend PBQPBuilder and pass an instance of their derived builder to the RegAllocPBQP constructor.

llvm-svn: 114272
2010-09-18 09:07:10 +00:00
Michael J. Spencer
37c9ae6c7f docs: Tweak wording.
llvm-svn: 114271
2010-09-18 08:32:32 +00:00
Evan Cheng
442cb9c620 Fix code that break critical edges for PHI uses. Watch out for multiple PHIs in different blocks.
llvm-svn: 114270
2010-09-18 06:42:17 +00:00
Owen Anderson
015641f659 Invert the logic of reachesChainWithoutSideEffects(). What we want to check is that there is
NO path to the destination containing side effects, not that SOME path contains no side effects.
In  practice, this only manifests with CombinerAA enabled, because otherwise the chain has little
to no branching, so "any" is effectively equivalent to "all".

llvm-svn: 114268
2010-09-18 04:45:14 +00:00
Eric Christopher
0c5e912e21 Thumb opcodes for thumb calls.
llvm-svn: 114263
2010-09-18 02:32:38 +00:00
Daniel Dunbar
3555832020 lit: Bump version to 0.2.0dev, for no apparent reason.
llvm-svn: 114262
2010-09-18 02:28:15 +00:00
Daniel Dunbar
9bf57694be lit: Tweak setup.py.
llvm-svn: 114261
2010-09-18 02:28:12 +00:00
Daniel Dunbar
98afc51d08 lit: These TODOs are done(ish).
llvm-svn: 114260
2010-09-18 02:28:09 +00:00
Eric Christopher
c9fef312c8 Add addrmode5 fp load support. Swap float/thumb operand adding to handle
thumb with floating point.

llvm-svn: 114256
2010-09-18 01:59:37 +00:00
Eric Christopher
b6ce0ab878 Floating point stores have a 3rd addressing mode type.
llvm-svn: 114254
2010-09-18 01:23:38 +00:00
Rafael Espindola
32e423fe2b Add test that was missing in my previous commit.
llvm-svn: 114248
2010-09-18 00:37:27 +00:00
Jim Grosbach
c909422ee9 factor out a simple helper function to create a label for PC-relative
instructions (PICADD, PICLDR, et.al.)

llvm-svn: 114243
2010-09-18 00:05:05 +00:00
Jim Grosbach
a19f7799fb PC-relative pseudo instructions are lowered and printed directly. Any encounter
with one in the generic printing code is an error.

llvm-svn: 114242
2010-09-18 00:04:53 +00:00
Dan Gohman
e96841854e Attempt to XFAIL this test on arm-linux, which is inexplicably failing.
llvm-svn: 114241
2010-09-18 00:04:37 +00:00
Benjamin Kramer
1cad9b6521 Fix vmov.f64 disassembly on targets where sizeof(long) != 8.
llvm-svn: 114240
2010-09-17 23:48:07 +00:00
Jim Grosbach
8b988eb1d4 Add MC-inst handling for tPICADD
llvm-svn: 114237
2010-09-17 23:41:53 +00:00
Bob Wilson
670e1915c0 Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64
value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert.  Radar 8407927.

llvm-svn: 114233
2010-09-17 22:59:05 +00:00
Jim Grosbach
8ae5cfffdd Teach the (non-MC) instruction printer to use the cannonical names for push/pop,
and shift instructions on ARM. Update the tests to match.

llvm-svn: 114230
2010-09-17 22:36:38 +00:00
Rafael Espindola
acd5bacfb9 Avoid relocations in a common case.
llvm-svn: 114229
2010-09-17 22:34:41 +00:00
Evan Cheng
8c2bde65f0 Teach machine sink to
1) Do forward copy propagation. This makes it easier to estimate the cost of the
   instruction being sunk.
2) Break critical edges on demand, including cases where the value is used by
   PHI nodes.
Critical edge splitting is not yet enabled by default.

llvm-svn: 114227
2010-09-17 22:28:18 +00:00
Eric Christopher
716614f126 Rework arm fast isel branch and compare code.
llvm-svn: 114226
2010-09-17 22:28:18 +00:00
Evan Cheng
042ab036a2 Machine CSE was forgetting to clear some data structures.
llvm-svn: 114222
2010-09-17 21:59:42 +00:00
Jim Grosbach
d2cf0742a4 Update tests to handle MC-inst instruction printing of shift operations. The
legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while
the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic
is correct and preferred according the ARM documentation (A8.6.98). The former
are pseudo-instructions for the latter.

llvm-svn: 114221
2010-09-17 21:58:46 +00:00
Evan Cheng
5f2926d516 Fix a potential bug that can cause miscomparison with and without debug info.
llvm-svn: 114220
2010-09-17 21:56:26 +00:00
Jakob Stoklund Olesen
37131971c3 Don't include <fenv.h> now that we have llvm/System/FEnv.h.
llvm-svn: 114219
2010-09-17 21:47:03 +00:00
Jim Grosbach
b86aebe2b7 FileCheck-ize
llvm-svn: 114218
2010-09-17 21:46:16 +00:00
Jim Grosbach
6e477cd3d8 Hook up verbose asm comment printing for SOImm operands in MC printer
llvm-svn: 114215
2010-09-17 21:33:25 +00:00
Jim Grosbach
352a616f23 trailing whitespace
llvm-svn: 114212
2010-09-17 21:25:10 +00:00
Jim Grosbach
134c3370ef trailing whitespace
llvm-svn: 114211
2010-09-17 21:23:56 +00:00