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Author SHA1 Message Date
Owen Anderson
ea89766d0c Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning. 
llvm-svn: 118097
 2010-11-02 22:41:42 +00:00
Dan Gohman
78b47498e3 Use '\0' instead of 0 for nul character constants. 
llvm-svn: 118096
 2010-11-02 22:41:19 +00:00
Bill Wendling
1546322a9c Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work 
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.

llvm-svn: 118094
 2010-11-02 22:31:46 +00:00
Owen Anderson
8aba4dbe03 Rename encoder methods to match naming convention. 
llvm-svn: 118093
 2010-11-02 22:28:01 +00:00
Chris Lattner
5caaacef3b mark a few codegenonly instructions. 
llvm-svn: 118092
 2010-11-02 22:26:33 +00:00
Mikhail Glushenkov
79047e7eb3 appendSuffix: don't append a dot when the suffix is empty. 
Additionally, move the implementation of appendSuffix to Path.cpp: it is
platform-independent.

llvm-svn: 118089
 2010-11-02 22:18:37 +00:00
Mikhail Glushenkov
97788c1061 Revert r118057, this is better fixed in appendSuffix itself. 
llvm-svn: 118088
 2010-11-02 22:18:28 +00:00
Owen Anderson
cdd587157f Provide correct encodings for the remaining vst variants that we currently generate. 
llvm-svn: 118087
 2010-11-02 22:18:18 +00:00
Dan Gohman
446b7f5e51 Eliminate some temporary std::strings. 
llvm-svn: 118086
 2010-11-02 22:07:47 +00:00
Owen Anderson
1f88ac90a1 Tentative encodings for the "single element from one lane" variant of vst1. 
llvm-svn: 118084
 2010-11-02 21:54:45 +00:00
Owen Anderson
46d4ab1a87 Add correct encodings for basic variants for vst3 and vst4. 
llvm-svn: 118082
 2010-11-02 21:47:03 +00:00
Rafael Espindola
daf6328eb0 Do relaxations with FT_Org fragments. Fixes the FIXME: 
// FIXME: We should compute this sooner, we don't want to recurse here, and
    // we would like to be more functional.

In MCAssembler::ComputeFragmentSize.

llvm-svn: 118080
 2010-11-02 21:38:23 +00:00
Bob Wilson
248c691f9a Add NEON VST1-lane instructions. Partial fix for Radar 8599955. 
llvm-svn: 118069
 2010-11-02 21:18:25 +00:00
Owen Anderson
36d5c04fbd Add correct encodings for the basic variants for vst2. 
llvm-svn: 118068
 2010-11-02 21:16:58 +00:00
Owen Anderson
c9f6909c96 Add correct encodings for the basic form of vst1. 
llvm-svn: 118067
 2010-11-02 21:06:06 +00:00
Dan Gohman
84ceaa19a4 Micro-optimize. 
llvm-svn: 118058
 2010-11-02 20:52:47 +00:00
Dan Gohman
172e1824d0 Don't append a dot on platforms which don't use exe suffixes. 
llvm-svn: 118057
 2010-11-02 20:49:48 +00:00
Mikhail Glushenkov
e41fe39fe7 llvmc: Fix tool finding logic. 
llvm-svn: 118056
 2010-11-02 20:47:41 +00:00
Owen Anderson
b34a5f1d02 Factor out a common encoding class for loads and stores with a lane parameter. 
llvm-svn: 118055
 2010-11-02 20:47:39 +00:00
Devang Patel
9af731f560 Fix DIType verifier. The element 3 is DIFile now. 
llvm-svn: 118054
 2010-11-02 20:41:13 +00:00
Owen Anderson
ee1337c01f Add correct encodings for the rest of the vld instructions that we generate. 
llvm-svn: 118053
 2010-11-02 20:40:59 +00:00
Mikhail Glushenkov
4c2caa10ad GetDLLSuffix: Remove the leading dot from LTDL_SHLIB_EXT. 
This allows using GetDLLSuffix() with appendSuffix().

llvm-svn: 118051
 2010-11-02 20:32:59 +00:00
Mikhail Glushenkov
709ca9117a Trailing whitespace. 
llvm-svn: 118050
 2010-11-02 20:32:52 +00:00
Mikhail Glushenkov
4077e2da6f FindExecutable: remove the executability check. 
This makes the behaviour of FindExecutable more consistent across platforms, but
I'm not very happy with the name...

llvm-svn: 118049
 2010-11-02 20:32:46 +00:00
Mikhail Glushenkov
b1d2a5ac52 Make FindProgramByName return paths with slashes unmodified on Windows. 
This makes its behaviour more consistent across platforms.

llvm-svn: 118048
 2010-11-02 20:32:39 +00:00
Mikhail Glushenkov
efb9f9754d 80-col violations. 
llvm-svn: 118045
 2010-11-02 20:32:31 +00:00
Mikhail Glushenkov
c86f1d26e9 Path: Add GetEXESuffix() to complement GetDLLSuffix(). 
llvm-svn: 118042
 2010-11-02 20:32:26 +00:00
Andrew Trick
f861447393 Fixes <rdar://problem/8612856>: During postRAsched, the antidependence 
breaker needs to check all definitions of the antidepenent register to
avoid multiple defs of the same new register.

llvm-svn: 118032
 2010-11-02 18:16:45 +00:00
Dale Johannesen
b758b5a1a3 Apply patch for use-after-free in InlineAsm constant handling, 
PR 8522 / 8616046.  Test reduction, analysis and patch by Tim Deegan!
(However, review by someone who understands the classes here better
is welcome.  John Krum will return!)

llvm-svn: 118030
 2010-11-02 17:59:27 +00:00
Jim Grosbach
5fe61a5f86 Sort bit assignments. Cosmetic change only. 
llvm-svn: 118029
 2010-11-02 17:59:04 +00:00
Devang Patel
37fa9bb66a Simplify. 
llvm-svn: 118027
 2010-11-02 17:37:00 +00:00
Jim Grosbach
d6df785c6d Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke 
assumptions about stack layout. Specifically, LR must be saved next to FP.

llvm-svn: 118026
 2010-11-02 17:35:25 +00:00
Rafael Espindola
1db6a21aff Add support for expressions in .sleb/.uleb directives. 
llvm-svn: 118023
 2010-11-02 17:22:24 +00:00
Devang Patel
e3575ef54f If value map does not have register for an argument then try to find frame index before giving up. 
llvm-svn: 118022
 2010-11-02 17:19:03 +00:00
Devang Patel
efd9ac540a Use frameindex, if available, as a last resort to emit debug info for a parameter. 
llvm-svn: 118020
 2010-11-02 17:01:30 +00:00
Owen Anderson
9d85c89ade Add correct NEON encodings for vld2, vld3, and vld4 basic variants. 
llvm-svn: 117997
 2010-11-02 01:24:55 +00:00
Eric Christopher
a376fe69a1 Remove an assert - it's possible to be hit, and we just want to avoid 
handling those cases for now.

llvm-svn: 117996
 2010-11-02 01:24:49 +00:00
Eric Christopher
a033f49ed1 Whitespeace 
llvm-svn: 117995
 2010-11-02 01:22:45 +00:00
Eric Christopher
26ddb729bd No really, no thumb1 for arm fast isel. Also add an informative comment as 
to what someone would need to do to support thumb1.

llvm-svn: 117994
 2010-11-02 01:21:28 +00:00
Jakob Stoklund Olesen
840357ca6a Don't try to split weird critical edges that really aren't: 
BB#1: derived from LLVM BB %bb.nph28
    Live Ins: %AL
    Predecessors according to CFG: BB#0
	TEST8rr %reg16384<kill>, %reg16384, %EFLAGS<imp-def>; GR8:%reg16384
	JNE_4 <BB#2>, %EFLAGS<imp-use,kill>
	JMP_4 <BB#2>
    Successors according to CFG: BB#2 BB#2

These double CFG edges only ever occur in bugpoint-generated code, so there is
no need to attempt something clever.

llvm-svn: 117992
 2010-11-02 00:58:37 +00:00
Owen Anderson
f4ab06d0b6 Attempt to provide correct encodings for a number of other vld1 variants, which we can't test 
since we can neither generate nor parse them at the moment.

llvm-svn: 117988
 2010-11-02 00:24:52 +00:00
Owen Anderson
bdb861b46f Add aesthetic break. 
llvm-svn: 117986
 2010-11-02 00:14:00 +00:00
Owen Anderson
6647eb222b Add correct NEON encodings for the "multiple single elements" form of vld. 
llvm-svn: 117984
 2010-11-02 00:05:05 +00:00
Jakob Stoklund Olesen
56f67c7d02 MachineLICM should not claim to be preserving the CFG when it can split critical 
edges on demand.

llvm-svn: 117982
 2010-11-01 23:59:55 +00:00
Jakob Stoklund Olesen
b0f64b3d2b Be more precise about verifying missing kill flags. 
It is legal for an instruction to have two operands using the same register,
only one a kill. This is interpreted as a kill.

llvm-svn: 117981
 2010-11-01 23:59:53 +00:00
Jakob Stoklund Olesen
a052004a89 When inserting copies during splitting, always use the parent register as the 
source, and let rewrite() clean it up.

This way, kill flags on the inserted copies are fixed as well during rewrite().

We can't just assume that all the copies we insert are going to be kills since
critical edges into loop headers sometimes require both source and dest to be
live out of a block.

llvm-svn: 117980
 2010-11-01 23:59:48 +00:00
Jim Grosbach
e5a253a203 Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXME 
for handling the fixup necessary.

llvm-svn: 117978
 2010-11-01 23:45:50 +00:00
Jim Grosbach
d50562f0ea Remove unused function. 
llvm-svn: 117977
 2010-11-01 23:40:56 +00:00
Bob Wilson
411b511ac0 Add support for alignment operands on VLD1-lane instructions. 
This is another part of the fix for Radar 8599955.

llvm-svn: 117976
 2010-11-01 23:40:51 +00:00
Bill Wendling
dd4216420a Missed reverting this bit. 
llvm-svn: 117971
 2010-11-01 23:17:54 +00:00
Bill Wendling
37c9af176d Minor cleanup. 
llvm-svn: 117969
 2010-11-01 23:11:22 +00:00
Chris Lattner
f94c2b782a rearrange a bit. 
llvm-svn: 117967
 2010-11-01 23:07:52 +00:00
Bob Wilson
b6bc135df8 Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. 
llvm-svn: 117964
 2010-11-01 22:04:05 +00:00
Jakob Stoklund Olesen
0ed56c87e4 Add kill flag verification. 
At least X86FloatingPoint requires correct kill flags after register allocation,
and targets using register scavenging benefit. Conservative kill flags are not
enough.

llvm-svn: 117960
 2010-11-01 21:51:31 +00:00
Jakob Stoklund Olesen
78ba455b51 Update kill flags while rewriting instructions after splitting. 
llvm-svn: 117959
 2010-11-01 21:51:29 +00:00
Bill Wendling
69e7c09c32 Move the machine operand MC encoding patterns to the parent classes. 
llvm-svn: 117956
 2010-11-01 21:17:06 +00:00
Owen Anderson
47f0efad86 When folding away a (shl (shr)) pair, we need to check that the bits that will BECOME the low 
bits are zero, not that the current low bits are zero.  Fixes <rdar://problem/8606771>.

llvm-svn: 117953
 2010-11-01 21:08:20 +00:00
Chris Lattner
b0ac93cf15 use our fancy new MnemonicAlias mechanism to remove a bunch of hacks 
from X86AsmParser.cpp

llvm-svn: 117952
 2010-11-01 21:06:34 +00:00
Bill Wendling
4340c9449a When we look at instructions to convert to setting the 's' flag, we need to look 
at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.

llvm-svn: 117950
 2010-11-01 20:41:43 +00:00
Jakob Stoklund Olesen
66012df062 Don't assign new registers created during a split to the same stack slot, but 
give them individual stack slots once the are actually spilled.

llvm-svn: 117945
 2010-11-01 19:49:57 +00:00
Jakob Stoklund Olesen
b4a55702b7 Add basic LiveStacks verification. 
When an instruction refers to a spill slot with a LiveStacks entry, check that
the spill slot is live at the instruction.

llvm-svn: 117944
 2010-11-01 19:49:52 +00:00
Bob Wilson
a9c593e696 NEON does not support truncating vector stores. Radar 8598391. 
llvm-svn: 117940
 2010-11-01 18:31:39 +00:00
Jim Grosbach
acc28d1b2a Add FIXME. 
llvm-svn: 117936
 2010-11-01 18:11:14 +00:00
Jim Grosbach
53d2661c60 Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates 
codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931
 2010-11-01 17:08:58 +00:00
Rafael Espindola
2f114f8430 Write the line info to .debug_line. 
llvm-svn: 117930
 2010-11-01 17:07:14 +00:00
Jim Grosbach
76910aa62f Mark ARM subtarget features that are available for the assembler. 
llvm-svn: 117929
 2010-11-01 16:59:54 +00:00
Jim Grosbach
2605b2b54f trailing whitespace 
llvm-svn: 117927
 2010-11-01 16:44:21 +00:00
Rafael Espindola
5571ce5ed4 Move EmitInstruction to MCObjectStreamer so that ELF and MachO can share it. 
llvm-svn: 117925
 2010-11-01 16:27:31 +00:00
Jim Grosbach
311aa5e22f The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the 
patterns as such

llvm-svn: 117923
 2010-11-01 15:59:52 +00:00
Rafael Espindola
a7f92c500c Add support for .value. 
llvm-svn: 117922
 2010-11-01 15:29:07 +00:00
Rafael Espindola
7a38cb0144 Implement .weakref. 
llvm-svn: 117911
 2010-11-01 14:28:48 +00:00
Bill Wendling
da3d0ce7b5 Move instruction encoding bits into the parent class and remove the temporary 
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.

llvm-svn: 117906
 2010-11-01 06:00:39 +00:00
Bill Wendling
70856991c5 The testcase is now XFAILed. Sorry about the breakage. 
llvm-svn: 117904
 2010-11-01 05:50:55 +00:00
Chris Lattner
d595d1f4d7 "mov[zs]x (mem), GR16" are not ambiguous: the mem 
must be 8 bits.  Support this memory form.

llvm-svn: 117902
 2010-11-01 05:41:10 +00:00
Chris Lattner
81d051481e Implement enough of the missing instalias support to get 
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901
 2010-11-01 05:34:34 +00:00
Chris Lattner
0a4807eefc make the asm matcher emitter reject instructions that have comments 
in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897
 2010-11-01 04:44:29 +00:00
Chris Lattner
9da275f86b reject instructions that contain a \n in their asmstring. Mark 
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884
 2010-11-01 00:46:16 +00:00
Eric Christopher
7295ed492c Revert r117876 for now, it's causing more testsuite failures. 
llvm-svn: 117879
 2010-10-31 22:42:55 +00:00
Bill Wendling
13936421e6 Disable the peephole optimizer until 186.crafty on armv6 is fixed. This is what 
looks like is happening:

Without the peephole optimizer:
  (1)   sub     r6, r6, #32
        orr     r12, r12, lr, lsl r9
        orr     r2, r2, r3, lsl r10
  (x)   cmp     r6, #0
        ldr     r9, LCPI2_10
        ldr     r10, LCPI2_11
  (2)   sub     r8, r8, #32
  (a)   movge   r12, lr, lsr r6
  (y)   cmp     r8, #0
LPC2_10:
        ldr     lr, [pc, r10]
  (b)   movge   r2, r3, lsr r8

With the peephole optimizer:
        ldr     r9, LCPI2_10
        ldr     r10, LCPI2_11
  (1*)  subs    r6, r6, #32
  (2*)  subs    r8, r8, #32
  (a*)  movge   r12, lr, lsr r6
  (b*)  movge   r2, r3, lsr r8

(1) is used by (x) for the conditional move at (a). (2) is used by (y) for the
conditional move at (b). After the peephole optimizer, these the flags resulting
from (1*) are ignored and only the flags from (2*) are considered for both
conditional moves.

llvm-svn: 117876
 2010-10-31 22:07:12 +00:00
Nicolas Geoffray
6889997474 Attach a GCModuleInfo to a MachineFunction. 
llvm-svn: 117867
 2010-10-31 20:38:38 +00:00
Chris Lattner
a4c36d0efe fix the !eq operator in tblgen to return a bit instead of an int. 
Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862
 2010-10-31 19:22:57 +00:00
Chris Lattner
5d088218e5 two changes: make the asmmatcher generator ignore ARM pseudos properly, 
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861
 2010-10-31 19:15:18 +00:00
Chris Lattner
01acd65875 reapply r117858 with apparent editor malfunction fixed (somehow I 
got a dulicated line).

llvm-svn: 117860
 2010-10-31 19:10:56 +00:00
Chris Lattner
8132a182e7 revert r117858 while I check out a failure I missed. 
llvm-svn: 117859
 2010-10-31 19:05:32 +00:00
Chris Lattner
70b05a5b88 the asm matcher can't handle operands with modifiers (like ${foo:bar}). 
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858
 2010-10-31 18:48:12 +00:00
Chris Lattner
8aaac91ca4 sketch out the planned instruction alias mechanism, add some comments about 
how the push/pop mnemonic aliases are wrong.

llvm-svn: 117857
 2010-10-31 18:43:46 +00:00
Duncan Sands
92f33ea784 Factorize the duplicated logic for choosing the right argument 
calling convention out of the fast and normal ISel files, and
into the calling convention TD file.

llvm-svn: 117856
 2010-10-31 13:21:44 +00:00
Duncan Sands
0f49c49476 Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86, 
which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.

llvm-svn: 117855
 2010-10-31 13:02:38 +00:00
Rafael Espindola
660b7f5c4a Add support for files with more than 65280 sections. No testcase since 
it would be a bit too big :-)

llvm-svn: 117849
 2010-10-31 00:16:26 +00:00
Eric Christopher
e012ee8db9 Make sure we have a legal type (and simple) before continuing. 
llvm-svn: 117848
 2010-10-30 21:25:26 +00:00
Chris Lattner
49227ad505 Resolve a terrible hack in tblgen: instead of hardcoding 
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.

llvm-svn: 117831
 2010-10-30 19:38:20 +00:00
Chris Lattner
15e92ddd01 Implement (and document!) support for MnemonicAlias's to have Requires 
directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.

llvm-svn: 117830
 2010-10-30 19:23:13 +00:00
Chris Lattner
441672d7cb really zap alias. 
llvm-svn: 117824
 2010-10-30 18:23:25 +00:00
Chris Lattner
ba9271be5b move fcompi alias to .td file and zap some useless code. 
llvm-svn: 117823
 2010-10-30 18:22:53 +00:00
Chris Lattner
1b3b2e113f move rep aliases to td file 
llvm-svn: 117822
 2010-10-30 18:17:33 +00:00
Chris Lattner
49f977366f move sal aliases to .td file. 
llvm-svn: 117821
 2010-10-30 18:14:54 +00:00
Chris Lattner
54892b4d8d fix an encoding mismatch where "sal %eax, 1" was not using the short encoding 
for shl.  Caught by inspection.

llvm-svn: 117820
 2010-10-30 18:13:10 +00:00
Chris Lattner
38179edecd move a bunch more aliases from .cpp -> .td file. 
llvm-svn: 117819
 2010-10-30 18:07:17 +00:00
Chris Lattner
ac7f4957b1 move cmov aliases to .td file. 
llvm-svn: 117818
 2010-10-30 17:56:50 +00:00
Chris Lattner
acec7b7d46 move setcc and jcc aliases from .cpp to .td 
llvm-svn: 117817
 2010-10-30 17:51:45 +00:00
Chris Lattner
e90ff8dcb6 move some code. 
llvm-svn: 117816
 2010-10-30 17:38:55 +00:00
Chris Lattner
7c61e4bca2 implement (and document!) the first kind of MC assembler alias, which 
just remaps one mnemonic to another.  Convert a few of the X86 aliases
from .cpp to .td code.

llvm-svn: 117815
 2010-10-30 17:36:36 +00:00
Duncan Sands
a8d9d6c6e3 Now that the MallocInst no longer exists, this workaround for 
it claiming not to have side-effects is no longer needed.

llvm-svn: 117789
 2010-10-30 16:12:16 +00:00
Jim Grosbach
b6c76a2662 Add FIXME. 
llvm-svn: 117787
 2010-10-30 14:54:23 +00:00
Jim Grosbach
951667ac39 Clean up comments. 
llvm-svn: 117785
 2010-10-30 13:48:28 +00:00
Duncan Sands
a7198342e7 If a function does a volatile load from a global constant, do not 
consider it to be readonly.  In fact, don't even consider it to be
readonly if it does a volatile load from an AllocaInst either (it
is debatable as to whether readonly would be correct or not in this
case; play safe for the moment).  This fixes PR8279.

llvm-svn: 117783
 2010-10-30 12:59:44 +00:00
Jim Grosbach
775afa274f Tidy up. 
llvm-svn: 117782
 2010-10-30 12:59:16 +00:00
Chris Lattner
45c679522d stay out of the reserved namespace 
llvm-svn: 117773
 2010-10-30 04:57:14 +00:00
Chris Lattner
deabc3d7fa simplify this code. 
llvm-svn: 117771
 2010-10-30 04:35:59 +00:00
Chris Lattner
3a36dd4a0b split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic. 
llvm-svn: 117769
 2010-10-30 04:09:10 +00:00
Jim Grosbach
298cac8db3 Avoid re-evaluating MI.getNumOperands() every iteration of the loop. 
llvm-svn: 117766
 2010-10-30 01:40:16 +00:00
Jakob Stoklund Olesen
b3b1db4e67 Include MachineBasicBlock numbers in viewCFG() output. 
llvm-svn: 117765
 2010-10-30 01:26:19 +00:00
Jakob Stoklund Olesen
035667c0d6 Make sure copies are inserted after any exception handling labels at the top of 
a basic block.

llvm-svn: 117764
 2010-10-30 01:26:16 +00:00
Jakob Stoklund Olesen
0ab92619d0 Add SkipPHIsAndLabels from PHIElimination to MachineBasicBlock. It is needed 
elsewhere.

llvm-svn: 117763
 2010-10-30 01:26:14 +00:00
Jakob Stoklund Olesen
b751dffc9f Disable more of physical register live intervals verification. 
llvm-svn: 117762
 2010-10-30 01:26:11 +00:00
Jakob Stoklund Olesen
4425035bfd Print out register class of spilled register. 
llvm-svn: 117761
 2010-10-30 01:26:09 +00:00
Bob Wilson
183c466006 Overhaul memory barriers in the ARM backend. Radar 8601999. 
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

llvm-svn: 117756
 2010-10-30 00:54:37 +00:00
Jim Grosbach
996d1280bd Encode the register list operands for ARM mode LDM/STM instructions. 
llvm-svn: 117753
 2010-10-30 00:37:59 +00:00
Bill Wendling
b68e0d0ee3 Some instructions end with an "ls" prefix, but it doesn't indicate that they are 
conditional. Check for those instructions explicitly.

llvm-svn: 117747
 2010-10-29 23:50:21 +00:00
Evan Cheng
d81c33d91e Teach machine cse to eliminate instructions with multiple physreg uses and defs. rdar://8610857. 
llvm-svn: 117745
 2010-10-29 23:36:03 +00:00
Jim Grosbach
9a473e23b8 Remove hard tab characters. 
llvm-svn: 117742
 2010-10-29 23:23:15 +00:00
Jim Grosbach
7ca6ac347d 80 column fix. 
llvm-svn: 117741
 2010-10-29 23:21:57 +00:00
Jim Grosbach
038d376c59 trailing whitespace 
llvm-svn: 117740
 2010-10-29 23:21:03 +00:00
Jim Grosbach
7cf8dcc5bd s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand 
encoder functions.

llvm-svn: 117738
 2010-10-29 23:19:55 +00:00
Evan Cheng
7695213793 Fix fpscr <-> GPR latency info. 
llvm-svn: 117737
 2010-10-29 23:16:55 +00:00
Rafael Espindola
0d9ac34ffa Be more strict on when we produce an undefined reference. In gas a file with 
just

.type   foo,@object

will produce an undefined reference to foo. On the other hand, a file with
just

.weakref bar, foo

will not. It is somewhat hard to support both in MC since both statements
should create the symbols. It should be possible if we really need to by
adding to the flags, but hopefully that is not necessary.

With this patch we do not produce a undefined reference in any of those cases.
The assembly file needs an actual use for the undefined reference to be
present.

This is in preparation for a patch implementing .weakref.

llvm-svn: 117735
 2010-10-29 23:09:31 +00:00
Bob Wilson
d84c4629c1 Clean up indentation and other whitespace. 
llvm-svn: 117728
 2010-10-29 22:20:45 +00:00
Bob Wilson
9297637759 Remove trailing whitespace. 
llvm-svn: 117727
 2010-10-29 22:20:43 +00:00
Bob Wilson
59dedc2629 Fix 80-column violation. 
llvm-svn: 117722
 2010-10-29 22:03:07 +00:00
Bob Wilson
d7f24e831f Change instcombine's getShuffleMask to represent undef with negative values. 
This code had previously used 2*N, where N is the mask length, to represent
undef.  That is not safe because the shufflevector operands may have more
than N elements -- they don't have to match the result type.

llvm-svn: 117721
 2010-10-29 22:03:05 +00:00
Bob Wilson
d67dddb134 Remove DAG combiner patch to fold vector splats. Instcombiner does it now. 
llvm-svn: 117720
 2010-10-29 22:03:02 +00:00
Bob Wilson
996353fb5d Make instcombine a little more aggressive in combining vector shuffles. 
Allow splats even if they don't match either of the original shuffles,
possibly due to undef entries in the shuffles masks.  Radar 8597790.
Also fix some 80-column violations.

llvm-svn: 117719
 2010-10-29 22:02:50 +00:00
Jim Grosbach
e811e91d02 add FIXME 
llvm-svn: 117718
 2010-10-29 21:56:51 +00:00
Jim Grosbach
fcfc42b7bb Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in 
the ARMExpandPseudos pass rather than during the asm lowering.

llvm-svn: 117714
 2010-10-29 21:35:25 +00:00
Eric Christopher
bf7cf2a203 Handle comparison values we already have - this fixes the consumer-typeset 
failure for llvm-gcc on arm fast isel.

llvm-svn: 117710
 2010-10-29 21:08:19 +00:00
Owen Anderson
b41f027059 Give up on doing in-line instruction simplification during correlated value propagation. Instruction simplification 
needs to be guaranteed never to be run on an unreachable block.  However, earlier block simplifications may have
changed the CFG to make block that were reachable when we began our iteration unreachable by the time we try to
simplify them. (Note that this also means that our depth-first iterators were potentially being invalidated).

This should not have a large impact on code quality, since later runs of instcombine should pick up these simplifications.
Fixes PR8506.

llvm-svn: 117709
 2010-10-29 21:05:17 +00:00
Jim Grosbach
93fbda05ee ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to 
handle it in the asm lowering.

llvm-svn: 117707
 2010-10-29 20:37:06 +00:00
Jim Grosbach
52638aa1c8 Fix typo. 
llvm-svn: 117703
 2010-10-29 20:21:49 +00:00
Jim Grosbach
4ca61d9877 ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS. 
llvm-svn: 117702
 2010-10-29 20:21:36 +00:00
Dan Gohman
85557399a1 Make ScalarEvolution::forgetLoop forget all contained loops too, because 
they may have ValuesAtScopes map entries referencing their outer loops.
This fixes a user-after-free reported in PR8471.

llvm-svn: 117698
 2010-10-29 20:16:10 +00:00
Jim Grosbach
162e3345fb ARM mode LDREX*/STREX* binary encodings. 
llvm-svn: 117695
 2010-10-29 19:58:57 +00:00
Jim Grosbach
5bc94b46a9 Encoding information for ARM conditional move instructions. 
llvm-svn: 117687
 2010-10-29 19:28:17 +00:00
Jakob Stoklund Olesen
469a9ef414 Fix sign error. 
llvm-svn: 117677
 2010-10-29 18:21:18 +00:00
Evan Cheng
392d2cbdcc Avoiding overly aggressive latency scheduling. If the two nodes share an 
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.

BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB

=>

BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB

This fixed the recent 256.bzip2 regression.

llvm-svn: 117675
 2010-10-29 18:09:28 +00:00
Evan Cheng
92293993bd - Don't schedule nodes with only MVT::Flag and MVT::Other values for latency. 
- Compute CopyToReg use operand latency correctly.

llvm-svn: 117674
 2010-10-29 18:07:31 +00:00
Jakob Stoklund Olesen
1f2fb9a020 Don't transfer unused values to the new intervals formed by splitting. 
llvm-svn: 117673
 2010-10-29 17:47:49 +00:00
Jim Grosbach
edec5cc6b8 Handle ARM addrmode5 instructions with an offset. 
llvm-svn: 117672
 2010-10-29 17:41:25 +00:00
Benjamin Kramer
d84e7a7b91 Silence Release build warnings. 
llvm-svn: 117671
 2010-10-29 17:40:05 +00:00
Jakob Stoklund Olesen
d56c4457a6 Teach ConnectedVNInfoEqClasses::Classify to deal with unused values. 
We don't want unused values forming their own equivalence classes, so we lump
them all together in one class, and then merge them with the class of the last
used value.

llvm-svn: 117670
 2010-10-29 17:37:29 +00:00
Jakob Stoklund Olesen
e577489ba5 Never propagate the idom value out of a block that defines its own value. 
llvm-svn: 117669
 2010-10-29 17:37:25 +00:00
John Thompson
6115a7f1d4 Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. 
llvm-svn: 117667
 2010-10-29 17:29:13 +00:00
Dan Gohman
85403d8246 Check if ErrMsg is null. This fixes the "not" command. 
llvm-svn: 117666
 2010-10-29 17:20:42 +00:00
Dan Gohman
6a889e86df Fix these error messages to be less confusing. These error 
messages primarily indicate errors running the viewer, not
errors with the graph file itself.

llvm-svn: 117665
 2010-10-29 17:03:40 +00:00
Dan Gohman
b27988e5bd Make Program::Wait differentiate execution failure due to the file 
being not found from the file being not executable. 

llvm-svn: 117664
 2010-10-29 16:54:25 +00:00
Jim Grosbach
6f257bd31b Revert 117660. Apparently it's not as trivial as that... 
llvm-svn: 117663
 2010-10-29 16:50:53 +00:00
Dan Gohman
a80b1afde3 Make Program::Wait provide an error message string for errors 
executing the child process and abnormal child process termination.

llvm-svn: 117661
 2010-10-29 16:39:01 +00:00
Jim Grosbach
8c9a2ee86e ARM addrmode5 instructions have neither writeback nor post-indexed modes. 
llvm-svn: 117660
 2010-10-29 16:38:59 +00:00
Jim Grosbach
29961ebfc5 Trailing whitespace. 
llvm-svn: 117651
 2010-10-29 14:46:02 +00:00
Benjamin Kramer
f2442da5f6 ARMAsmParser: Plug a memory leak. 
llvm-svn: 117648
 2010-10-29 09:43:39 +00:00
Eric Christopher
930a767468 Add an unreachable to silence warning - the switch is actually 
fully enumerated.

llvm-svn: 117647
 2010-10-29 09:26:59 +00:00
Bill Wendling
d9412db2c8 This may be an ARM target, so check for _Unwind_SjLj_Resume. 
llvm-svn: 117643
 2010-10-29 07:46:01 +00:00
Dan Gohman
753c9ce807 Teach memdep to use pointsToConstantMemory to determine that loads 
from constant memory don't alias any stores.

llvm-svn: 117636
 2010-10-29 01:14:04 +00:00
Jakob Stoklund Olesen
b7a4b7a7b0 Fix broken equivalence class calculation. We could probably also use 
EquvivalenceClasses.h except it looks like overkill when elements are continuous
integers.

llvm-svn: 117631
 2010-10-29 00:40:59 +00:00
Jakob Stoklund Olesen
1210a5145a Print out the connected components in the verifier after complaining about their 
multiplicity.

llvm-svn: 117630
 2010-10-29 00:40:57 +00:00
Jakob Stoklund Olesen
e446520687 Run a verification pass before any splitting to better distribute blame. 
llvm-svn: 117629
 2010-10-29 00:40:55 +00:00
Chris Lattner
115cd02d22 add simple support for addrmode5 operands, allowing 
vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.

llvm-svn: 117626
 2010-10-29 00:27:31 +00:00
Devang Patel
bf9c3c8947 Ignore empty blocks. 
llvm-svn: 117615
 2010-10-28 22:11:59 +00:00
Chris Lattner
ef237e6013 give better error diagnostics, for example: 
t.s:1:14: error: invalid operand for instruction
vldr.64	d17, [r0]   
       	     ^

instead of:

t.s:1:1: error: unrecognized instruction
vldr.64	d17, [r0]   
^

llvm-svn: 117611
 2010-10-28 21:41:58 +00:00
Chris Lattner
ba1e908431 hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes 
the opcode string in the inst dump, e.g.:
	vmov	r2, r3, d17             @ encoding: [0x31,0x2b,0x53,0xec]
                                        @ <MCInst #989 VMOVRRD
                                        @  <MCOperand Reg:68>
                                        @  <MCOperand Reg:69>
                                        @  <MCOperand Reg:19>
                                        @  <MCOperand Imm:14>
                                        @  <MCOperand Reg:0>>

The "VMOVRRD" is new.

llvm-svn: 117609
 2010-10-28 21:37:33 +00:00
Rafael Espindola
913ce7ebc8 Improvements to .section parsing: 
* If we have a M or a G, reject sections without the type
* Only parse the flag specific arguments if we have M or G
* Parse the corresponding arguments for M and G

We ignore the G arguments and flag for now.

llvm-svn: 117608
 2010-10-28 21:33:33 +00:00
Chris Lattner
4210ffb9c5 move a method out of line. 
llvm-svn: 117605
 2010-10-28 21:28:01 +00:00
Chris Lattner
b6c7a9e204 remove the rest of hte owningptr's, no functionality change. 
llvm-svn: 117603
 2010-10-28 20:52:15 +00:00
Jakob Stoklund Olesen
c570151dc2 One day, physical register live ranges will be sensible. 
llvm-svn: 117602
 2010-10-28 20:44:22 +00:00
Jakob Stoklund Olesen
ccbfbefd93 Replace SplitKit SSA update with an iterative algorithm very similar to the one 
in SSAUpdaterImpl.h

Verifying live intervals revealed that the old method was completely wrong, and
we need an iterative approach to calculating PHI placemant. Fortunately, we have
MachineDominators available, so we don't have to compute that over and over
like SSAUpdaterImpl.h must.

Live-out values are cached between calls to mapValue() and computed in a greedy
way, so most calls will be working with very small block sets.

Thanks to Bob for explaining how this should work.

llvm-svn: 117599
 2010-10-28 20:34:52 +00:00
Jakob Stoklund Olesen
6f4262448e Make MachineDominators available for SplitEditor. We are going to need it for 
proper SSA updating.

This doesn't cause MachineDominators to be recomputed since we are already
requiring MachineLoopInfo which uses dominators as well.

llvm-svn: 117598
 2010-10-28 20:34:50 +00:00
Jakob Stoklund Olesen
35f9c58245 Add a temporary command line option to verify machine code after each spill or 
split.

llvm-svn: 117597
 2010-10-28 20:34:47 +00:00
Dan Gohman
d512ed689c Revert r117582, which reverted r77396. Searching PATH for a string 
which contains slashes is inconsistent with the meaning of PATH on
Unix-type platforms, and pretty surprising.

If the user has given a specific path to execute and we can't
execute it, we should fail and say why.  (Apparently the new
posix_spawn code doesn't always say why, but that's a separate
issue.)

llvm-svn: 117596
 2010-10-28 20:34:33 +00:00
Rafael Espindola
b562975139 Add support for the .string directive. 
llvm-svn: 117592
 2010-10-28 20:02:27 +00:00
Devang Patel
a496603faf Do not work too hard to find type's file info. There is a special field to record file info. 
llvm-svn: 117588
 2010-10-28 19:50:08 +00:00
Rafael Espindola
f230319275 Defined weak symbols should have non-zero value. 
llvm-svn: 117585
 2010-10-28 19:39:57 +00:00
Mikhail Glushenkov
8988adb7db llvmc: Make ExecuteProgram() look in the driver directory first. 
llvm-svn: 117584
 2010-10-28 19:33:08 +00:00
Mikhail Glushenkov
7ee0f678cb Remove an unnecessary check and an unnecessary temporary. 
llvm-svn: 117583
 2010-10-28 19:33:04 +00:00
Mikhail Glushenkov
b727c53cff Revert r77396. 
Original commit message:

    On "Unix", if Program::FindProgramByName is given a name containing
    slashes, just go with it, regardless of whether it looks like it will
    be executable. This follows the behavior of sh(1) more closely.

It's better when behaviour is consistent between platforms. This change also
makes FindExecutable() behave as expected on unix-likes (before this commit, it
used to always succeed).

llvm-svn: 117582
 2010-10-28 19:32:58 +00:00
Mikhail Glushenkov
e2c628c84f Trailing whitespace. 
llvm-svn: 117581
 2010-10-28 19:32:53 +00:00
Rafael Espindola
862d688cbd Fix relocations with renamed symbols. 
llvm-svn: 117575
 2010-10-28 19:08:03 +00:00
Benjamin Kramer
fbfb8cf5f8 Reduce malloc thrashing. 
llvm-svn: 117572
 2010-10-28 18:41:23 +00:00
Jim Grosbach
d02c1c7d77 PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. 
llvm-svn: 117571
 2010-10-28 18:34:10 +00:00
Rafael Espindola
e62cf892ae Aliases defined with .symver should copy the binding of the symbols they alias. 
Move the existing patching for undefined symbols so that all the patching
is done in the same function.

llvm-svn: 117570
 2010-10-28 18:33:03 +00:00
Devang Patel
0e43a2d84f Technically DIFile scope should also be handled here. 
llvm-svn: 117563
 2010-10-28 17:30:52 +00:00
Chris Lattner
0a21ad2553 rearrange ParseRegisterList. 
llvm-svn: 117560
 2010-10-28 17:23:41 +00:00
Chris Lattner
a9c0f00f10 refactor some code to simplify it, eliminating some owningptr's. 
llvm-svn: 117559
 2010-10-28 17:20:03 +00:00
Bob Wilson
65124cd7c7 Teach the DAG combiner to fold a splat of a splat. Radar 8597790. 
Also do some minor refactoring to reduce indentation.

llvm-svn: 117558
 2010-10-28 17:06:14 +00:00
Roman Divacky
2aedee6ff2 Use the IDVal directly as there's no need to convert to std::string. 
Pointed out by Chris!

llvm-svn: 117557
 2010-10-28 16:57:58 +00:00
Roman Divacky
8555f153e9 Implement .equ directive as a synonym to .set. 
llvm-svn: 117553
 2010-10-28 16:22:58 +00:00
Duncan Sands
eccf0b18a5 Fix PR8494: when reading invalid bitcode, getTypeByID may return 
a null pointer.

llvm-svn: 117551
 2010-10-28 15:47:26 +00:00
Rafael Espindola
ff7e4e4e43 Implement R_X86_64_DTPOFF32. 
llvm-svn: 117548
 2010-10-28 15:11:03 +00:00
Rafael Espindola
1d1ff5485c Implement TLSLD. 
llvm-svn: 117547
 2010-10-28 15:02:40 +00:00
Rafael Espindola
8372247e83 Implement DTPOFF. 
llvm-svn: 117546
 2010-10-28 14:48:59 +00:00
Rafael Espindola
c44c5b374a Implement TLSLDM. 
llvm-svn: 117544
 2010-10-28 14:37:09 +00:00
Rafael Espindola
d8ef67f8b9 Implement VK_GOTNTPOFF and switch RelocNeedsGOT to use VariantKind. 
llvm-svn: 117543
 2010-10-28 14:22:44 +00:00