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Author SHA1 Message Date
Duncan Sands
3bf2a701a5 In the calling convention logic, ValVT is always a legal type, 
and as such can be represented by an MVT - the more complicated
EVT is not needed.  Use MVT for ValVT everywhere.

llvm-svn: 118245
 2010-11-04 10:49:57 +00:00
Evan Cheng
165e65f53a Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli. 
llvm-svn: 118237
 2010-11-04 05:19:35 +00:00
Daniel Dunbar
06d64897d3 System: Add llvm_execute_on_thread, which does what it says. 
- Primarily useful for running some code with a specified stack size, when
   pthreads are available.

llvm-svn: 118222
 2010-11-04 01:26:25 +00:00
Jim Grosbach
9766b186b6 Add ARM fixup info for load/store label references. Probably will need a bit of 
tweaking when we start using it for object file emission or JIT, but it's a
start.

llvm-svn: 118221
 2010-11-04 01:12:30 +00:00
Bill Wendling
990c247994 Add encoding for VSTR. 
llvm-svn: 118220
 2010-11-04 00:59:42 +00:00
Jakob Stoklund Olesen
aa7acbe740 Disable fancy splitting during spilling unless -extra-spiller-splits is given. 
This way, InlineSpiller does the same amount of splitting as the standard
spiller. Splitting should really be guided by the register allocator, and
doesn't belong in the spiller at all.

llvm-svn: 118216
 2010-11-04 00:32:32 +00:00
Jim Grosbach
af6104d4bf Teach ARM Target to use the tblgen support for generating an MC'ized 
CodeEmitter.

llvm-svn: 118209
 2010-11-03 23:52:49 +00:00
Owen Anderson
d144bb1ddc Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization. 
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.

llvm-svn: 118204
 2010-11-03 23:15:26 +00:00
Owen Anderson
1a89511e5d Add support for code generation of the one register with immediate form of vorr. 
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.

llvm-svn: 118201
 2010-11-03 22:44:51 +00:00
Jim Grosbach
6c197e41bf trailing whitespace 
llvm-svn: 118199
 2010-11-03 22:03:20 +00:00
Eric Christopher
3f1ac311ff Just return undef for invalid masks or elts, and since we're doing that, 
just do it earlier too.

llvm-svn: 118195
 2010-11-03 20:44:42 +00:00
Jakob Stoklund Olesen
13bf5713f2 Let RegAllocBasic require MachineDominators - they are already available and 
splitting needs them.

llvm-svn: 118194
 2010-11-03 20:39:26 +00:00
Jakob Stoklund Olesen
7dc4b810ed Tag debug output as regalloc 
llvm-svn: 118193
 2010-11-03 20:39:23 +00:00
Eric Christopher
6b586a109e Optimize generated code for integer materialization a bit. 
llvm-svn: 118192
 2010-11-03 20:21:17 +00:00
Owen Anderson
98f9965c89 Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead, 
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.

llvm-svn: 118183
 2010-11-03 18:16:27 +00:00
Bob Wilson
f44e708279 Add codegen patterns for VST1-lane instructions. Radar 8599955. 
llvm-svn: 118176
 2010-11-03 16:24:53 +00:00
Bob Wilson
0ec96428ba Check for extractelement with a variable operand for the element number. 
For NEON we had been assuming this was always an immediate constant.

llvm-svn: 118175
 2010-11-03 16:24:50 +00:00
Mikhail Glushenkov
991857f132 Rename FindExecutable to PrependMainExecutablePath. 
Makes it more clear that it is just a path manipulation function.

llvm-svn: 118174
 2010-11-03 16:14:16 +00:00
Duncan Sands
1028fd63a0 Rename PointsToLocalMemory to PointsToLocalOrConstantMemory to make 
the code more self-documenting.

llvm-svn: 118171
 2010-11-03 14:45:05 +00:00
Duncan Sands
41edf30895 Simplify uses of MVT and EVT. An MVT can be compared directly 
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.

llvm-svn: 118169
 2010-11-03 12:17:33 +00:00
Duncan Sands
f6e5e02c9b Inside the calling convention logic LocVT is always a simple 
value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.

llvm-svn: 118167
 2010-11-03 11:35:31 +00:00
Eric Christopher
719d9d324b If we have an undef mask our Elt will be -1 for our access, handle 
this by using an undef as a pointer.

Fixes rdar://8625016

llvm-svn: 118164
 2010-11-03 09:36:40 +00:00
Evan Cheng
eab7251695 Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. 
llvm-svn: 118160
 2010-11-03 06:34:55 +00:00
Evan Cheng
b41703bc2f Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. 
llvm-svn: 118152
 2010-11-03 05:14:24 +00:00
Bill Wendling
3894287c96 Put the PC encoding in the correct bit position. 
llvm-svn: 118151
 2010-11-03 04:57:44 +00:00
Eric Christopher
bc79fa1c9e Invert these branches by default, it makes assembly comparisons a little 
easier to read.

llvm-svn: 118148
 2010-11-03 04:29:11 +00:00
Bill Wendling
34599f4aa8 The MC code couldn't handle ARM LDR instructions with negative offsets: 
vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.

llvm-svn: 118144
 2010-11-03 01:49:29 +00:00
Dan Gohman
8071a75d31 Fix DAGCombiner to avoid going into an infinite loop when it 
encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff).
This fixes rdar://8606584.

llvm-svn: 118143
 2010-11-03 01:47:46 +00:00
Jim Grosbach
90a084bac2 Remove unused function. 
llvm-svn: 118141
 2010-11-03 01:35:15 +00:00
Jim Grosbach
d3213d4048 Remove the no longer used 'Modifier' optional operand to the ARM 
printOperand() asm printer helper functions. rdar://8425198

llvm-svn: 118140
 2010-11-03 01:11:15 +00:00
Jim Grosbach
4d6b503b4c Remove unused function. 
llvm-svn: 118139
 2010-11-03 01:07:48 +00:00
Jim Grosbach
c10d3f3d4b Break ARM addrmode4 (load/store multiple base address) into its constituent 
parts. Represent the operation mode as an optional operand instead.
rdar://8614429

llvm-svn: 118137
 2010-11-03 01:01:43 +00:00
Evan Cheng
67db408634 Two sets of changes. Sorry they are intermingled. 
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
   "optimize for latency". Call instructions don't have the right latency and
   this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
   not # of micro-ops since multi-latency instructions is completely executed
   even when the predicate is false. Also, some instruction will be "slower"
   when they are predicated due to the register def becoming implicit input.
   rdar://8598427

llvm-svn: 118135
 2010-11-03 00:45:17 +00:00
Evan Cheng
e156473432 Modify scheduling itineraries to correct instruction latencies (not operand 
latencies) of loads.

llvm-svn: 118134
 2010-11-03 00:40:22 +00:00
Dan Gohman
69a6379472 Print an error as one big string instead of breaking it up. 
llvm-svn: 118130
 2010-11-03 00:24:33 +00:00
Dan Gohman
36d08298f4 Delete unused variables. 
llvm-svn: 118128
 2010-11-03 00:09:12 +00:00
Dan Gohman
4ad5745d44 Remove several unhelpful checks for isValid from sys::Path. 
llvm-svn: 118127
 2010-11-03 00:01:23 +00:00
Eric Christopher
b817a3e8fe Make sure we're only storing a single bit here. 
llvm-svn: 118126
 2010-11-02 23:59:09 +00:00
Chris Lattner
73111ecc25 per a suggestion by Frits van Bommel, mark all MBlaze Pseudo 
instructions as isCodeGenOnly in the parent class instead of
sprinkling it throughout the .td files.

llvm-svn: 118125
 2010-11-02 23:57:05 +00:00
Owen Anderson
f754738bbb Revert r118097 to fix buildbots. 
llvm-svn: 118121
 2010-11-02 23:47:29 +00:00
Chris Lattner
d3f7a5d3bd Completely reject instructions that have an operand in their 
ins/outs list that isn't specified by their asmstring.  Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right.  Mark a bunch of ARM instructions that use this as 
isCodeGenOnly.  Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).

llvm-svn: 118119
 2010-11-02 23:40:41 +00:00
Jakob Stoklund Olesen
ea31f5aadd Let the -inline-threshold command line argument take precedence over the 
threshold given to createFunctionInliningPass().

Both opt -O3 and clang would silently ignore the -inline-threshold option.

llvm-svn: 118117
 2010-11-02 23:40:26 +00:00
Dan Gohman
3a69090d70 Don't try to enforce MAXPATHLEN in sys::Path for Unix. OS's can check 
limits on their own.

llvm-svn: 118113
 2010-11-02 23:19:55 +00:00
Dan Gohman
ea2d1eb5d4 Simplify. 
llvm-svn: 118110
 2010-11-02 23:16:26 +00:00
Dan Gohman
1250781030 Fix a copy+pasto. 
llvm-svn: 118106
 2010-11-02 22:56:51 +00:00
Dan Gohman
1c41b20c57 Avoid manipulating paths in fixed-sized arrays. 
llvm-svn: 118105
 2010-11-02 22:55:34 +00:00
Bill Wendling
1fb9812066 Obsessive formatting changes. No functionality impact. 
llvm-svn: 118103
 2010-11-02 22:53:11 +00:00
Dan Gohman
ce8c453106 Simplify this code. 
llvm-svn: 118102
 2010-11-02 22:50:10 +00:00
Bill Wendling
5ff380b14b Omit unused parameter name. 
llvm-svn: 118099
 2010-11-02 22:46:04 +00:00
Bill Wendling
f25c2b8895 Simplify the EncodeInstruction method now that a lot of the special case stuff 
is handled with the MC encoder.

llvm-svn: 118098
 2010-11-02 22:44:12 +00:00
Owen Anderson
ea89766d0c Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning. 
llvm-svn: 118097
 2010-11-02 22:41:42 +00:00
Dan Gohman
78b47498e3 Use '\0' instead of 0 for nul character constants. 
llvm-svn: 118096
 2010-11-02 22:41:19 +00:00
Bill Wendling
1546322a9c Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work 
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.

llvm-svn: 118094
 2010-11-02 22:31:46 +00:00
Owen Anderson
8aba4dbe03 Rename encoder methods to match naming convention. 
llvm-svn: 118093
 2010-11-02 22:28:01 +00:00
Chris Lattner
5caaacef3b mark a few codegenonly instructions. 
llvm-svn: 118092
 2010-11-02 22:26:33 +00:00
Mikhail Glushenkov
79047e7eb3 appendSuffix: don't append a dot when the suffix is empty. 
Additionally, move the implementation of appendSuffix to Path.cpp: it is
platform-independent.

llvm-svn: 118089
 2010-11-02 22:18:37 +00:00
Mikhail Glushenkov
97788c1061 Revert r118057, this is better fixed in appendSuffix itself. 
llvm-svn: 118088
 2010-11-02 22:18:28 +00:00
Owen Anderson
cdd587157f Provide correct encodings for the remaining vst variants that we currently generate. 
llvm-svn: 118087
 2010-11-02 22:18:18 +00:00
Dan Gohman
446b7f5e51 Eliminate some temporary std::strings. 
llvm-svn: 118086
 2010-11-02 22:07:47 +00:00
Owen Anderson
1f88ac90a1 Tentative encodings for the "single element from one lane" variant of vst1. 
llvm-svn: 118084
 2010-11-02 21:54:45 +00:00
Owen Anderson
46d4ab1a87 Add correct encodings for basic variants for vst3 and vst4. 
llvm-svn: 118082
 2010-11-02 21:47:03 +00:00
Rafael Espindola
daf6328eb0 Do relaxations with FT_Org fragments. Fixes the FIXME: 
// FIXME: We should compute this sooner, we don't want to recurse here, and
    // we would like to be more functional.

In MCAssembler::ComputeFragmentSize.

llvm-svn: 118080
 2010-11-02 21:38:23 +00:00
Bob Wilson
248c691f9a Add NEON VST1-lane instructions. Partial fix for Radar 8599955. 
llvm-svn: 118069
 2010-11-02 21:18:25 +00:00
Owen Anderson
36d5c04fbd Add correct encodings for the basic variants for vst2. 
llvm-svn: 118068
 2010-11-02 21:16:58 +00:00
Owen Anderson
c9f6909c96 Add correct encodings for the basic form of vst1. 
llvm-svn: 118067
 2010-11-02 21:06:06 +00:00
Dan Gohman
84ceaa19a4 Micro-optimize. 
llvm-svn: 118058
 2010-11-02 20:52:47 +00:00
Dan Gohman
172e1824d0 Don't append a dot on platforms which don't use exe suffixes. 
llvm-svn: 118057
 2010-11-02 20:49:48 +00:00
Mikhail Glushenkov
e41fe39fe7 llvmc: Fix tool finding logic. 
llvm-svn: 118056
 2010-11-02 20:47:41 +00:00
Owen Anderson
b34a5f1d02 Factor out a common encoding class for loads and stores with a lane parameter. 
llvm-svn: 118055
 2010-11-02 20:47:39 +00:00
Devang Patel
9af731f560 Fix DIType verifier. The element 3 is DIFile now. 
llvm-svn: 118054
 2010-11-02 20:41:13 +00:00
Owen Anderson
ee1337c01f Add correct encodings for the rest of the vld instructions that we generate. 
llvm-svn: 118053
 2010-11-02 20:40:59 +00:00
Mikhail Glushenkov
4c2caa10ad GetDLLSuffix: Remove the leading dot from LTDL_SHLIB_EXT. 
This allows using GetDLLSuffix() with appendSuffix().

llvm-svn: 118051
 2010-11-02 20:32:59 +00:00
Mikhail Glushenkov
709ca9117a Trailing whitespace. 
llvm-svn: 118050
 2010-11-02 20:32:52 +00:00
Mikhail Glushenkov
4077e2da6f FindExecutable: remove the executability check. 
This makes the behaviour of FindExecutable more consistent across platforms, but
I'm not very happy with the name...

llvm-svn: 118049
 2010-11-02 20:32:46 +00:00
Mikhail Glushenkov
b1d2a5ac52 Make FindProgramByName return paths with slashes unmodified on Windows. 
This makes its behaviour more consistent across platforms.

llvm-svn: 118048
 2010-11-02 20:32:39 +00:00
Mikhail Glushenkov
efb9f9754d 80-col violations. 
llvm-svn: 118045
 2010-11-02 20:32:31 +00:00
Mikhail Glushenkov
c86f1d26e9 Path: Add GetEXESuffix() to complement GetDLLSuffix(). 
llvm-svn: 118042
 2010-11-02 20:32:26 +00:00
Andrew Trick
f861447393 Fixes <rdar://problem/8612856>: During postRAsched, the antidependence 
breaker needs to check all definitions of the antidepenent register to
avoid multiple defs of the same new register.

llvm-svn: 118032
 2010-11-02 18:16:45 +00:00
Dale Johannesen
b758b5a1a3 Apply patch for use-after-free in InlineAsm constant handling, 
PR 8522 / 8616046.  Test reduction, analysis and patch by Tim Deegan!
(However, review by someone who understands the classes here better
is welcome.  John Krum will return!)

llvm-svn: 118030
 2010-11-02 17:59:27 +00:00
Jim Grosbach
5fe61a5f86 Sort bit assignments. Cosmetic change only. 
llvm-svn: 118029
 2010-11-02 17:59:04 +00:00
Devang Patel
37fa9bb66a Simplify. 
llvm-svn: 118027
 2010-11-02 17:37:00 +00:00
Jim Grosbach
d6df785c6d Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke 
assumptions about stack layout. Specifically, LR must be saved next to FP.

llvm-svn: 118026
 2010-11-02 17:35:25 +00:00
Rafael Espindola
1db6a21aff Add support for expressions in .sleb/.uleb directives. 
llvm-svn: 118023
 2010-11-02 17:22:24 +00:00
Devang Patel
e3575ef54f If value map does not have register for an argument then try to find frame index before giving up. 
llvm-svn: 118022
 2010-11-02 17:19:03 +00:00
Devang Patel
efd9ac540a Use frameindex, if available, as a last resort to emit debug info for a parameter. 
llvm-svn: 118020
 2010-11-02 17:01:30 +00:00
Owen Anderson
9d85c89ade Add correct NEON encodings for vld2, vld3, and vld4 basic variants. 
llvm-svn: 117997
 2010-11-02 01:24:55 +00:00
Eric Christopher
a376fe69a1 Remove an assert - it's possible to be hit, and we just want to avoid 
handling those cases for now.

llvm-svn: 117996
 2010-11-02 01:24:49 +00:00
Eric Christopher
a033f49ed1 Whitespeace 
llvm-svn: 117995
 2010-11-02 01:22:45 +00:00
Eric Christopher
26ddb729bd No really, no thumb1 for arm fast isel. Also add an informative comment as 
to what someone would need to do to support thumb1.

llvm-svn: 117994
 2010-11-02 01:21:28 +00:00
Jakob Stoklund Olesen
840357ca6a Don't try to split weird critical edges that really aren't: 
BB#1: derived from LLVM BB %bb.nph28
    Live Ins: %AL
    Predecessors according to CFG: BB#0
	TEST8rr %reg16384<kill>, %reg16384, %EFLAGS<imp-def>; GR8:%reg16384
	JNE_4 <BB#2>, %EFLAGS<imp-use,kill>
	JMP_4 <BB#2>
    Successors according to CFG: BB#2 BB#2

These double CFG edges only ever occur in bugpoint-generated code, so there is
no need to attempt something clever.

llvm-svn: 117992
 2010-11-02 00:58:37 +00:00
Owen Anderson
f4ab06d0b6 Attempt to provide correct encodings for a number of other vld1 variants, which we can't test 
since we can neither generate nor parse them at the moment.

llvm-svn: 117988
 2010-11-02 00:24:52 +00:00
Owen Anderson
bdb861b46f Add aesthetic break. 
llvm-svn: 117986
 2010-11-02 00:14:00 +00:00
Owen Anderson
6647eb222b Add correct NEON encodings for the "multiple single elements" form of vld. 
llvm-svn: 117984
 2010-11-02 00:05:05 +00:00
Jakob Stoklund Olesen
56f67c7d02 MachineLICM should not claim to be preserving the CFG when it can split critical 
edges on demand.

llvm-svn: 117982
 2010-11-01 23:59:55 +00:00
Jakob Stoklund Olesen
b0f64b3d2b Be more precise about verifying missing kill flags. 
It is legal for an instruction to have two operands using the same register,
only one a kill. This is interpreted as a kill.

llvm-svn: 117981
 2010-11-01 23:59:53 +00:00
Jakob Stoklund Olesen
a052004a89 When inserting copies during splitting, always use the parent register as the 
source, and let rewrite() clean it up.

This way, kill flags on the inserted copies are fixed as well during rewrite().

We can't just assume that all the copies we insert are going to be kills since
critical edges into loop headers sometimes require both source and dest to be
live out of a block.

llvm-svn: 117980
 2010-11-01 23:59:48 +00:00
Jim Grosbach
e5a253a203 Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXME 
for handling the fixup necessary.

llvm-svn: 117978
 2010-11-01 23:45:50 +00:00
Jim Grosbach
d50562f0ea Remove unused function. 
llvm-svn: 117977
 2010-11-01 23:40:56 +00:00
Bob Wilson
411b511ac0 Add support for alignment operands on VLD1-lane instructions. 
This is another part of the fix for Radar 8599955.

llvm-svn: 117976
 2010-11-01 23:40:51 +00:00
Bill Wendling
dd4216420a Missed reverting this bit. 
llvm-svn: 117971
 2010-11-01 23:17:54 +00:00
Bill Wendling
37c9af176d Minor cleanup. 
llvm-svn: 117969
 2010-11-01 23:11:22 +00:00
Chris Lattner
f94c2b782a rearrange a bit. 
llvm-svn: 117967
 2010-11-01 23:07:52 +00:00
Bob Wilson
b6bc135df8 Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. 
llvm-svn: 117964
 2010-11-01 22:04:05 +00:00
Jakob Stoklund Olesen
0ed56c87e4 Add kill flag verification. 
At least X86FloatingPoint requires correct kill flags after register allocation,
and targets using register scavenging benefit. Conservative kill flags are not
enough.

llvm-svn: 117960
 2010-11-01 21:51:31 +00:00
Jakob Stoklund Olesen
78ba455b51 Update kill flags while rewriting instructions after splitting. 
llvm-svn: 117959
 2010-11-01 21:51:29 +00:00
Bill Wendling
69e7c09c32 Move the machine operand MC encoding patterns to the parent classes. 
llvm-svn: 117956
 2010-11-01 21:17:06 +00:00
Owen Anderson
47f0efad86 When folding away a (shl (shr)) pair, we need to check that the bits that will BECOME the low 
bits are zero, not that the current low bits are zero.  Fixes <rdar://problem/8606771>.

llvm-svn: 117953
 2010-11-01 21:08:20 +00:00
Chris Lattner
b0ac93cf15 use our fancy new MnemonicAlias mechanism to remove a bunch of hacks 
from X86AsmParser.cpp

llvm-svn: 117952
 2010-11-01 21:06:34 +00:00
Bill Wendling
4340c9449a When we look at instructions to convert to setting the 's' flag, we need to look 
at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.

llvm-svn: 117950
 2010-11-01 20:41:43 +00:00
Jakob Stoklund Olesen
66012df062 Don't assign new registers created during a split to the same stack slot, but 
give them individual stack slots once the are actually spilled.

llvm-svn: 117945
 2010-11-01 19:49:57 +00:00
Jakob Stoklund Olesen
b4a55702b7 Add basic LiveStacks verification. 
When an instruction refers to a spill slot with a LiveStacks entry, check that
the spill slot is live at the instruction.

llvm-svn: 117944
 2010-11-01 19:49:52 +00:00
Bob Wilson
a9c593e696 NEON does not support truncating vector stores. Radar 8598391. 
llvm-svn: 117940
 2010-11-01 18:31:39 +00:00
Jim Grosbach
acc28d1b2a Add FIXME. 
llvm-svn: 117936
 2010-11-01 18:11:14 +00:00
Jim Grosbach
53d2661c60 Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates 
codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931
 2010-11-01 17:08:58 +00:00
Rafael Espindola
2f114f8430 Write the line info to .debug_line. 
llvm-svn: 117930
 2010-11-01 17:07:14 +00:00
Jim Grosbach
76910aa62f Mark ARM subtarget features that are available for the assembler. 
llvm-svn: 117929
 2010-11-01 16:59:54 +00:00
Jim Grosbach
2605b2b54f trailing whitespace 
llvm-svn: 117927
 2010-11-01 16:44:21 +00:00
Rafael Espindola
5571ce5ed4 Move EmitInstruction to MCObjectStreamer so that ELF and MachO can share it. 
llvm-svn: 117925
 2010-11-01 16:27:31 +00:00
Jim Grosbach
311aa5e22f The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the 
patterns as such

llvm-svn: 117923
 2010-11-01 15:59:52 +00:00
Rafael Espindola
a7f92c500c Add support for .value. 
llvm-svn: 117922
 2010-11-01 15:29:07 +00:00
Rafael Espindola
7a38cb0144 Implement .weakref. 
llvm-svn: 117911
 2010-11-01 14:28:48 +00:00
Bill Wendling
da3d0ce7b5 Move instruction encoding bits into the parent class and remove the temporary 
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.

llvm-svn: 117906
 2010-11-01 06:00:39 +00:00
Bill Wendling
70856991c5 The testcase is now XFAILed. Sorry about the breakage. 
llvm-svn: 117904
 2010-11-01 05:50:55 +00:00
Chris Lattner
d595d1f4d7 "mov[zs]x (mem), GR16" are not ambiguous: the mem 
must be 8 bits.  Support this memory form.

llvm-svn: 117902
 2010-11-01 05:41:10 +00:00
Chris Lattner
81d051481e Implement enough of the missing instalias support to get 
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901
 2010-11-01 05:34:34 +00:00
Chris Lattner
0a4807eefc make the asm matcher emitter reject instructions that have comments 
in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897
 2010-11-01 04:44:29 +00:00
Chris Lattner
9da275f86b reject instructions that contain a \n in their asmstring. Mark 
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884
 2010-11-01 00:46:16 +00:00
Eric Christopher
7295ed492c Revert r117876 for now, it's causing more testsuite failures. 
llvm-svn: 117879
 2010-10-31 22:42:55 +00:00
Bill Wendling
13936421e6 Disable the peephole optimizer until 186.crafty on armv6 is fixed. This is what 
looks like is happening:

Without the peephole optimizer:
  (1)   sub     r6, r6, #32
        orr     r12, r12, lr, lsl r9
        orr     r2, r2, r3, lsl r10
  (x)   cmp     r6, #0
        ldr     r9, LCPI2_10
        ldr     r10, LCPI2_11
  (2)   sub     r8, r8, #32
  (a)   movge   r12, lr, lsr r6
  (y)   cmp     r8, #0
LPC2_10:
        ldr     lr, [pc, r10]
  (b)   movge   r2, r3, lsr r8

With the peephole optimizer:
        ldr     r9, LCPI2_10
        ldr     r10, LCPI2_11
  (1*)  subs    r6, r6, #32
  (2*)  subs    r8, r8, #32
  (a*)  movge   r12, lr, lsr r6
  (b*)  movge   r2, r3, lsr r8

(1) is used by (x) for the conditional move at (a). (2) is used by (y) for the
conditional move at (b). After the peephole optimizer, these the flags resulting
from (1*) are ignored and only the flags from (2*) are considered for both
conditional moves.

llvm-svn: 117876
 2010-10-31 22:07:12 +00:00
Nicolas Geoffray
6889997474 Attach a GCModuleInfo to a MachineFunction. 
llvm-svn: 117867
 2010-10-31 20:38:38 +00:00
Chris Lattner
a4c36d0efe fix the !eq operator in tblgen to return a bit instead of an int. 
Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862
 2010-10-31 19:22:57 +00:00
Chris Lattner
5d088218e5 two changes: make the asmmatcher generator ignore ARM pseudos properly, 
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861
 2010-10-31 19:15:18 +00:00
Chris Lattner
01acd65875 reapply r117858 with apparent editor malfunction fixed (somehow I 
got a dulicated line).

llvm-svn: 117860
 2010-10-31 19:10:56 +00:00
Chris Lattner
8132a182e7 revert r117858 while I check out a failure I missed. 
llvm-svn: 117859
 2010-10-31 19:05:32 +00:00
Chris Lattner
70b05a5b88 the asm matcher can't handle operands with modifiers (like ${foo:bar}). 
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858
 2010-10-31 18:48:12 +00:00
Chris Lattner
8aaac91ca4 sketch out the planned instruction alias mechanism, add some comments about 
how the push/pop mnemonic aliases are wrong.

llvm-svn: 117857
 2010-10-31 18:43:46 +00:00
Duncan Sands
92f33ea784 Factorize the duplicated logic for choosing the right argument 
calling convention out of the fast and normal ISel files, and
into the calling convention TD file.

llvm-svn: 117856
 2010-10-31 13:21:44 +00:00
Duncan Sands
0f49c49476 Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86, 
which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.

llvm-svn: 117855
 2010-10-31 13:02:38 +00:00
Rafael Espindola
660b7f5c4a Add support for files with more than 65280 sections. No testcase since 
it would be a bit too big :-)

llvm-svn: 117849
 2010-10-31 00:16:26 +00:00
Eric Christopher
e012ee8db9 Make sure we have a legal type (and simple) before continuing. 
llvm-svn: 117848
 2010-10-30 21:25:26 +00:00
Chris Lattner
49227ad505 Resolve a terrible hack in tblgen: instead of hardcoding 
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.

llvm-svn: 117831
 2010-10-30 19:38:20 +00:00
Chris Lattner
15e92ddd01 Implement (and document!) support for MnemonicAlias's to have Requires 
directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.

llvm-svn: 117830
 2010-10-30 19:23:13 +00:00
Chris Lattner
441672d7cb really zap alias. 
llvm-svn: 117824
 2010-10-30 18:23:25 +00:00
Chris Lattner
ba9271be5b move fcompi alias to .td file and zap some useless code. 
llvm-svn: 117823
 2010-10-30 18:22:53 +00:00
Chris Lattner
1b3b2e113f move rep aliases to td file 
llvm-svn: 117822
 2010-10-30 18:17:33 +00:00
Chris Lattner
49f977366f move sal aliases to .td file. 
llvm-svn: 117821
 2010-10-30 18:14:54 +00:00
Chris Lattner
54892b4d8d fix an encoding mismatch where "sal %eax, 1" was not using the short encoding 
for shl.  Caught by inspection.

llvm-svn: 117820
 2010-10-30 18:13:10 +00:00
Chris Lattner
38179edecd move a bunch more aliases from .cpp -> .td file. 
llvm-svn: 117819
 2010-10-30 18:07:17 +00:00
Chris Lattner
ac7f4957b1 move cmov aliases to .td file. 
llvm-svn: 117818
 2010-10-30 17:56:50 +00:00
Chris Lattner
acec7b7d46 move setcc and jcc aliases from .cpp to .td 
llvm-svn: 117817
 2010-10-30 17:51:45 +00:00