RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-23 04:52:54 +02:00
Code Issues Projects Releases Wiki Activity
35,969 Commits 4 Branches 5 Tags 704 MiB
ad9a6ccb83
Commit Graph

147 Commits

Author SHA1 Message Date
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Evan Cheng
64a1febf9a Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. 
llvm-svn: 44960
 2007-12-12 23:12:09 +00:00
Andrew Lenharth
6e449dc482 something wrong with this opt 
llvm-svn: 44370
 2007-11-27 18:31:30 +00:00
Bill Wendling
934fcd87e7 Unifacalize the CALLSEQ{START,END} stuff. 
llvm-svn: 44045
 2007-11-13 09:19:02 +00:00
Bill Wendling
cc75435ebf Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack 
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).

This can only result in tears...

llvm-svn: 44037
 2007-11-13 00:44:25 +00:00
Owen Anderson
aba398a5ce Add a flag for indirect branch instructions. 
Target maintainers: please check that the instructions for your target are correctly marked.

llvm-svn: 44012
 2007-11-12 07:39:39 +00:00
Evan Cheng
b43255bc68 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
llvm-svn: 41863
 2007-09-11 19:55:27 +00:00
Evan Cheng
53cb03b583 No more noResults. 
llvm-svn: 40132
 2007-07-21 00:34:19 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Andrew Lenharth
c894d4e3ce Use this nifty Constraints thing and fix the inverted conditional moves 
llvm-svn: 36191
 2007-04-17 04:07:59 +00:00
Andrew Lenharth
42ced99f24 FTOIT and ITOFT are bit converts, and if we drop 21264s, are always available 
llvm-svn: 33492
 2007-01-24 21:09:16 +00:00
Andrew Lenharth
8261b94b09 Be sure to grab weak functions too, and make implicit defs comments 
llvm-svn: 32308
 2006-12-07 17:39:14 +00:00
Chris Lattner
13ae6835d9 silence warnings. 
llvm-svn: 31394
 2006-11-03 01:18:29 +00:00
Andrew Lenharth
c43c2d6966 fix 2006-11-01-vastart.ll 
llvm-svn: 31371
 2006-11-02 03:05:26 +00:00
Andrew Lenharth
92b6c807c7 more shotenning 
llvm-svn: 31331
 2006-10-31 23:46:56 +00:00
Andrew Lenharth
cc672e3b2b Let us play simplify the td file (and fix a few missed sub and mul patterns). 
llvm-svn: 31322
 2006-10-31 19:52:12 +00:00
Andrew Lenharth
c4f8836525 Add all that branch mangling niftiness 
llvm-svn: 31313
 2006-10-31 16:49:55 +00:00
Evan Cheng
fe5bb5dbe6 Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. 
llvm-svn: 30945
 2006-10-13 21:14:26 +00:00
Chris Lattner
80790cad34 adjcallstack up/down clobbers the sp 
llvm-svn: 30910
 2006-10-12 18:00:14 +00:00
Chris Lattner
b9c1ea6dcc Use cute tblgen tricks to make zap handling more powerful. Specifically, 
when the dag combiner simplifies an and mask, notice this and allow those bits
to be missing from the zap mask.

This compiles Alpha/zapnot4.ll into:

        sll $16,3,$0
        zapnot $0,3,$0
        ret $31,($26),1

instead of:

        ldah $0,1($31)
        lda $0,-8($0)
        sll $16,3,$1
        and $1,$0,$0
        ret $31,($26),1

It would be *really* nice to replace the hunk of code in the
AlphaISelDAGToDAG.cpp file that matches (and (srl (x, C), c2) into
(SRL (ZAPNOTi)) with a similar pattern, but I've spent enough time poking
at alpha.  Make andrew will do this.

llvm-svn: 30875
 2006-10-11 05:13:56 +00:00
Chris Lattner
95a8905db2 Remove dead/redundant instructions. These are handled by ZAPNOTi 
llvm-svn: 30872
 2006-10-11 04:12:39 +00:00
Evan Cheng
d22f3dd3ed Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. 
llvm-svn: 30844
 2006-10-09 20:57:25 +00:00
Andrew Lenharth
d12f2d614a catch constants more often 
llvm-svn: 30534
 2006-09-20 15:05:49 +00:00
Andrew Lenharth
5d958d3405 Jump tables on Alpha 
llvm-svn: 30463
 2006-09-18 18:01:03 +00:00
Evan Cheng
34a49551f5 CALLSEQ_* produces chain even if that's not needed. 
llvm-svn: 29603
 2006-08-11 09:03:33 +00:00
Evan Cheng
7e30f4efe7 Remove a duplicate pattern/ 
llvm-svn: 29413
 2006-07-31 18:42:49 +00:00
Andrew Lenharth
fe127f3de7 Let the alpha breakage begin. First Formals and RET. next Calls 
llvm-svn: 28753
 2006-06-12 18:09:24 +00:00
Andrew Lenharth
813c3dcf58 ignore ordered/unordered for now 
llvm-svn: 28679
 2006-06-04 00:25:51 +00:00
Andrew Lenharth
4760eaae91 support x * (c1 + c2) where c1 and c2 are pow2s. special case for c2 == 4 
llvm-svn: 27370
 2006-04-03 04:19:17 +00:00
Andrew Lenharth
af4a638eab mul by const conversion sequences. more coming soon 
llvm-svn: 27368
 2006-04-03 03:18:59 +00:00
Andrew Lenharth
f124519fc8 fcopysign for mixed mode 
llvm-svn: 26651
 2006-03-09 17:56:33 +00:00
Andrew Lenharth
e08d165146 alpha and llvm have different oppinions on which arg is the sign bit 
llvm-svn: 26647
 2006-03-09 17:41:50 +00:00
Andrew Lenharth
25de2846c5 Alpha Scheduling classes 
llvm-svn: 26643
 2006-03-09 17:16:45 +00:00
Andrew Lenharth
c180d749a2 fcopysign and get rid of dsnode cruft. custom PA runtimes make this better in some senses 
llvm-svn: 26641
 2006-03-09 14:58:25 +00:00
Andrew Lenharth
c879542ab0 isStoreToStackSlot 
llvm-svn: 25925
 2006-02-03 03:07:37 +00:00
Andrew Lenharth
9812806d03 Add immediate forms of cmov and remove some cruft 
llvm-svn: 25882
 2006-02-01 19:37:33 +00:00
Chris Lattner
7a06abe72b cmovle != cmovlt 
llvm-svn: 25761
 2006-01-29 03:47:30 +00:00
Chris Lattner
20d4194a0d PHI and INLINEASM are now built-in instructions provided by Target.td 
llvm-svn: 25674
 2006-01-27 01:46:15 +00:00
Andrew Lenharth
23afe2f288 minor renaming 
llvm-svn: 25640
 2006-01-26 03:24:15 +00:00
Andrew Lenharth
ad88ba7c98 allow R28 to be used for frame calculations without entirely removing it from circulation 
llvm-svn: 25639
 2006-01-26 03:22:07 +00:00
Andrew Lenharth
f7d549848c added stores to lsmark 
llvm-svn: 25552
 2006-01-23 21:51:33 +00:00
Andrew Lenharth
85b5ef30e5 fix up more lsmark stuff 
llvm-svn: 25550
 2006-01-23 21:23:26 +00:00
Andrew Lenharth
b7a4322232 yea, lowering this stuff will basically work 
llvm-svn: 25549
 2006-01-23 20:59:50 +00:00
Andrew Lenharth
96520cb68d typo 
llvm-svn: 25464
 2006-01-19 21:10:38 +00:00
Andrew Lenharth
9abecccdcb nasty nasty patterns 
llvm-svn: 25463
 2006-01-19 20:49:37 +00:00
Andrew Lenharth
b2671cf884 fix short immediate loads 
llvm-svn: 25371
 2006-01-16 21:41:39 +00:00
Andrew Lenharth
09447d44ac this pattern was bogus 
llvm-svn: 25197
 2006-01-11 03:33:06 +00:00
Andrew Lenharth
0dd7d82ec6 Int immediate loading fix 
llvm-svn: 25182
 2006-01-10 19:12:47 +00:00
Andrew Lenharth
58e26e2c4b proper branch not equal sequence 
llvm-svn: 25159
 2006-01-09 19:49:58 +00:00
Chris Lattner
0bbcba6cff unbreak the build, these are now in TargetSelectionDAG.td 
llvm-svn: 25109
 2006-01-05 04:48:15 +00:00