Jim Grosbach
ade39d38e1
Clean up formatting a bit.
...
llvm-svn: 137393
2011-08-11 23:57:17 +00:00
Jim Grosbach
d17df06881
ARM vector compare to zero instruction assembly parsing support.
...
llvm-svn: 137389
2011-08-11 23:51:13 +00:00
Jim Grosbach
41ef68eb17
Fix tests per now-correct encoding as of r137371.
...
llvm-svn: 137376
2011-08-11 22:31:48 +00:00
Jim Grosbach
edefbb31c3
ARM STRT assembly parsing and encoding.
...
llvm-svn: 137372
2011-08-11 22:18:00 +00:00
Jim Grosbach
ed8a320007
ARM load shifted register pre-index fix shift value asm parser encoding.
...
llvm-svn: 137367
2011-08-11 22:05:09 +00:00
Jim Grosbach
609316e481
ARM STRHT assembly parsing and encoding.
...
llvm-svn: 137358
2011-08-11 21:39:41 +00:00
Jim Grosbach
5c12d41c95
ARM STRH assembly parsing and encoding.
...
llvm-svn: 137353
2011-08-11 21:17:22 +00:00
Owen Anderson
4618d77bcd
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
...
llvm-svn: 137347
2011-08-11 20:47:56 +00:00
Owen Anderson
1ec4fcb5d3
Improve operand validation for Thumb2 addressing modes.
...
llvm-svn: 137344
2011-08-11 20:40:40 +00:00
Jim Grosbach
81b2835f83
ARM STRD assembly parsing and encoding.
...
llvm-svn: 137342
2011-08-11 20:28:23 +00:00
Owen Anderson
73e7d34732
Continue to tighten decoding by performing more operand validation.
...
llvm-svn: 137340
2011-08-11 20:21:46 +00:00
Jim Grosbach
bfc85134c2
ARM STRBT assembly parsing and encoding.
...
llvm-svn: 137337
2011-08-11 20:04:56 +00:00
Jim Grosbach
87f0f921b5
Add FIXME.
...
llvm-svn: 137336
2011-08-11 19:43:42 +00:00
Jim Grosbach
a6572a1201
ARM STRB assembly parsing and encoding tests.
...
llvm-svn: 137335
2011-08-11 19:42:58 +00:00
Jim Grosbach
9673dc9e01
Fix a copy/paste error so that LDRB(register) actually gets tested.
...
llvm-svn: 137333
2011-08-11 19:34:23 +00:00
Jim Grosbach
986a3eb0b2
ARM STR(register) assembly parsing and encoding tests.
...
llvm-svn: 137332
2011-08-11 19:26:17 +00:00
Jim Grosbach
e6bd3a1ab8
ARM STR(immediate) assembly parsing and encoding.
...
llvm-svn: 137331
2011-08-11 19:22:40 +00:00
Owen Anderson
63ccfdccd1
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
...
llvm-svn: 137325
2011-08-11 19:00:18 +00:00
Owen Anderson
decc5fcced
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
...
llvm-svn: 137323
2011-08-11 18:55:42 +00:00
Owen Anderson
707fcaca0e
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
...
llvm-svn: 137322
2011-08-11 18:41:59 +00:00
Owen Anderson
8d6b9f063f
Improve error checking in the new ARM disassembler. Patch by James Molloy.
...
llvm-svn: 137320
2011-08-11 18:24:51 +00:00
Jim Grosbach
9717a9c0d3
ARM push of a single register encodes as pre-indexed STR.
...
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
llvm-svn: 137318
2011-08-11 18:07:11 +00:00
Jim Grosbach
abaaf4513f
ARM pop of a single register encodes as post-indexed LDR.
...
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
llvm-svn: 137316
2011-08-11 17:35:48 +00:00
Jim Grosbach
eb96dd6c99
ARM tests for LDRSHT assembly parsing and encoding.
...
llvm-svn: 137274
2011-08-10 23:18:30 +00:00
Jim Grosbach
e2cc6866d1
ARM tests for LDRSH assembly parsing and encoding.
...
llvm-svn: 137272
2011-08-10 23:12:25 +00:00
Jim Grosbach
f65a625648
ARM tests for LDRSBT assembly parsing and encoding.
...
llvm-svn: 137271
2011-08-10 23:08:56 +00:00
Jim Grosbach
e22ad37645
ARM tests for LDRSB assembly parsing and encoding.
...
llvm-svn: 137270
2011-08-10 23:06:44 +00:00
Jim Grosbach
f291232aa1
Add FIXME.
...
llvm-svn: 137265
2011-08-10 22:56:43 +00:00
Jim Grosbach
5c5f1c8305
ARM tests for LDRHT assembly parsing and encoding.
...
llvm-svn: 137263
2011-08-10 22:55:38 +00:00
Jim Grosbach
7c1596bf26
ARM tests for LDRH(register) assembly parsing and encoding.
...
llvm-svn: 137261
2011-08-10 22:45:42 +00:00
Jim Grosbach
e0ccd6b34e
ARM LDRH(immediate) assembly parsing and encoding support.
...
llvm-svn: 137260
2011-08-10 22:42:16 +00:00
Jim Grosbach
e0c10a6d0c
Add FIXME
...
llvm-svn: 137258
2011-08-10 22:20:38 +00:00
Jim Grosbach
4ad2dc8bb2
ARM LDRD(register) assembly parsing and encoding.
...
Add support for literal encoding of #-0 along the way.
llvm-svn: 137254
2011-08-10 21:56:18 +00:00
Jim Grosbach
bbef0044c8
ARM LDRD(immediate) assembly parsing and encoding support.
...
llvm-svn: 137244
2011-08-10 20:29:19 +00:00
Owen Anderson
0fde7a84ee
Add initial support for decoding NEON instructions in Thumb2 mode.
...
llvm-svn: 137236
2011-08-10 19:01:10 +00:00
Owen Anderson
87b5ce880a
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
...
llvm-svn: 137189
2011-08-10 00:03:03 +00:00
Owen Anderson
b717d71aa1
Tighten operand checking of register-shifted-register operands.
...
llvm-svn: 137180
2011-08-09 23:33:27 +00:00
Owen Anderson
62faf296dd
Tighten operand checking on memory barrier instructions.
...
llvm-svn: 137176
2011-08-09 23:25:42 +00:00
Owen Anderson
869ce85500
Tighten operand checking on CPS instructions.
...
llvm-svn: 137172
2011-08-09 23:05:39 +00:00
Owen Anderson
8ad37f68a2
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
...
llvm-svn: 137168
2011-08-09 22:48:45 +00:00
Benjamin Kramer
ca48bdfd5b
ARM Disassembler: sign extend branch immediates.
...
Not sure about BLXi, but this is what the old disassembler did.
llvm-svn: 137156
2011-08-09 22:02:50 +00:00
Owen Anderson
2aa4c7e391
Tighten Thumb1 branch predicate decoding.
...
llvm-svn: 137146
2011-08-09 21:07:45 +00:00
Owen Anderson
ffe1c55752
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
...
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
llvm-svn: 137144
2011-08-09 20:55:18 +00:00
Jim Grosbach
d6da18cf19
ARM parsing and encoding for LDRBT instruction.
...
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.
llvm-svn: 137074
2011-08-08 23:28:47 +00:00
Jim Grosbach
dce26073db
ARM parsing and encoding for LDRB instruction.
...
llvm-svn: 137071
2011-08-08 22:37:06 +00:00
Jim Grosbach
1dbe50798e
Add FIXME.
...
llvm-svn: 137070
2011-08-08 22:11:33 +00:00
Jim Grosbach
00c4316907
ARM load instruction shifted register index operands.
...
Parsing and encoding for shifted index operands for load instructions.
llvm-svn: 136986
2011-08-05 22:03:36 +00:00
Jim Grosbach
40a7e379c4
ARM indexed load assembly parsing and encoding.
...
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.
llvm-svn: 136982
2011-08-05 21:28:30 +00:00
Jim Grosbach
861430e0bb
Add ARM LDR parsing tests.
...
llvm-svn: 136977
2011-08-05 20:33:39 +00:00
Rafael Espindola
b16f4e78a4
Fix the bitwidth of the remaining fields.
...
llvm-svn: 136884
2011-08-04 17:00:11 +00:00