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107 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
83d2cfd6cd Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704
 2010-05-26 17:27:12 +00:00
Jakob Stoklund Olesen
0fefdf4d2a Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." 
This reverts commit 104654.

llvm-svn: 104660
 2010-05-26 01:21:14 +00:00
Jakob Stoklund Olesen
a2f0c34e41 Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104654
 2010-05-26 00:28:19 +00:00
Jakob Stoklund Olesen
696fbed514 Remove NumberHack entirely. 
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.

llvm-svn: 104627
 2010-05-25 19:49:33 +00:00
Jakob Stoklund Olesen
d1f4d14609 Switch SubRegSet to using symbolic SubRegIndices 
llvm-svn: 104571
 2010-05-24 23:03:18 +00:00
Jakob Stoklund Olesen
3a19b732d8 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data 
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

llvm-svn: 104563
 2010-05-24 21:46:58 +00:00
Jakob Stoklund Olesen
f40bb16b94 Rename X86 subregister indices to something shorter. 
Use the tablegen-produced enums.

llvm-svn: 104493
 2010-05-24 14:48:17 +00:00
Jakob Stoklund Olesen
9a54fec092 Add the SubRegIndex TableGen class. 
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

llvm-svn: 104492
 2010-05-24 14:48:12 +00:00
Sean Callanan
4331428e24 Eliminated the classification of control registers into %ecr_ 
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196
 2010-05-06 20:59:00 +00:00
Jim Grosbach
0c336a7923 Fix PR6696 and PR6663 
When a frame pointer is not otherwise required, and dynamic stack alignment
is necessary solely due to the spilling of a register with larger alignment
requirements than the default stack alignment, the frame pointer can be both
used as a general purpose register and a frame pointer. That goes poorly, for
obvious reasons. This patch brings back a bit of old logic for identifying
the use of such registers and conservatively reserves the frame pointer
during register allocation in such cases.

For now, implement for X86 only since it's 32-bit linux which is hitting this,
and we want a targeted fix for 2.7. As a follow-on, this will be expanded
to handle other targets, as theoretically the problem could arise elsewhere
as well.

llvm-svn: 100559
 2010-04-06 20:26:37 +00:00
Evan Cheng
7d8c39bb1c Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions. 
llvm-svn: 98465
 2010-03-14 03:48:46 +00:00
Dan Gohman
3177cfd002 Implement XMM subregs. 
Extracting the low element of a vector is now done with EXTRACT_SUBREG,
and the zero-extension performed by load movss is now modeled with
SUBREG_TO_REG, and so on.

Register-to-register movss and movsd are no longer considered copies;
they are two-address instructions which insert a scalar into a vector.

llvm-svn: 97354
 2010-02-28 00:17:42 +00:00
Dan Gohman
124de89a93 Remove SIL, DIL, and BPL from the GR8_NOREX allocation order also. 
llvm-svn: 94560
 2010-01-26 18:30:24 +00:00
Dan Gohman
9fe369e610 SIL, DIL, BPL, and SPL require a REX prefix. 
llvm-svn: 94558
 2010-01-26 18:14:22 +00:00
Sean Callanan
06b6feb2e1 Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier

llvm-svn: 91638
 2009-12-18 00:01:26 +00:00
Dan Gohman
b38864fb37 Add RIP to GR64_NOREX. This fixed a MachineVerifier error when RIP 
is used in an operand which requires GR64_NOREX.

llvm-svn: 83307
 2009-10-05 15:42:08 +00:00
Sean Callanan
3386a02b81 Added a new register class for segment registers 
to the Intel register table.
Added 16- and 64-bit MOVs to and from the segment
registers to the Intel instruction tables.

llvm-svn: 81895
 2009-09-15 18:47:29 +00:00
Dan Gohman
0caa78bc21 Minor whitespace tidiness. 
llvm-svn: 77602
 2009-07-30 17:04:07 +00:00
Dan Gohman
0a16a3ee84 Rename GRAD to GR32_AD, to follow the naming convention of other 
classes. And define its SubRegClassList.

llvm-svn: 77601
 2009-07-30 17:02:08 +00:00
Dan Gohman
3c7e8160f6 Add a new register class to describe operands that can't be SP, 
due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.

llvm-svn: 77565
 2009-07-30 01:56:29 +00:00
Dan Gohman
179f1e8a27 Eliminate a bunch of redundant tables. 
llvm-svn: 77558
 2009-07-30 00:40:42 +00:00
Dan Gohman
79565c910c Use array_endof instead of doing it manually. 
llvm-svn: 77553
 2009-07-30 00:10:18 +00:00
David Greene
0bf8cb7487 Add a 256-bit register class and YMM registers. 
llvm-svn: 74469
 2009-06-29 22:50:51 +00:00
Chris Lattner
a8ee785cef add %rip to the GR64 register class. Lets avoid allocating it to anything though! :) 
llvm-svn: 74328
 2009-06-26 21:25:00 +00:00
Dan Gohman
a241dec2fc Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these 
to precisely describe the h-register subreg register classes.
Thanks to Jakob Stoklund Olesen for spotting this and for the
initial patch!

Also, make getStoreRegOpcode and getLoadRegOpcode aware of the
needs of h registers.

llvm-svn: 70211
 2009-04-27 16:41:36 +00:00
Dan Gohman
180fa04e35 Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD, 
GR32_ABCD, and GR64_ABCD, respectively, to help describe them.

llvm-svn: 70210
 2009-04-27 16:33:14 +00:00
Dan Gohman
56227ee26e Do for GR16_NOREX what r69049 did for GR8_NOREX, to avoid trouble with 
the local register allocator.

llvm-svn: 69115
 2009-04-15 00:10:16 +00:00
Dan Gohman
1e76e65007 GR8_NOREX can contain the H registers, since they don't require 
REX prefixes.

llvm-svn: 69108
 2009-04-15 00:00:48 +00:00
Evan Cheng
b64f2c1b08 Some of GR8_NOREX registers are only available in 64-bit mode. 
llvm-svn: 69049
 2009-04-14 16:57:43 +00:00
Dan Gohman
be7227005f Implement x86 h-register extract support. 
- Add patterns for h-register extract, which avoids a shift and mask,
   and in some cases a temporary register.
 - Add address-mode matching for turning (X>>(8-n))&(255<<n), where
   n is a valid address-mode scale value, into an h-register extract
   and a scaled-offset address.
 - Replace X86's MOV32to32_ and related instructions with the new
   target-independent COPY_TO_SUBREG instruction.

On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.

These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.

llvm-svn: 68962
 2009-04-13 16:09:41 +00:00
Dan Gohman
6e6f9e3a4f Fix copy+pastos in comments. 
llvm-svn: 68958
 2009-04-13 15:28:29 +00:00
Dan Gohman
ac6a439313 List the l registers before h registers, for consistency. 
llvm-svn: 68954
 2009-04-13 15:18:42 +00:00
Rafael Espindola
7eb72dc5f2 Re-apply 68552. 
Tested by bootstrapping llvm-gcc and using that to build llvm.

llvm-svn: 68645
 2009-04-08 21:14:34 +00:00
Bill Wendling
6e702cf68c Temporarily revert r68552. This was causing a failure in the self-hosting LLVM 
builds.

--- Reverse-merging (from foreign repository) r68552 into '.':
U    test/CodeGen/X86/tls8.ll
U    test/CodeGen/X86/tls10.ll
U    test/CodeGen/X86/tls2.ll
U    test/CodeGen/X86/tls6.ll
U    lib/Target/X86/X86Instr64bit.td
U    lib/Target/X86/X86InstrSSE.td
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86RegisterInfo.cpp
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86CodeEmitter.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86InstrInfo.h
U    lib/Target/X86/X86ISelDAGToDAG.cpp
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U    lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U    lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U    lib/Target/X86/X86ISelLowering.h
U    lib/Target/X86/X86InstrInfo.cpp
U    lib/Target/X86/X86InstrBuilder.h
U    lib/Target/X86/X86RegisterInfo.td

llvm-svn: 68560
 2009-04-07 22:35:25 +00:00
Rafael Espindola
0324937229 Reduce code duplication on the TLS implementation. 
This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.

Will work on it and on X86-64 support.

llvm-svn: 68552
 2009-04-07 21:37:46 +00:00
Evan Cheng
db402a7a49 Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs. 
llvm-svn: 65996
 2009-03-04 01:41:49 +00:00
Dan Gohman
c017343459 Reformat the allocation-order arrays to a more conventional style. 
llvm-svn: 63121
 2009-01-27 19:25:38 +00:00
Stuart Hastings
545f47a2cb <rdar://problem/6351057> 
Discourage (allocate last) use of x86_64 R12 and R13 due to their
longer instruction encodings.

llvm-svn: 59644
 2008-11-19 17:19:35 +00:00
Dale Johannesen
29e1b2e9fd Remove unneeded stuff from GRAD register class. 
llvm-svn: 59311
 2008-11-14 18:10:48 +00:00
Dale Johannesen
de9fdff884 Extend InlineAsm::C_Register to allow multiple specific registers 
(actually, code already all worked, only the comment
changed).  Use this to implement 'A' constraint on x86.
Fixes PR 1779.

llvm-svn: 59266
 2008-11-13 21:52:36 +00:00
Evan Cheng
168bd3be1b Change x86 register allocation ordering to match that of gcc. Otherwise some tools get confused by prologue generated by llvm. 
llvm-svn: 58517
 2008-10-31 16:52:57 +00:00
Evan Cheng
688a8070f4 ATT asm printer just print register AsmName's instead of calling tolower on each charater of Name. This speeds it up by 10%. 
llvm-svn: 53208
 2008-07-07 22:21:06 +00:00
Dale Johannesen
fdf8fe6c03 Add v2f32 (MMX) type to X86. Support is primitive: 
load,store,call,return,bitcast.  This is enough to
make call and return work.

llvm-svn: 52691
 2008-06-24 22:01:44 +00:00
Christopher Lamb
74f4d837df Recommitting parts of r48130. These do not appear to cause the observed failures. 
llvm-svn: 48223
 2008-03-11 10:09:17 +00:00
Evan Cheng
53213ba056 In 32-bit mode, mark 64-bit GPR's as unallocatable. 
llvm-svn: 48217
 2008-03-11 07:16:00 +00:00
Chris Lattner
d393772580 Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to 
copyfromreg/copytoreg instead.

llvm-svn: 48174
 2008-03-10 21:08:41 +00:00
Evan Cheng
067ecbc341 Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests. 
llvm-svn: 48167
 2008-03-10 19:31:26 +00:00
Christopher Lamb
32e5ce3d96 Allow insert_subreg into implicit, target-specific values. 
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.

llvm-svn: 48130
 2008-03-10 06:12:08 +00:00
Chris Lattner
71189e9501 claim ST(x) registers are 80 bits, which is true. This doesn't affect 
codegen yet because these can't be spilled (they don't exist until after RA).

llvm-svn: 48098
 2008-03-09 07:49:01 +00:00
Dan Gohman
cabaec582f Rename MRegisterInfo to TargetRegisterInfo. 
llvm-svn: 46930
 2008-02-10 18:45:23 +00:00